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Regard whitespace Rev 2326 → Rev 2325

/drivers/video/drm/i915/i915_gem.c
File deleted
/drivers/video/drm/i915/i915_gem_tiling.c
File deleted
/drivers/video/drm/i915/intel_ringbuffer.h
File deleted
/drivers/video/drm/i915/i915_dma.c
File deleted
/drivers/video/drm/i915/intel_i2c.c
File deleted
/drivers/video/drm/i915/intel_drv.h
File deleted
/drivers/video/drm/i915/Gtt/intel-gtt.c
35,6 → 35,9
static bool intel_enable_gtt(void);
 
 
#define PG_SW 0x003
#define PG_NOCACHE 0x018
 
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560
46,7 → 49,43
#define AGP_USER_MEMORY (AGP_USER_TYPES)
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
 
static inline uint8_t __raw_readb(const volatile void __iomem *addr)
{
return *(const volatile uint8_t __force *) addr;
}
 
static inline uint16_t __raw_readw(const volatile void __iomem *addr)
{
return *(const volatile uint16_t __force *) addr;
}
 
static inline uint32_t __raw_readl(const volatile void __iomem *addr)
{
return *(const volatile uint32_t __force *) addr;
}
 
#define readb __raw_readb
#define readw __raw_readw
#define readl __raw_readl
 
 
static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
{ *(volatile uint8_t __force *) addr = b;}
 
static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
{ *(volatile uint16_t __force *) addr = b;}
 
static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
{ *(volatile uint32_t __force *) addr = b;}
 
static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
{ *(volatile __u64 *)addr = b;}
 
#define writeb __raw_writeb
#define writew __raw_writew
#define writel __raw_writel
#define writeq __raw_writeq
 
static inline int pci_read_config_word(struct pci_dev *dev, int where,
u16 *val)
{
761,8 → 800,3
return 1;
}
 
const struct intel_gtt *intel_gtt_get(void)
{
return &intel_private.base;
}
 
/drivers/video/drm/i915/i915_drv.c
37,11 → 37,18
#include <errno-base.h>
#include <linux/pci.h>
 
 
enum {
RCS = 0x0,
VCS,
BCS,
I915_NUM_RINGS,
};
 
 
#include "i915_drv.h"
#include <syscall.h>
 
#define PCI_VENDOR_ID_INTEL 0x8086
 
#define INTEL_VGA_DEVICE(id, info) { \
.class = PCI_CLASS_DISPLAY_VGA << 8, \
.class_mask = 0xff0000, \
81,110 → 88,7
{0, 0, 0}
};
 
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
 
void intel_detect_pch (struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pch;
 
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
* need to expose ISA bridge to let driver know the real hardware
* underneath. This is a requirement from virtualization team.
*/
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
if (pch) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
int id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
}
}
}
}
 
static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
int count;
 
count = 0;
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
udelay(10);
 
I915_WRITE_NOTRACE(FORCEWAKE, 1);
POSTING_READ(FORCEWAKE);
 
count = 0;
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
udelay(10);
}
 
/*
* Generally this is called implicitly by the register read function. However,
* if some sequence requires the GT to not power down then this function should
* be called at the beginning of the sequence followed by a call to
* gen6_gt_force_wake_put() at the end of the sequence.
*/
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
// WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 
/* Forcewake is atomic in case we get in here without the lock */
if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
__gen6_gt_force_wake_get(dev_priv);
}
 
static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
{
I915_WRITE_NOTRACE(FORCEWAKE, 0);
POSTING_READ(FORCEWAKE);
}
 
/*
* see gen6_gt_force_wake_get()
*/
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
{
// WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 
if (atomic_dec_and_test(&dev_priv->forcewake_count))
__gen6_gt_force_wake_put(dev_priv);
}
 
void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
{
if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) {
int loop = 500;
u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
udelay(10);
fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
}
// WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
dev_priv->gt_fifo_count = fifo;
}
dev_priv->gt_fifo_count--;
}
 
 
 
 
 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
 
int i915_init(void)
252,7 → 156,7
 
//int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
ret = i915_driver_load(dev, ent->driver_data );
// ret = radeon_driver_load_kms(dev, ent->driver_data );
// if (ret)
// goto err_g4;
 
/drivers/video/drm/i915/i915_drv.h
32,7 → 32,7
 
#include "i915_reg.h"
//#include "intel_bios.h"
#include "intel_ringbuffer.h"
//#include "intel_ringbuffer.h"
//#include <linux/io-mapping.h>
//#include <linux/i2c.h>
//#include <drm/intel-gtt.h>
274,17 → 274,17
void __iomem *regs;
u32 gt_fifo_count;
 
struct intel_gmbus {
struct i2c_adapter adapter;
struct i2c_adapter *force_bit;
u32 reg0;
} *gmbus;
// struct intel_gmbus {
// struct i2c_adapter adapter;
// struct i2c_adapter *force_bit;
// u32 reg0;
// } *gmbus;
 
struct pci_dev *bridge_dev;
struct intel_ring_buffer ring[I915_NUM_RINGS];
// struct intel_ring_buffer ring[I915_NUM_RINGS];
uint32_t next_seqno;
 
drm_dma_handle_t *status_page_dmah;
// drm_dma_handle_t *status_page_dmah;
// uint32_t counter;
// drm_local_map_t hws_map;
// struct drm_i915_gem_object *pwrctx;
367,7 → 367,7
// struct notifier_block lid_notifier;
 
int crt_ddc_pin;
struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
// struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
667,8 → 667,8
u32 pch_pf_pos, pch_pf_size;
int panel_t3, panel_t12;
 
struct drm_crtc *plane_to_crtc_mapping[2];
struct drm_crtc *pipe_to_crtc_mapping[2];
// struct drm_crtc *plane_to_crtc_mapping[2];
// struct drm_crtc *pipe_to_crtc_mapping[2];
// wait_queue_head_t pending_flip_queue;
bool flip_pending_is_done;
 
1209,7 → 1209,7
} else { \
val = read##y(dev_priv->regs + reg); \
} \
/* trace_i915_reg_rw(false, reg, val, sizeof(val)); */\
trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
}
 
1221,7 → 1221,7
 
#define __i915_write(x, y) \
static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
/* trace_i915_reg_rw(true, reg, val, sizeof(val));*/ \
trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__gen6_gt_wait_for_fifo(dev_priv); \
} \
/drivers/video/drm/i915/main.c
53,7 → 53,6
#define PCI_CLASS_REVISION 0x08
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
 
int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
{
70,8 → 69,7
class >>= 16;
 
if( (class == PCI_CLASS_DISPLAY_VGA) ||
(class == PCI_CLASS_BRIDGE_HOST) ||
(class == PCI_CLASS_BRIDGE_ISA))
(class == PCI_CLASS_BRIDGE_HOST) )
ret = 1;
}
return ret;
/drivers/video/drm/i915/pci.c
504,7 → 504,7
dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
dev->pci_dev.vendor,
dev->pci_dev.device,
dev->pci_dev.busnr,
dev->pci_dev.bus,
dev->pci_dev.devfn);
 
}
569,97 → 569,3
}
return NULL;
};
 
 
struct pci_dev * pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
pci_dev_t *dev;
 
for(dev = (pci_dev_t*)devices.next;
&dev->link != &devices;
dev = (pci_dev_t*)dev->link.next)
{
if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
return &dev->pci_dev;
}
return NULL;
}
 
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
pci_dev_t *dev;
 
dev = (pci_dev_t*)devices.next;
 
if(from != NULL)
{
for(; &dev->link != &devices;
dev = (pci_dev_t*)dev->link.next)
{
if( &dev->pci_dev == from)
{
dev = (pci_dev_t*)dev->link.next;
break;
};
}
};
 
for(; &dev->link != &devices;
dev = (pci_dev_t*)dev->link.next)
{
if( dev->pci_dev.class == class)
{
return &dev->pci_dev;
}
}
 
return NULL;
}
 
 
#define PIO_OFFSET 0x10000UL
#define PIO_MASK 0x0ffffUL
#define PIO_RESERVED 0x40000UL
 
#define IO_COND(addr, is_pio, is_mmio) do { \
unsigned long port = (unsigned long __force)addr; \
if (port >= PIO_RESERVED) { \
is_mmio; \
} else if (port > PIO_OFFSET) { \
port &= PIO_MASK; \
is_pio; \
}; \
} while (0)
 
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
if (port > PIO_MASK)
return NULL;
return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
}
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
resource_size_t start = pci_resource_start(dev, bar);
resource_size_t len = pci_resource_len(dev, bar);
unsigned long flags = pci_resource_flags(dev, bar);
 
if (!len || !start)
return NULL;
if (maxlen && len > maxlen)
len = maxlen;
if (flags & IORESOURCE_IO)
return ioport_map(start, len);
if (flags & IORESOURCE_MEM) {
return ioremap(start, len);
}
/* What? */
return NULL;
}
 
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
IO_COND(addr, /* nothing */, iounmap(addr));
}