/drivers/video/Intel-2D/gen4_render.c |
---|
File deleted |
/drivers/video/Intel-2D/gen4_render.h |
---|
File deleted |
/drivers/video/Intel-2D/sna_render_inline.h |
---|
File deleted |
/drivers/video/Intel-2D/gen5_render.c |
---|
1062,6 → 1062,7 |
gen5_align_vertex(sna, tmp); |
return true; |
return false; |
} |
1406,7 → 1407,5 |
sna->render.max_3d_size = MAX_3D_SIZE; |
sna->render.max_3d_pitch = 1 << 18; |
sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT; |
return true; |
} |
/drivers/video/Intel-2D/gen6_render.c |
---|
42,7 → 42,7 |
#include "brw/brw.h" |
#include "gen6_render.h" |
#include "gen4_source.h" |
#include "gen4_vertex.h" |
#define NO_COMPOSITE 0 |
209,12 → 209,12 |
{ |
uint32_t src, dst; |
// src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
// dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend; |
src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
dst = GEN6_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend; |
// dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend; |
#if 0 |
/* If there's no dst alpha channel, adjust the blend op so that |
* we'll treat it always as 1. |
1836,6 → 1836,10 |
gen6_magic_ca_pass(sna, op); |
} |
if (op->mask.bo) |
kgem_bo_destroy(&sna->kgem, op->mask.bo); |
if (op->src.bo) |
kgem_bo_destroy(&sna->kgem, op->src.bo); |
// sna_render_composite_redirect_done(sna, op); |
} |
2704,7 → 2708,8 |
tmp->dst.format = PICT_x8r8g8b8; |
tmp->src.repeat = SAMPLER_EXTEND_NONE; |
tmp->src.repeat = RepeatNone; |
tmp->src.filter = PictFilterNearest; |
tmp->src.is_affine = true; |
tmp->src.bo = src_bo; |
2713,12 → 2718,6 |
tmp->src.width = src->drawable.width; |
tmp->src.height = src->drawable.height; |
if ( (tmp->src.width == width) && |
(tmp->src.height == height) ) |
tmp->src.filter = SAMPLER_FILTER_NEAREST; |
else |
tmp->src.filter = SAMPLER_FILTER_BILINEAR; |
tmp->is_affine = tmp->src.is_affine; |
tmp->has_component_alpha = false; |
tmp->need_magic_ca_pass = false; |
3495,8 → 3494,6 |
sna->render.max_3d_size = GEN6_MAX_SIZE; |
sna->render.max_3d_pitch = 1 << 18; |
sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT; |
return true; |
} |
/drivers/video/Intel-2D/gen7_render.c |
---|
255,7 → 255,6 |
src = GEN7_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
dst = GEN7_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend; |
#if 0 |
/* If there's no dst alpha channel, adjust the blend op so that |
* we'll treat it always as 1. |
1358,14 → 1357,6 |
} |
} |
fastcall static void |
gen7_render_composite_blt(struct sna *sna, |
const struct sna_composite_op *op, |
const struct sna_composite_rectangles *r) |
{ |
gen7_get_rectangles(sna, op, 1, gen7_emit_composite_state); |
op->prim_emit(sna, op, r); |
} |
static uint32_t |
gen7_composite_create_blend_state(struct sna_static_stream *stream) |
{ |
1399,6 → 1390,14 |
} |
fastcall static void |
gen7_render_composite_blt(struct sna *sna, |
const struct sna_composite_op *op, |
const struct sna_composite_rectangles *r) |
{ |
gen7_get_rectangles(sna, op, 1, gen7_emit_composite_state); |
op->prim_emit(sna, op, r); |
} |
static void gen7_render_composite_done(struct sna *sna, |
const struct sna_composite_op *op) |
1503,93 → 1502,6 |
static void gen7_render_flush(struct sna *sna) |
{ |
gen4_vertex_close(sna); |
1598,6 → 1510,8 |
assert(sna->render.vertex_offset == 0); |
} |
static void |
gen7_render_context_switch(struct kgem *kgem, |
int new_mode) |
1679,6 → 1593,7 |
return (DEVICE_ID(sna->PciInfo) & 0xf) == 0x6; |
} |
static bool gen7_render_setup(struct sna *sna) |
{ |
struct gen7_render_state *state = &sna->render_state.gen7; |
1765,6 → 1680,7 |
return state->general_bo != NULL; |
} |
bool gen7_render_init(struct sna *sna) |
{ |
if (!gen7_render_setup(sna)) |
1782,8 → 1698,6 |
sna->render.max_3d_size = GEN7_MAX_SIZE; |
sna->render.max_3d_pitch = 1 << 18; |
sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT; |
return true; |
} |
/drivers/video/Intel-2D/sna.c |
---|
10,16 → 10,6 |
static struct sna_fb sna_fb; |
static struct kgem_bo *mask_bo; |
static int mask_width, mask_height; |
static inline void delay(uint32_t time) |
{ |
__asm__ __volatile__( |
"int $0x40" |
::"a"(5), "b"(time) |
:"memory"); |
}; |
typedef struct __attribute__((packed)) |
{ |
unsigned handle; |
106,7 → 96,7 |
sna->render.active = 0; |
} |
int sna_accel_init(struct sna *sna) |
bool sna_accel_init(struct sna *sna) |
{ |
const char *backend; |
132,12 → 122,15 |
} else if (sna->info->gen >= 050) { |
if (gen5_render_init(sna)) |
backend = "Ironlake"; |
} else if (sna->info->gen >= 040) { |
/* } else if (sna->info->gen >= 040) { |
if (gen4_render_init(sna)) |
backend = "Broadwater/Crestline"; |
/* } else if (sna->info->gen >= 030) { |
} else if (sna->info->gen >= 030) { |
if (gen3_render_init(sna)) |
backend = "gen3"; */ |
backend = "gen3"; |
} else if (sna->info->gen >= 020) { |
if (gen2_render_init(sna)) |
backend = "gen2"; */ |
} |
DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
163,12 → 156,10 |
DBG(("%s\n", __FUNCTION__)); |
sna = malloc(sizeof(*sna)); |
sna = malloc(sizeof(struct sna)); |
if (sna == NULL) |
return 0; |
return false; |
memset(sna, 0, sizeof(*sna)); |
io.handle = service; |
io.io_code = SRV_GET_PCI_INFO; |
io.input = &device; |
177,10 → 168,7 |
io.out_size = 0; |
if (call_service(&io)!=0) |
{ |
free(sna); |
return 0; |
}; |
return false; |
sna->PciInfo = &device; |
187,8 → 175,6 |
sna->info = intel_detect_chipset(sna->PciInfo); |
kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
delay(10); |
/* |
if (!xf86ReturnOptValBool(sna->Options, |
OPTION_RELAXED_FENCING, |
216,24 → 202,9 |
sna->flags = 0; |
sna_accel_init(sna); |
delay(10); |
return sna->render.caps; |
return sna_accel_init(sna); |
} |
void sna_fini() |
{ |
if( sna_device ) |
{ |
sna_device->render.fini(sna_device); |
kgem_bo_destroy(&sna_device->kgem, mask_bo); |
kgem_close_batches(&sna_device->kgem); |
kgem_cleanup_cache(&sna_device->kgem); |
}; |
} |
#if 0 |
static bool sna_solid_cache_init(struct sna *sna) |
440,16 → 411,6 |
}; |
void sna_destroy_bitmap(bitmap_t *bitmap) |
{ |
struct kgem_bo *bo; |
bo = (struct kgem_bo *)bitmap->handle; |
kgem_bo_destroy(&sna_device->kgem, bo); |
}; |
void sna_lock_bitmap(bitmap_t *bitmap) |
{ |
struct kgem_bo *bo; |
463,12 → 424,18 |
int sna_create_mask() |
{ |
struct kgem_bo *bo; |
char proc_info[1024]; |
int width, height; |
int i; |
printf("%s width %d height %d\n", __FUNCTION__, sna_fb.width, sna_fb.height); |
get_proc_info(proc_info); |
bo = kgem_create_2d(&sna_device->kgem, sna_fb.width, sna_fb.height, |
width = *(uint32_t*)(proc_info+42)+1; |
height = *(uint32_t*)(proc_info+46)+1; |
printf("%s width %d height %d\n", __FUNCTION__, width, height); |
bo = kgem_create_2d(&sna_device->kgem, width, height, |
8,I915_TILING_NONE, CREATE_CPU_MAP); |
if(bo == NULL) |
481,8 → 448,6 |
memset(map, 0, bo->pitch * height); |
mask_bo = bo; |
mask_width = width; |
mask_height = height; |
return 0; |
539,14 → 504,6 |
winw = *(uint32_t*)(proc_info+42)+1; |
winh = *(uint32_t*)(proc_info+46)+1; |
VG_CLEAR(update); |
update.handle = mask_bo->handle; |
// update.bo_size = __kgem_bo_size(mask_bo); |
// update.bo_pitch = mask_bo->pitch; |
update.bo_map = (__u32)MAP(mask_bo->map); |
drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
mask_bo->pitch = update.bo_pitch; |
memset(&src, 0, sizeof(src)); |
memset(&dst, 0, sizeof(dst)); |
memset(&mask, 0, sizeof(dst)); |
560,8 → 517,8 |
dst.drawable.height = sna_fb.height; |
mask.drawable.bitsPerPixel = 8; |
mask.drawable.width = update.width; |
mask.drawable.height = update.height; |
mask.drawable.width = winw; |
mask.drawable.height = winh; |
memset(&composite, 0, sizeof(composite)); |
593,6 → 550,13 |
composite.done(sna_device, &composite); |
}; |
VG_CLEAR(update); |
update.handle = mask_bo->handle; |
update.bo_size = __kgem_bo_size(mask_bo); |
update.bo_pitch = mask_bo->pitch; |
update.bo_map = MAP(mask_bo->map); |
drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update); |
kgem_submit(&sna_device->kgem); |
return 0; |
/drivers/video/Intel-2D/sna.h |
---|
134,10 → 134,6 |
/* 4bpp formats */ |
} PictFormatShort; |
#define PIXMAN_FORMAT_A(f) (((f) >> 12) & 0x0f) |
#define PICT_FORMAT_A(f) PIXMAN_FORMAT_A(f) |
#define RepeatNone 0 |
#define RepeatNormal 1 |
#define RepeatPad 2 |
/drivers/video/Intel-2D/sna_render.h |
---|
10,10 → 10,6 |
#define GXinvalid 0xff |
#define HW_BIT_BLIT (1<<0) /* BGRX blitter */ |
#define HW_TEX_BLIT (1<<1) /* stretch blit */ |
#define HW_VID_BLIT (1<<2) /* planar and packed video */ |
struct sna; |
struct sna_glyph; |
struct sna_video; |
156,8 → 152,6 |
struct sna_render { |
int active; |
int caps; |
int max_3d_size; |
int max_3d_pitch; |
166,6 → 160,7 |
#define PREFER_GPU_RENDER 0x2 |
#define PREFER_GPU_SPANS 0x4 |
bool (*composite)(struct sna *sna, uint8_t op, |
PicturePtr dst, PicturePtr src, PicturePtr mask, |
int16_t src_x, int16_t src_y, |
/drivers/video/Intel-2D/sna_stream.c |
---|
116,6 → 116,7 |
return sna_static_stream_offsetof(stream, p.store); |
} |
unsigned |
sna_static_stream_compile_wm(struct sna *sna, |
struct sna_static_stream *stream, |
/drivers/video/Intel-2D/i915_drm.h |
---|
944,8 → 944,6 |
struct drm_i915_mask_update { |
__u32 handle; |
__u32 width; |
__u32 height; |
__u32 bo_size; |
__u32 bo_pitch; |
__u32 bo_map; |
/drivers/video/Intel-2D/kgem-sna.c |
---|
32,19 → 32,7 |
#include "sna.h" |
#include "sna_reg.h" |
static inline |
int user_free(void *mem) |
{ |
int val; |
__asm__ __volatile__( |
"int $0x40" |
:"=a"(val) |
:"a"(68),"b"(12),"c"(mem)); |
return val; |
} |
unsigned int cpu_cache_size(); |
static struct kgem_bo * |
981,7 → 969,7 |
DBG(("%s: maximum batch size? %d\n", __FUNCTION__, |
kgem->batch_size)); |
kgem->min_alignment = 16; |
kgem->min_alignment = 4; |
if (gen < 040) |
kgem->min_alignment = 64; |
1327,7 → 1315,7 |
bo->handle, kgem->vma[type].count)); |
VG(if (type) VALGRIND_MAKE_MEM_NOACCESS(MAP(bo->map), bytes(bo))); |
user_free(MAP(bo->map)); |
// munmap(MAP(bo->map), bytes(bo)); |
bo->map = NULL; |
if (!list_is_empty(&bo->vma)) { |
1339,8 → 1327,6 |
static void kgem_bo_free(struct kgem *kgem, struct kgem_bo *bo) |
{ |
DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle)); |
printf("%s: handle=%d\n", __FUNCTION__, bo->handle); |
assert(bo->refcnt == 0); |
assert(bo->exec == NULL); |
assert(!bo->snoop || bo->rq == NULL); |
1601,8 → 1587,6 |
{ |
DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle)); |
printf("%s: handle=%d\n", __FUNCTION__, bo->handle); |
assert(list_is_empty(&bo->list)); |
assert(bo->refcnt == 0); |
assert(!bo->purged); |
4214,18 → 4198,7 |
return 1; |
}; |
void kgem_close_batches(struct kgem *kgem) |
{ |
int n; |
for (n = 0; n < ARRAY_SIZE(kgem->pinned_batches); n++) { |
while (!list_is_empty(&kgem->pinned_batches[n])) { |
kgem_bo_destroy(kgem, |
list_first_entry(&kgem->pinned_batches[n], |
struct kgem_bo, list)); |
} |
} |
}; |
/drivers/video/Intel-2D/kgem.h |
---|
28,7 → 28,7 |
#ifndef KGEM_H |
#define KGEM_H |
#define HAS_DEBUG_FULL 1 |
#define HAS_DEBUG_FULL 0 |
#include <stdint.h> |
#include <stdbool.h> |
/drivers/video/Intel-2D/compiler.h |
---|
38,7 → 38,6 |
#define constant __attribute__((const)) |
#define pure __attribute__((pure)) |
#define __packed__ __attribute__((__packed__)) |
#define flatten __attribute__((flatten)) |
#else |
#define likely(expr) (expr) |
#define unlikely(expr) (expr) |
49,7 → 48,6 |
#define constant |
#define pure |
#define __packed__ |
#define flatten |
#endif |
#ifdef HAVE_VALGRIND |
/drivers/video/Intel-2D/sna_reg.h |
---|
51,7 → 51,6 |
#define XY_TEXT_IMMEDIATE_BLT ((2<<29)|(0x31<<22)|(1<<16)) |
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) |
#define XY_PAT_BLT ((2<<29)|(0x51<<22)|0x4) |
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) |
#define XY_MONO_PAT ((0x2<<29)|(0x52<<22)|0x7) |
#define XY_MONO_SRC_COPY ((0x2<<29)|(0x54<<22)|(0x6)) |