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Regard whitespace Rev 2327 → Rev 2326

/drivers/video/drm/i915/intel_bios.h
File deleted
/drivers/video/drm/i915/intel_bios.c
File deleted
/drivers/video/drm/i915/intel_opregion.c
File deleted
/drivers/video/drm/i915/intel_dp.c
File deleted
/drivers/video/drm/i915/intel_display.c
File deleted
/drivers/video/drm/i915/Gtt/intel-gtt.c
766,8 → 766,3
return &intel_private.base;
}
 
 
phys_addr_t get_bus_addr(void)
{
return intel_private.gma_bus_addr;
};
/drivers/video/drm/i915/i915_dma.c
81,68 → 81,6
return 0;
}
 
static int i915_load_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
 
ret = intel_parse_bios(dev);
if (ret)
DRM_INFO("failed to find VBIOS tables\n");
 
// intel_register_dsm_handler();
 
/* IIR "flip pending" bit means done if this bit is set */
if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
dev_priv->flip_pending_is_done = true;
 
intel_modeset_init(dev);
 
#if 0
 
ret = i915_load_gem_init(dev);
if (ret)
goto cleanup_vga_switcheroo;
 
intel_modeset_gem_init(dev);
 
ret = drm_irq_install(dev);
if (ret)
goto cleanup_gem;
 
/* Always safe in the mode setting case. */
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = 1;
 
ret = intel_fbdev_init(dev);
if (ret)
goto cleanup_irq;
 
drm_kms_helper_poll_init(dev);
 
/* We're off and running w/KMS */
dev_priv->mm.suspended = 0;
 
#endif
 
return 0;
 
cleanup_irq:
// drm_irq_uninstall(dev);
cleanup_gem:
// mutex_lock(&dev->struct_mutex);
// i915_gem_cleanup_ringbuffer(dev);
// mutex_unlock(&dev->struct_mutex);
cleanup_vga_switcheroo:
// vga_switcheroo_unregister_client(dev->pdev);
cleanup_vga_client:
// vga_client_register(dev->pdev, NULL, NULL, NULL);
out:
return ret;
}
 
 
 
static void i915_pineview_get_mem_freq(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
395,7 → 333,7
// intel_setup_mchbar(dev);
intel_setup_gmbus(dev);
 
intel_opregion_setup(dev);
// intel_opregion_setup(dev);
 
/* Make sure the bios did its job and set up vital registers */
// intel_setup_bios(dev);
446,12 → 384,15
 
intel_detect_pch(dev);
 
ret = i915_load_modeset_init(dev);
if (ret < 0) {
DRM_ERROR("failed to init modeset\n");
goto out_gem_unload;
}
 
// if (drm_core_check_feature(dev, DRIVER_MODESET)) {
// ret = i915_load_modeset_init(dev);
// if (ret < 0) {
// DRM_ERROR("failed to init modeset\n");
// goto out_gem_unload;
// }
// }
 
/* Must be done after probing outputs */
// intel_opregion_init(dev);
// acpi_video_register();
/drivers/video/drm/i915/i915_drv.c
40,12 → 40,6
#include "i915_drv.h"
#include <syscall.h>
 
unsigned int i915_lvds_downclock = 0;
int i915_vbt_sdvo_panel_type = -1;
unsigned int i915_panel_use_ssc = 1;
unsigned int i915_powersave = 1;
unsigned int i915_enable_fbc = 1;
 
#define PCI_VENDOR_ID_INTEL 0x8086
 
#define INTEL_VGA_DEVICE(id, info) { \
/drivers/video/drm/i915/i915_drv.h
31,7 → 31,7
#define _I915_DRV_H_
 
#include "i915_reg.h"
#include "intel_bios.h"
//#include "intel_bios.h"
#include "intel_ringbuffer.h"
//#include <linux/io-mapping.h>
//#include <linux/i2c.h>
43,9 → 43,6
/* General customization:
*/
 
#define I915_TILING_NONE 0
 
 
#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
 
#define DRIVER_NAME "i915"
335,7 → 332,7
int cfb_y;
// struct intel_fbc_work *fbc_work;
 
struct intel_opregion opregion;
// struct intel_opregion opregion;
 
/* overlay */
// struct intel_overlay *overlay;
363,7 → 360,7
bool initialized;
bool support;
int bpp;
struct edp_power_seq pps;
// struct edp_power_seq pps;
} edp;
bool no_aux_handshake;
 
383,7 → 380,7
// struct workqueue_struct *wq;
 
/* Display functions */
struct drm_i915_display_funcs display;
// struct drm_i915_display_funcs display;
 
/* PCH chipset type */
enum intel_pch pch_type;
663,7 → 660,7
size_t object_memory;
u32 object_count;
} mm;
struct sdvo_device_mapping sdvo_mappings[2];
// struct sdvo_device_mapping sdvo_mappings[2];
/* indicate whether the LVDS_BORDER should be enabled or not */
unsigned int lvds_border_bits;
/* Panel fitter placement and size for Ironlake+ */
685,9 → 682,9
bool busy;
u16 orig_clock;
int child_dev_num;
struct child_device_config *child_dev;
struct drm_connector *int_lvds_connector;
struct drm_connector *int_edp_connector;
// struct child_device_config *child_dev;
// struct drm_connector *int_lvds_connector;
// struct drm_connector *int_edp_connector;
 
bool mchbar_need_disable;
 
735,153 → 732,7
I915_CACHE_LLC_MLC, /* gen6+ */
};
 
struct drm_i915_gem_object {
struct drm_gem_object base;
 
/** Current space allocated to this object in the GTT, if any. */
struct drm_mm_node *gtt_space;
struct list_head gtt_list;
 
/** This object's place on the active/flushing/inactive lists */
struct list_head ring_list;
struct list_head mm_list;
/** This object's place on GPU write list */
struct list_head gpu_write_list;
/** This object's place in the batchbuffer or on the eviction list */
struct list_head exec_list;
 
/**
* This is set if the object is on the active or flushing lists
* (has pending rendering), and is not set if it's on inactive (ready
* to be unbound).
*/
unsigned int active : 1;
 
/**
* This is set if the object has been written to since last bound
* to the GTT
*/
unsigned int dirty : 1;
 
/**
* This is set if the object has been written to since the last
* GPU flush.
*/
unsigned int pending_gpu_write : 1;
 
/**
* Fence register bits (if any) for this object. Will be set
* as needed when mapped into the GTT.
* Protected by dev->struct_mutex.
*
* Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
*/
signed int fence_reg : 5;
 
/**
* Advice: are the backing pages purgeable?
*/
unsigned int madv : 2;
 
/**
* Current tiling mode for the object.
*/
unsigned int tiling_mode : 2;
unsigned int tiling_changed : 1;
 
/** How many users have pinned this object in GTT space. The following
* users can each hold at most one reference: pwrite/pread, pin_ioctl
* (via user_pin_count), execbuffer (objects are not allowed multiple
* times for the same batchbuffer), and the framebuffer code. When
* switching/pageflipping, the framebuffer code has at most two buffers
* pinned per crtc.
*
* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
* bits with absolutely no headroom. So use 4 bits. */
unsigned int pin_count : 4;
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 
/**
* Is the object at the current location in the gtt mappable and
* fenceable? Used to avoid costly recalculations.
*/
unsigned int map_and_fenceable : 1;
 
/**
* Whether the current gtt mapping needs to be mappable (and isn't just
* mappable by accident). Track pin and fault separate for a more
* accurate mappable working set.
*/
unsigned int fault_mappable : 1;
unsigned int pin_mappable : 1;
 
/*
* Is the GPU currently using a fence to access this buffer,
*/
unsigned int pending_fenced_gpu_access:1;
unsigned int fenced_gpu_access:1;
 
unsigned int cache_level:2;
 
struct page **pages;
 
/**
* DMAR support
*/
struct scatterlist *sg_list;
int num_sg;
 
/**
* Used for performing relocations during execbuffer insertion.
*/
struct hlist_node exec_node;
unsigned long exec_handle;
struct drm_i915_gem_exec_object2 *exec_entry;
 
/**
* Current offset of the object in GTT space.
*
* This is the same as gtt_space->start
*/
uint32_t gtt_offset;
 
/** Breadcrumb of last rendering to the buffer. */
uint32_t last_rendering_seqno;
struct intel_ring_buffer *ring;
 
/** Breadcrumb of last fenced GPU access to the buffer. */
uint32_t last_fenced_seqno;
struct intel_ring_buffer *last_fenced_ring;
 
/** Current tiling stride for the object, if it's tiled. */
uint32_t stride;
 
/** Record of address bit 17 of each page at last unbind. */
unsigned long *bit_17;
 
 
/**
* If present, while GEM_DOMAIN_CPU is in the read domain this array
* flags which individual pages are valid.
*/
uint8_t *page_cpu_valid;
 
/** User space pin count and filp owning the pin */
uint32_t user_pin_count;
struct drm_file *pin_filp;
 
/** for phy allocated objects */
struct drm_i915_gem_phys_object *phys_obj;
 
/**
* Number of crtcs where this object is currently the fb, but
* will be page flipped away on the next vblank. When it
* reaches 0, dev_priv->pending_flip_queue will be woken up.
*/
atomic_t pending_flip;
};
 
 
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 
/**
/drivers/video/drm/i915/intel_i2c.c
289,7 → 289,7
GPIOF,
};
struct intel_gpio *gpio;
 
ENTER();
if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
return NULL;
 
317,7 → 317,7
 
if (i2c_bit_add_bus(&gpio->adapter))
goto out_free;
 
LEAVE();
return &gpio->adapter;
 
out_free:
502,7 → 502,7
};
struct drm_i915_private *dev_priv = dev->dev_private;
int ret, i;
 
ENTER();
dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
GFP_KERNEL);
if (dev_priv->gmbus == NULL)
534,7 → 534,7
}
 
intel_i2c_reset(dev_priv->dev);
 
LEAVE();
return 0;
 
err:
/drivers/video/drm/i915/pci.c
663,184 → 663,3
IO_COND(addr, /* nothing */, iounmap(addr));
}
 
 
struct pci_bus_region {
resource_size_t start;
resource_size_t end;
};
 
static inline void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
region->start = res->start;
region->end = res->end;
}
 
static inline int pci_read_config_dword(struct pci_dev *dev, int where,
u32 *val)
{
*val = PciRead32(dev->busnr, dev->devfn, where);
return 1;
}
 
static inline int pci_write_config_dword(struct pci_dev *dev, int where,
u32 val)
{
PciWrite32(dev->busnr, dev->devfn, where, val);
return 1;
}
 
int pci_enable_rom(struct pci_dev *pdev)
{
struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
struct pci_bus_region region;
u32 rom_addr;
 
if (!res->flags)
return -1;
 
pcibios_resource_to_bus(pdev, &region, res);
pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
rom_addr &= ~PCI_ROM_ADDRESS_MASK;
rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
return 0;
}
 
void pci_disable_rom(struct pci_dev *pdev)
{
u32 rom_addr;
pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
}
 
/**
* pci_get_rom_size - obtain the actual size of the ROM image
* @pdev: target PCI device
* @rom: kernel virtual pointer to image of ROM
* @size: size of PCI window
* return: size of actual ROM image
*
* Determine the actual length of the ROM image.
* The PCI window size could be much larger than the
* actual image size.
*/
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
{
void __iomem *image;
int last_image;
 
image = rom;
do {
void __iomem *pds;
/* Standard PCI ROMs start out with these bytes 55 AA */
if (readb(image) != 0x55) {
dev_err(&pdev->dev, "Invalid ROM contents\n");
break;
}
if (readb(image + 1) != 0xAA)
break;
/* get the PCI data structure and check its signature */
pds = image + readw(image + 24);
if (readb(pds) != 'P')
break;
if (readb(pds + 1) != 'C')
break;
if (readb(pds + 2) != 'I')
break;
if (readb(pds + 3) != 'R')
break;
last_image = readb(pds + 21) & 0x80;
/* this length is reliable */
image += readw(pds + 16) * 512;
} while (!last_image);
 
/* never return a size larger than the PCI resource window */
/* there are known ROMs that get the size wrong */
return min((size_t)(image - rom), size);
}
 
 
/**
* pci_map_rom - map a PCI ROM to kernel space
* @pdev: pointer to pci device struct
* @size: pointer to receive size of pci window over ROM
*
* Return: kernel virtual pointer to image of ROM
*
* Map a PCI ROM into kernel space. If ROM is boot video ROM,
* the shadow BIOS copy will be returned instead of the
* actual ROM.
*/
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
loff_t start;
void __iomem *rom;
 
/*
* IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
* memory map if the VGA enable bit of the Bridge Control register is
* set for embedded VGA.
*/
if (res->flags & IORESOURCE_ROM_SHADOW) {
/* primary video rom always starts here */
start = (loff_t)0xC0000;
*size = 0x20000; /* cover C000:0 through E000:0 */
} else {
if (res->flags &
(IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
return (void __iomem *)(unsigned long)
pci_resource_start(pdev, PCI_ROM_RESOURCE);
} else {
/* assign the ROM an address if it doesn't have one */
// if (res->parent == NULL &&
// pci_assign_resource(pdev,PCI_ROM_RESOURCE))
return NULL;
// start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
// *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
// if (*size == 0)
// return NULL;
 
/* Enable ROM space decodes */
// if (pci_enable_rom(pdev))
// return NULL;
}
}
 
rom = ioremap(start, *size);
if (!rom) {
/* restore enable if ioremap fails */
if (!(res->flags & (IORESOURCE_ROM_ENABLE |
IORESOURCE_ROM_SHADOW |
IORESOURCE_ROM_COPY)))
pci_disable_rom(pdev);
return NULL;
}
 
/*
* Try to find the true size of the ROM since sometimes the PCI window
* size is much larger than the actual size of the ROM.
* True size is important if the ROM is going to be copied.
*/
*size = pci_get_rom_size(pdev, rom, *size);
return rom;
}
 
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
{
struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
 
if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
return;
 
iounmap(rom);
 
/* Disable again before continuing, leave enabled if pci=rom */
if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
pci_disable_rom(pdev);
}