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<title>AVRA ChangeLog</title>
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<body>
<div id="layout-banner">
<div id="layout-title">AVRA</div>
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div>
</div>
<table>
<tr valign="top">
<td id="layout-menu">
<div>&#187;<a href="index.html">Home</a></div>
<div>&#187;<a href="README.html">Readme</a></div>
<div>&#187;<a href="downloads.html">Downloads</a></div>
<div>&#187;<a href="ChangeLog.html">ChangeLog</a></div>
<div>&#187;<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div>
<div id="page-source">&#187;<a href="ChangeLog.txt">Page&nbsp;Source</a></div>
</td>
<td>
<div id="layout-content">
<div id="header">
<h1>AVRA ChangeLog</h1>
</div>
<div id="content">
<h2 id="_version_1_3_0_20100628">Version 1.3.0 (20100628)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Jerry Jacobs</p></div>
<div class="ulist"><div class="title">Additions and changes</div><ul>
<li>
<p>
Added new targets, ATtiny13A, ATtiny24/A, ATtiny44/A, ATtiny84, ATtiny2313A,
ATtiny4313, ATmega328P
</p>
</li>
<li>
<p>
Added mingw32 support for building windows binairies from linux host
</p>
</li>
<li>
<p>
Removed obsolete Dev-C++ for windows building
</p>
</li>
<li>
<p>
Updated documentation and rewritten in asciidoc markup language
</p>
</li>
</ul></div>
<div class="ulist"><div class="title">Bug fixes</div><ul>
<li>
<p>
<strong>FIXED</strong>: 1934647: Handle also <em>#</em> directives because include files don&#8217;t use <em>.</em> directives.
</p>
</li>
<li>
<p>
<strong>FIXED</strong>: 1970530: Make whitespace character possible between function name and open bracket.
</p>
</li>
<li>
<p>
<strong>FIXED</strong>: 1970630: Make line continuation possible with backslash as the last character of a line.
</p>
</li>
<li>
<p>
<strong>FIXED</strong>: 2929406: Change incorrect argument --includedir to includepath.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_2_3_20071115">Version 1.2.3 (20071115)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Burkhard Arenfeld</p></div>
<div class="ulist"><ul>
<li>
<p>
Fix bug 1697037 (Error with single character <em>;</em>)
</p>
</li>
<li>
<p>
Better check for line termination. Now a single CR or a FF generates an warning message. Code with bad CR
termination could appear, if you edit CR-LF terminated files (WIN/DOS) with linux (LF only) editors.
</p>
</li>
<li>
<p>
Add patch 1604128 from Jim Galbraith (New devices ATtiny25/45/85, small fix for ATmega8 (no jmp, call instruction))
</p>
</li>
<li>
<p>
Fix bug in handling of special tags (%HOUR% &#8230;). A % without a special tag was replaced by previous tag value.
</p>
</li>
<li>
<p>
Use a global timestamp for all functions which needs a time (pi&#8594;time).
</p>
</li>
<li>
<p>
Fix bug in handling of unknown args (E.g.: avra --abc &#8594; Segfault).
</p>
</li>
<li>
<p>
Fix segfault if .error directive without parameter is used.
</p>
</li>
<li>
<p>
Add a warning, if characters with code &gt; 127 are used in .db strings and fix listing output.
</p>
</li>
<li>
<p>
Take a look at Testcode_avra-1_2_3.asm, which demonstrate some differences between 1.2.3 and previous releases
</p>
</li>
<li>
<p>
AVR000.zip contains some header files for different devices.
</p>
</li>
<li>
<p>
Included avra binary was created with ubuntu 7.10 linux
</p>
</li>
</ul></div>
<div class="ulist"><div class="title">Bug fixes</div><ul>
<li>
<p>
<strong>FIXED</strong>: 1462900: Segfault, if error in -D parameter.
</p>
</li>
<li>
<p>
<strong>FIXED</strong>: 1742436: Error in .dseg size check.
</p>
</li>
<li>
<p>
<strong>FIXED</strong>: 1742437: Error in EEPROM presence check
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_2_2_20070511">Version 1.2.2 (20070511)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Burkhard Arenfeld</p></div>
<div class="ulist"><ul>
<li>
<p>
Check in print_msg() if filename is NULL. Avoid printing a NULL-Pointer.
</p>
</li>
<li>
<p>
Warning, if no .DEVICE was found, because address range check doesn&#8217;t work without it
</p>
</li>
<li>
<p>
Error, if more than one .DEVICE was found.
</p>
</li>
<li>
<p>
Error, if .DEVICE is after any assembled code or .ORG directive, because .DEVICE resets the address
counters and the assembler builds wrong code.
</p>
</li>
<li>
<p>
Create a list of program segments (see orglist). Every .ORG, .DEVICE, .?SEG is stored, so the
assembler now can check for overlapping segments. Now overlapped segments in Flash, Data or EEPROM memory
are detected. Very usefull, if .ORG is used to build tables or bootloader code at specific addresses.
</p>
</li>
<li>
<p>
Better check for exceeding device space in RAM, Flash or EEPROM memory. Now not the total count of
assembled memory is used, instead every assembled address range is checked.
</p>
</li>
<li>
<p>
.DSEG and .ESEG now generates an error, if device has no RAM / EEPROM.
</p>
</li>
<li>
<p>
Now a warning appears, if a .DEF name is already used as constant or label. Atmel assembler generates this
warning, too.
</p>
</li>
<li>
<p>
Fix a small bug in the example program.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_2_1_20061117">Version 1.2.1 (20061117)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Roland Riegel</p></div>
<div class="ulist"><ul>
<li>
<p>
Some of the high end AVRs use the SRAM adress range from 0x60 to 0x100 for IO extension.
Avra so far used to start with SRAM Usage at 0x60. This is now set from case by case.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_2_0_20061015">Version 1.2.0 (20061015)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Burkhard Arenfeld</p></div>
<div class="ulist"><ul>
<li>
<p>
Patch segfault, if .error is given without parameter
</p>
</li>
<li>
<p>
Patch segfault, if .device is given with an invalid parameter
</p>
</li>
<li>
<p>
Check in predef_dev() if symbol is already defined. Can happens, if someone
tries to define the symbol with the -D parameter. E.g.: <em>avra -D <em>ATMEGA8</em> Test.asm</em>
now generate error message, because <em>ATMEGA8</em> is reserved
</p>
</li>
<li>
<p>
Add .elseif directive. It&#8217;s the same like .elif. (Original Atmel assembler use .elseif
and not .elif)
</p>
</li>
<li>
<p>
In .db lines strings can now contain <em>,</em> and <em>;</em> characters.
</p>
</li>
<li>
<p>
Allow forward declaration of constants (.equ) except for .ifdef and .ifndef.
Invalid forward declarations are checked now. (In the first pass undefined Symbols in
.ifdef and .ifndef parameters are stored in a <em>blacklist</em> and checked in the second pass)
</p>
</li>
<li>
<p>
Extend the .message directive for better debugging. Now it accept not only a String.
You can use a list of expressions like in a .db directive as parameter.
</p>
</li>
<li>
<p>
The assembler <em>pass</em> variable moved into the pi struct. I deleted the pass variable from
a lot of functions.
</p>
</li>
<li>
<p>
New functions in avra.c. It was easier for me, to understand the code without the
for(label = first; &#8230;)-loops. Replaced a lot of for(label = &#8230;) -loops by one of this
functions.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_1_1_20060906">Version 1.1.1 (20060906)</h2>
<div class="sectionbody">
<div class="ulist"><ul>
<li>
<p>
right shift operator bug
</p>
</li>
<li>
<p>
LPM is supported on ATtiny26 but avra say it isn&#8217;t
</p>
</li>
<li>
<p>
bugfix for jmp/call opcode
</p>
</li>
<li>
<p>
crash due to a strcmp with null pointer when parsing the cmd line args
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_1_0_20051227">Version 1.1.0 (20051227)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
.DW defines were missing in the listfile.
</p>
</li>
<li>
<p>
Support for mega8515.
</p>
</li>
<li>
<p>
Fix for generic register names and extended macro syntax.
</p>
</li>
<li>
<p>
Makefile for lcc-win32 Compiler.
</p>
</li>
<li>
<p>
Changed "global" keyword to ".global".
</p>
</li>
<li>
<p>
Added .includepath directive that allows setting include path.
</p>
</li>
<li>
<p>
segfault when not passing any sourcefiles.
</p>
</li>
<li>
<p>
--define FOO=2 does not work as claimed by the documentation.
</p>
</li>
<li>
<p>
Added return value, indicating whether avra failed or succeded.
</p>
</li>
<li>
<p>
Added support for automake utilities. See manual for more info.
</p>
</li>
<li>
<p>
if no code is present, eeprom hex file will be written anyway.
</p>
</li>
<li>
<p>
added -W NoRegDef for suppressing Register assignment warnings.
</p>
</li>
<li>
<p>
.db values were sometimes wrong printed in lst file with 6 leading F.
</p>
</li>
<li>
<p>
Added BYTE1() function equivalent to LOW().
</p>
</li>
<li>
<p>
The character " (pharentesis) could not be use as single character like <em>"</em>
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_0_1_20040610">Version 1.0.1 (20040610)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
Added meta tags for time and date.
</p>
</li>
<li>
<p>
Expression of .elif was cutted off in list file - fixed.
</p>
</li>
<li>
<p>
.equ, .org, .defines added to list file output.
</p>
</li>
<li>
<p>
Values and expressions of .db assignemts are now listed in listfile.
</p>
</li>
<li>
<p>
Added Support for ATmega48, ATmega88 and ATmega168.
</p>
</li>
<li>
<p>
Added .include error file name print out.
</p>
</li>
<li>
<p>
Fixed seg fault that could happen while using .LIST directive with no
listfile switched on.
</p>
</li>
<li>
<p>
Error when using comments within macros that made use of sign @ fixed.
</p>
</li>
<li>
<p>
Listfile lines are now prefixed with the current segment C,D,E for
code, data and eeprom.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_1_0_0_20040214">Version 1.0.0 (20040214)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
Added support for ATtiny13 and ATtiny2313
</p>
</li>
<li>
<p>
List file command line syntax now AVRASM compatible
</p>
</li>
<li>
<p>
Map file command line syntax now AVRASM compatible
</p>
</li>
<li>
<p>
Fixed problem with limited macro label running numbers
</p>
</li>
<li>
<p>
Now multiple labels can be used within macros
</p>
</li>
<li>
<p>
Fixed error output line number for included files
</p>
</li>
<li>
<p>
code cleaned up
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_9_1_20030602">Version 0.9.1 (20030602)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
fixed code for Linux compiler
</p>
</li>
<li>
<p>
fixed nested macro labels
</p>
</li>
<li>
<p>
code cleaned up
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_9_20030523">Version 0.9 (20030523)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
Added labels to macros
</p>
</li>
<li>
<p>
Added special codes <em>dst</em> and <em>src</em>
</p>
</li>
<li>
<p>
Added directive .endmacro, only .endm was allowed so far
</p>
</li>
<li>
<p>
Added a return(0); at the end of main() to quiet the Borland C++ 5.5
compiler (Jim Galbraith)
</p>
</li>
<li>
<p>
Fixed wrong flash size calculation (Jim Galbraith)
</p>
</li>
<li>
<p>
In device.c, added ATtiny26 to struct device device_list[] (Jim Galbraith)
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_8_20030307">Version 0.8 (20030307)</h2>
<div class="sectionbody">
<div class="paragraph"><p>by Tobias Weber</p></div>
<div class="ulist"><ul>
<li>
<p>
Added new macro assembler coding facilities
</p>
</li>
<li>
<p>
Added error description for .include directives
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_7_20000217">Version 0.7 (20000217)</h2>
<div class="sectionbody">
<div class="ulist"><ul>
<li>
<p>
Added supported() function to check in a .if if a instruction is
supported (From Lesha Bogdanow &lt;<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>&gt;).
</p>
</li>
<li>
<p>
Added checking of which mnemonic that work on the different AVRs
(From Lesha Bogdanow &lt;<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>&gt;).
</p>
</li>
<li>
<p>
Added constants <em>DEVICE</em>, <em>FLASH_SIZE</em>, <em>RAM_SIZE</em> and
<em>EEPROM_SIZE</em> (From Lesha Bogdanow &lt;<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>&gt;).
</p>
</li>
<li>
<p>
Added tiny devices (From Lesha Bogdanow &lt;<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>&gt;).
</p>
</li>
<li>
<p>
Changed error on constant out of range into a warning.
</p>
</li>
<li>
<p>
Added support for instructions: (E)LPM Rd,Z(+), SPM, ESPM, BREAK,
MOVW, MULS, MULSU, FMUL, FMULS, FMULSU
</p>
</li>
<li>
<p>
Added support for new devices: ATmega8, ATmega16, ATmega32,
ATmega128, ATmega162, ATmega163, ATmega323, AT94K
</p>
</li>
<li>
<p>
Added --devices switch to list all supported devices.
</p>
</li>
<li>
<p>
Fixed bug in map file name when the name had more than one . (dot)
</p>
</li>
<li>
<p>
Added option --includedirs to add additional include dirs in
search path.
</p>
</li>
<li>
<p>
Added support for creation of intel hex 32 files to be able to
address memory above 64KB. Uses 02 records for addresses up to 1MB
and 04 record for addresses above 1MB.
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_6_20000124">Version 0.6 (20000124)</h2>
<div class="sectionbody">
<div class="ulist"><ul>
<li>
<p>
Added COFF support from Bob Harris &lt;<a href="mailto:rth@McLean.Sparta.Com">rth@McLean.Sparta.Com</a>&gt;
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_5_19990331">Version 0.5 (19990331)</h2>
<div class="sectionbody">
<div class="ulist"><ul>
<li>
<p>
Bugfix: a inline string copy did not terminate string.
</p>
</li>
<li>
<p>
Fixed bug causing --define symbol=value not to work.
</p>
</li>
<li>
<p>
Added output of memory usage.
</p>
</li>
<li>
<p>
Fixed bug when there was a { in a comment.
</p>
</li>
<li>
<p>
Fixed count for data segment.
</p>
</li>
<li>
<p>
Fix to make a forward referenced label in .db/.dw work.
</p>
</li>
<li>
<p>
Added ATmega161 and ATtiny15 in list.
</p>
</li>
<li>
<p>
rjmp and rcall now wraps around with 4k word devices.
</p>
</li>
<li>
<p>
Fixed bug when branching backwards with BRBS or BRBC
</p>
</li>
</ul></div>
</div>
<h2 id="_version_0_4_19990202">Version 0.4 (19990202)</h2>
<div class="sectionbody">
<div class="ulist"><ul>
<li>
<p>
Added support for global keyword to use on labels in macros.
</p>
</li>
<li>
<p>
Fixed get_next_token to handle commas inside ' '
</p>
</li>
<li>
<p>
Fixed bug when searching for correct macro_call, so recursive
and nested macros will work.
</p>
</li>
<li>
<p>
Now handles commas in strings.
</p>
</li>
<li>
<p>
Added fix to handle semi colon in a string.
</p>
</li>
<li>
<p>
Improved mnemonic parsing for ld and st
</p>
</li>
</ul></div>
</div>
</div>
<div id="footnotes"><hr /></div>
<div id="footer">
<div id="footer-text">
Version 1.3.0<br />
Last updated 2010-06-28 16:04:24 CEST
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/contrib/toolchain/avra/doc/Makefile
0,0 → 1,55
###
# Sourceforge helper Makefile
###
USER=jerryjacobs
HOSTNAME=shell.sourceforge.net
PROJECT=avra
HTDOCS=/home/groups/a/av/avra/htdocs
 
all: help
 
upload: htdocs_scp htdocs_chmod
 
###
# Help message
###
help:
@echo "No command specified! Available commands:"
@echo
@echo "Current settings"
@echo "----------------"
@echo " User: ${USER}"
@echo " Hostname: ${HOSTNAME}"
@echo " Project: ${PROJECT}"
@echo " Remote htdoc: ${HTDOCS}"
@echo
@echo "Shell commands"
@echo "--------------"
@echo " * shell, open a shell"
@echo " * shell_create, create a shell"
@echo
@echo "htdocs commands"
@echo "---------------"
@echo " * htdocs_scp, copy all files from current dir to remote htdocs"
@echo " * htdocs_rm, remove all files from remote htdocs"
 
###
# Shell
###
shell:
ssh ${USER},${PROJECT}@${HOSTNAME}
 
shell_create:
ssh ${USER},${PROJECT}@${HOSTNAME} create
 
###
# htdocs
###
htdocs_scp:
scp -r * ${USER}@${HOSTNAME}:${HTDOCS}
 
htdocs_chmod:
ssh ${USER}@${HOSTNAME} chmod -Rv ug+rw ${HTDOCS}/*
 
htdocs_rm:
ssh ${USER}@${HOSTNAME} rm -Rv ${HTDOCS}/*
/contrib/toolchain/avra/doc/README.html
0,0 → 1,759
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN"
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<meta name="generator" content="AsciiDoc 8.5.3" />
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<div id="layout-banner">
<div id="layout-title">AVRA</div>
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div>
</div>
<table>
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<td id="layout-menu">
<div>&#187;<a href="index.html">Home</a></div>
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<td>
<div id="layout-content">
<div id="header">
<h1>README</h1>
</div>
<div id="content">
<h2 id="_general_and_licensing_information">General and licensing information</h2>
<div class="sectionbody">
<div class="paragraph"><p>AVRA v1.3.0 - Assember for the Atmel AVR microcontroller family</p></div>
<h3 id="_licensing_information">Licensing information</h3><div style="clear:left"></div>
<div class="paragraph"><p>This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version. Please read below for for information.</p></div>
<h3 id="_disclaimer">Disclaimer</h3><div style="clear:left"></div>
<div class="paragraph"><p>This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.</p></div>
<h3 id="_gnu_general_public_license">GNU General Public License</h3><div style="clear:left"></div>
<div class="paragraph"><p>You should have received a copy of the GNU General Public License
along with this program; see the file "COPYING". If not, visit
<a href="http://www.gnu.org">http://www.gnu.org</a> or write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. You can
also contact the authors of AVRA to receive a copy of the COPYING file.</p></div>
<h3 id="_trademarks_and_copyright">Trademarks and copyright</h3><div style="clear:left"></div>
<div class="paragraph"><p>Atmel, AVR, AVR Studio, Intel, Windows are registered enterprises, brands
and registered trademarks. The mentioned companies have no relation to
AVRA and are therefore not responslible for any problems that occur when
using AVRA. Many thanks for your products, support and efforts.</p></div>
</div>
<h2 id="_introducion">Introducion</h2>
<div class="sectionbody">
<div class="paragraph"><p>AVRA is an assembler for Atmel AVR microcontrollers, and it is almost
compatible with Atmel&#8217;s own assembler AVRASM32. The programming
principles and conceptions are based on the ANSI programming language "C".</p></div>
<div class="paragraph"><p>The initial version of AVRA was written by John Anders Haugum. He released
all versions until v0.7. All later versions were released by Tobias Weber.</p></div>
<h3 id="_differences_between_avra_and_avrasm32">Differences between AVRA and AVRASM32</h3><div style="clear:left"></div>
<div class="paragraph"><p>There are some differences between the original Atmel assembler AVRASM32 and AVRA. Basically AVRA is designed to replace AVRASM32 without special changes in your current Atmel AVR Studio enviroment.
Command line options have been adapted as far as it was possible until now. Jumping to fault containing line directly by double-clicking on the error message in the output window does work as with AVRASM32.</p></div>
<h3 id="_the_differences_in_detail">The differences in detail</h3><div style="clear:left"></div>
<div class="ulist"><ul>
<li>
<p>
Support for some extra preprocessor directives.
</p>
<div class="literalblock">
<div class="content">
<pre><tt>.define, .undef, .ifdef, .ifndef, .if, .else, .endif, .elif, .elseif, .warning</tt></pre>
</div></div>
</li>
<li>
<p>
Not all command line options are supported.
Specifying an eeprom file (-e) is not supported. All eeprom data is
put out into a file called program.eep.hex and always Intel hex
format. Other hex file formats than Intel are currently not supported.
</p>
</li>
<li>
<p>
Forward references not supported for .ifdef and .ifndef directives.
This makes sure, that directives like .ifdef and .undef are working
properly. If you are familiar with the C programming language, you
should get easily into AVRA. See chapter "Programming techniques" for
more information about how to write proper code.
</p>
</li>
<li>
<p>
Enhanced macro support
AVRA has some new features for writing flexible macros. This should
increase the ability to reuse code e.g. build your own library.
</p>
</li>
<li>
<p>
Debugging support
AVRA creates a coff file everytime the assembly was sucessful. This
file allows AVR Studio or any coff compatible debugger to simulate
or emulate the program.
</p>
</li>
<li>
<p>
Meta tags for assembly time
This helps you tracking versions of your software and can also be
used to generate customer specific serial numbers.
</p>
</li>
</ul></div>
<h3 id="_compatibility">Compatibility</h3><div style="clear:left"></div>
<div class="paragraph"><p>Since AVRA is written in ANSI C, it should be possible to compile it on
most system platforms. If you have problems compiling AVRA, please leave
a message on the sourceforge message board or send a mail to the
authors of AVRA.</p></div>
</div>
<h2 id="_installation">Installation</h2>
<div class="sectionbody">
<div class="paragraph"><p>To install avra you should copy the avra-executable to an apropriate
location. To compile you should rename the appropriate makefile, and
perform a make (use smake for Amiga SAS/C, and nmake for Mickeysoft
visual c++).</p></div>
<h3 id="_linux">Linux</h3><div style="clear:left"></div>
<div class="paragraph"><p>To compile avra you need gcc and the automake utilities. These will create
a ./configure script that evaluates your system enviroment. To get the
AVRA executable, you have to issue the following commands:</p></div>
<div class="paragraph"><p>aclocal
autoconf
automake -a
./configure
make &amp;&amp; make install</p></div>
<h3 id="_amigaos">AmigaOS</h3><div style="clear:left"></div>
<div class="paragraph"><p>avra can be copied any apropriate directory. If you are using the source
distribution a <em>make install</em> will do the same.</p></div>
<h3 id="_microsoft_windows">Microsoft Windows</h3><div style="clear:left"></div>
<div class="paragraph"><p>If you received the Windows binary package, look into the \bin
directory where you can find avra.exe. This should be copied to any
apropriate location. You can also overwrite AVRASM32.EXE in your
Atmel AVR Studio. If you want to compile it yourself you could download then
OpenWatcom C/C++ Toolchain for windows and create a new project and add the C
and H files to it and compile.</p></div>
<h3 id="_apple_os_x">Apple OS X</h3><div style="clear:left"></div>
<div class="paragraph"><p>If you recieved the Apple OS X binary package, look into the bin directory this
file is compiled universal and should run on intel 32 and 64 bit and powerpc. If
you want to compile it yourself go to the src directory and invoke <tt>make -f
makefiles/Makefiles.osx</tt> and then the executable should be created.</p></div>
</div>
<h2 id="_synopsis">Synopsis</h2>
<div class="sectionbody">
<h3 id="_command_line_usage">Command line usage</h3><div style="clear:left"></div>
<div class="literalblock">
<div class="content">
<pre><tt>usage: AVRA [-f][O|M|I|G] output file type
[-o &lt;filename&gt;] output file name
[-l &lt;filename&gt;] generate list file
[-m &lt;mapfile&gt;] generate map file
[--define &lt;symbol&gt;[=&lt;value&gt;]] [--includedir &lt;dir&gt;] [--listmac]
[--max_errors &lt;number&gt;] [--devices] [--version]
[-h] [--help] general help
[-W NoRegDef] supress register redefinition warnings
&lt;file to assemble&gt;</tt></pre>
</div></div>
<h3 id="_parameter_list">Parameter list</h3><div style="clear:left"></div>
<div class="literalblock">
<div class="content">
<pre><tt>--listfile -l : Create list file
--mapfile -m : Create map file
--define -D : Define symbol.
--includedir -I : Additional include dirs.
--listmac : List macro expansion in listfile.
--max_errors : Maximum number of errors before exit
(default: 10)
--devices : List out supported devices.
--version : Version information.
--help, -h : This help text.</tt></pre>
</div></div>
<h3 id="_warning_supression">Warning supression</h3><div style="clear:left"></div>
<div class="paragraph"><p>Since avra 1.1 there is a possibility to supress certain warnings.
Currently only register reassignment warnings can be supressed.</p></div>
<div class="paragraph"><p>Example: avra -W NoRegDef</p></div>
</div>
<h2 id="_programming_techniques">Programming techniques</h2>
<div class="sectionbody">
<h3 id="_using_directives">Using directives</h3><div style="clear:left"></div>
<div class="paragraph"><p>AVRA offers a number of directives that are not part of Atmel&#8217;s
assembler. These directives should help you creating versatile code that
can be designed more modular.</p></div>
<h4 id="_directive_define">Directive .define</h4>
<div class="paragraph"><p>To define a constant, use ".define". This does the same thing as ".equ",
it is just a little more C style. Keep in mind that AVRA is not case
sensitive. Do not mix ".def" and ".define", because ".def" is used to
assign registers only. This is due to backward compatibility to Atmel&#8217;s
AVRASM32. Here is an example on how .define can be used.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.define network 1</tt></pre>
</div></div>
<div class="paragraph"><p>Now "network" is set to the value 1. You may want to assemble a specific
part of your code depeding on a define or switch setting. You can test
your defined word on existence (.ifdef and .ifndef) as well as on the
value it represents. The following code shows a way to prevent error
messages due to testing undefined constants. Conditional directives must
always end with an .endif directive.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.ifndef network
.define network 0
.endif</tt></pre>
</div></div>
<h4 id="_directive_if_and_else">Directive .if and .else</h4>
<div class="paragraph"><p>The three lines in the last example set the default value of "network".
In the next example, you see how we can use default values. If a constant
has not defined previously, it is set to zero. Now you can test wether
e.g. network support is included into the assemby process.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.if network = 1
.include "include\tcpip.asm"
.else
.include "include\dummynet.asm"
.endif</tt></pre>
</div></div>
<div class="paragraph"><p>In the second part of the above listing you see the use of .else, which
defines the part of the condition that is being executed if the equation
of the preceding .if statement is not equal. You can also use the else
statement to test another equasion. For that purpose use .elif, which
means "else if". Always close this conditional part with ".endif"</p></div>
<h4 id="_directive_error">Directive .error</h4>
<div class="paragraph"><p>This directive can be used to throw errors if a part in the code has reached
that should not be reached. The following example shows how we can stop
the assembly process if a particular value has not been previously set.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.ifndef network
.error "network is not configured!" ;the assembler stops here</tt></pre>
</div></div>
<h4 id="_directive_nolist_and_list">Directive .nolist and .list</h4>
<div class="paragraph"><p>The ouput to the list file can be paused by this two directives. After
avra discovers a .nolist while assembling, it stops output to the list file.
After a .list directive is detected, it continues the normal list file output.</p></div>
<h4 id="_directive_includepath">Directive .includepath</h4>
<div class="paragraph"><p>By default, any file that is included from within the source file must
either be a single filename or a complete absolute path. With the directive
.includepath you can set an additional include path . Furthermore you can
set as many include paths as you want. Be sure not no use same filename
in separate includes, because then it is no longer clear which one avra
should take.</p></div>
</div>
<h2 id="_using_include_files">Using include files</h2>
<div class="sectionbody">
<div class="paragraph"><p>To avoid multiple inclusions of include files, you may use some pre-
processor directives. See example file stack.asm that is being included
into the main programm file as well as in other include files.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.ifndef _STACK_ASM_
.define _STACK_ASM_</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.include "include/config.inc"</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; *** stack macro ***</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.dseg
m_stack: .byte __stack_size__
.cseg</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro stack_setup
load [v:w,m_stack + __stack_size__]
outp [SPREG,v:w]
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.endif ; avoid multiple inclusion of stack.asm</tt></pre>
</div></div>
<h3 id="_using_build_date_meta_tags">Using build date meta tags</h3><div style="clear:left"></div>
<div class="paragraph"><p>If you like to implement compiler build time and date into your
program, you can make use of some sepcial tags that avra supports.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>%MINUTE% is being replaced by the current minute (00-59)
%HOUR% is being replaced by the current hour (00-23)
%DAY% is being replaced by the current day of month (01-31)
%MONTH% is being replaced by the current month (01-12)
%YEAR% is being replaced by the current year (2004-9999)</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>buildtime: .db "Release date %DAY%.%MONTH%.%YEAR% %HOUR%:%MINUTE%"</tt></pre>
</div></div>
<div class="paragraph"><p>This line will then assembled by avra into:</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>buildtime: .db "Release date 10.05.2004 19:54"</tt></pre>
</div></div>
<div class="paragraph"><p>You may also create a self defined serial number with meta tags:</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.define serialnumber %DAY% + %MONTH%*31 + (%YEAR% - 2000) *31*12</tt></pre>
</div></div>
<div class="paragraph"><p>The %TAG% is translated before any other parsing happens. The real
output can be found in the list file.</p></div>
</div>
<h2 id="_macro_features">Macro features</h2>
<div class="sectionbody">
<div class="paragraph"><p>Sometimes you have to work with 16 bit or greater variables stored
in 8 bit registers. The enhanced macro support allows you to write short
and flexible macros that simplify access to big variables. The extended
mode is active, as soon as you use parenthesis like this "[ ]" to wrap
macro parameters.</p></div>
<h3 id="_auto_type_conversion_for_macros">Auto type conversion for macros</h3><div style="clear:left"></div>
<div class="paragraph"><p>Values representing more than 8 Bits are usualy kept in a set of byte
wide registers. To simplify 16 Bit or greater operations, I added a new
language definitions. Words can be written as r16:r17, whereas register
r16 contains the higher part and register r17 the lower part of this
16 Bit value.</p></div>
<h4 id="_macro_data_types">Macro data types</h4>
<div class="paragraph"><p>There are 3 data types that can be used. They will be added as character
separated by one underline character.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>immediate values _i
registers _8,_16,_24,_32,_40,_48,_56,_64
void parameter _v</tt></pre>
</div></div>
<div class="paragraph"><p>16 Bit Source and Destionation registers <em>dst</em> and <em>src</em></p></div>
<div class="literalblock">
<div class="content">
<pre><tt>src = YH:YL
dst = ZH:ZL</tt></pre>
</div></div>
<div class="paragraph"><p>Within the parenthesis, the two words src and dst are interpreted as YH:YL
and ZH:ZL. Normal code outside of the macro parameter parenthesis can
still make use of these special key words "src" and "dst".</p></div>
<h4 id="_examples_for_automatic_type_conversion">Examples for automatic type conversion</h4>
<div class="paragraph"><p>To simplify the parameters in the demonstration below, we need to
redefine some registers.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.def a = r16 ; general purpose registers
.def b = r17
.def c = r18
.def d = r19</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.def w = r20 ; working register
.def v = r21 ; working register</tt></pre>
</div></div>
<div class="paragraph"><p>If we substract 16 Bit values stored in a, higher byte and b, lower byte
with that in c:d, we usually have to use the following command sequence:</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>sub b,d
sbc a,c</tt></pre>
</div></div>
<div class="paragraph"><p>Now we can do the following steps to simplify 16 or more Bit manipulations</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro subs
.message "no parameters specified"
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro subs_16_16
sub @1,@3
sbc @0,@2
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro subs_16_8
sub @1,@2
sbci @0,0
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>;now we can write a 16 Bit subraction as:</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>subs [a:b,c:d]</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>;or for calculating 16 minus 8 Bit</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>subs [a:b,c]</tt></pre>
</div></div>
<h3 id="_overloading_macros">Overloading macros</h3><div style="clear:left"></div>
<div class="paragraph"><p>Like in you are used to C functions, you can write macros for different
parameter lists. If you would like to have a versatile macro, you can
specify a unique macro for each parameter situation. See the next sample.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro load</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; this message is shown if you use the macro within your code
; specifying no parameters. If your macro allows the case where
; no parameters are given, exchange .message with your code.</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.message "no parameters specified"
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; Here we define the macro "load" for the case it is being used
; with two registers as first parameter and a immediate (constant)
; value as second parameter.</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro load_16_i
ldi @0,high(@2)
ldi @1,low(@2)
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; the same case, but now with a 32 bit register value as first
; parameter</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro load_32_i
ldi @0,BYTE4(@4)
ldi @1,BYTE3(@4)
ldi @2,high(@4)
ldi @3,low(@4)
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; Now let's see how these macros are being used in the code</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>load [a:b,15] ;uses macro load_16_i to load immediate</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>load [a:b:c:d,15] ;uses macro load_32_i to load immediate</tt></pre>
</div></div>
<h3 id="_more_examples">More examples</h3><div style="clear:left"></div>
<div class="literalblock">
<div class="content">
<pre><tt>.dseg
counter .byte 2
.cseg</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro poke
.message "no parameters"
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro poke_i_16_i
ldi @1,high(@3)
sts @0+0,@1
ldi @2,low(@3)
sts @0+1,@2
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro poke_i_i
ldi w,@1
sts @0+0,w
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro poke_i_v_i
ldi w,high(@3)
sts @0+0,w
ldi w,low(@3)
sts @0+1,w
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro poke_i_v_v_v_i
ldi w,high(@3)
sts @0+0,w
ldi w,low(@3)
sts @0+1,w
ldi w,BYTE3(@3)
sts @0+2,w
ldi w,BYTE4(@3)
sts @0+3,w
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; this writes '9999' into the memory at 'counter'
; uses only the working register for transfering the values.</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>poke [counter,w:w,9999]</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; works same as above, but the transferred value '9999' is also
; kept in the pair of register a:b</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>poke [counter,a:b,9999]</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; in my design 'w' is always working reg. which implies that
; it cannot be used for normal variables. The following example
; uses poke_i_i because the parameter contains two immediate values.</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>poke [counter,9999] ;uses poke_i_i</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; to be able to choose between a 8,16 or 32 Bit operation, you just
; add a void parameter.</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>poke [counter,,9999] ;uses poke_i_v_i</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; and the same for 32 Bit pokes</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>poke [counter,,,,9999] ;uses poke_i_v_v_v_i</tt></pre>
</div></div>
<h3 id="_loops_within_macros">Loops within macros</h3><div style="clear:left"></div>
<div class="paragraph"><p>One problem you may have experienced, is that labels defined within macros
are defined twice if you call the macro for example two times. Now you can
use labels for macro loops. Loops within macros must end with <em>_%</em>. the
"%" symbol is replaced by a running number.</p></div>
<h4 id="_loop_example">Loop example</h4>
<div class="literalblock">
<div class="content">
<pre><tt>; Definition of the macro</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>.macro write_8_8
write_%:
st Z+,@0
dec @1
brne write_%
.endm</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; Use in user code</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>write [a,b]
write [c,d]</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>; After assembling this code, the result looks like this</tt></pre>
</div></div>
<div class="literalblock">
<div class="content">
<pre><tt>write_1:
st Z+,a
dec b
brne write_1
write_2:
st Z+,c
dec d
brne write_2</tt></pre>
</div></div>
</div>
<h2 id="_warnings_and_errors">Warnings and Errors</h2>
<div class="sectionbody">
<div class="paragraph"><p>Some errors and warnings may confuse you a little bit so we will try to
clear some frequently asked questions about such cases.</p></div>
<h3 id="_constant_out_of_range">Constant out of range</h3><div style="clear:left"></div>
<div class="paragraph"><p>This warning occurs if a value exceeds the byte or word value of a assignment.
Read the comment posted by Jim Galbraith:</p></div>
<div class="paragraph"><p>The expression (~0x80) is a Bitwise Not operation. This
operator returns the input expression with all its bits
inverted. If 0x80 represents -128, then 0x7f, or +127
should be ok. If this is considered as a 32-bit expression
(AVRA internal representation), then it appears to be more
like oxffffffff-0x80 or 0xffffffff<sup>0x80. The result would then
be 0xffffff7f. The assembler would then have to be told or it
would have to decide, based on context, how much
significance to assign to the higher bits. I have also
encountered such conditions with various assemblers,
including AVRA. To make sure the assembler does what I
really want, I use a construct like 0xff-0x80 or 0xff</sup>0x80.
This way the bit significance cannot extend beyond bit-7 and
there cannot be any misunderstanding.</p></div>
<h3 id="_can_8217_t_use_db_directive_in_data_segment">Can&#8217;t use .DB directive in data segment</h3><div style="clear:left"></div>
<div class="paragraph"><div class="title">DB and .DW is only used to assign constant data in eeprom or code space.</div><p>The reason why using it within data segment is forbidden is, that you
cannot set ram content at assembly time. The values must be programmed into
ROM area and at boot read from ROM into RAM. This is up to the user code.
You can only allocate memory for your variables using labels and the .byte
directive.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>.dseg
my_string: .byte 15</tt></pre>
</div></div>
<h3 id="_byte_directive">BYTE directive</h3><div style="clear:left"></div>
<div class="paragraph"><div class="title">BYTE directive can only be used in data segment (.DSEG)</div><p>This directive cannot be used in code or eeprom region because this only
allocates memory without assgning distinct values to it. Please use .db
or .dw instead.</p></div>
<h3 id="_internal_assembler_error">Internal assembler error</h3><div style="clear:left"></div>
<div class="paragraph"><p>If you get an "Internal assembler error" please contact the project maintainer
by sending him a code example and a description of your working enviroment.</p></div>
</div>
<h2 id="_avra_internals">AVRA internals</h2>
<div class="sectionbody">
<div class="paragraph"><p>This section provides thoughts of the avra internal design. I have to admit
that the code of avra is anything else than clean and optimized. To increase
the code readability I will try to give you some standards that should improve
quality. The following standards are similar to what GNU proposes.</p></div>
<h3 id="_coding_standards">Coding standards</h3><div style="clear:left"></div>
<div class="paragraph"><p>Tab space is always 2 spaces. The Tab character (ascii 9) is not used.
if,while,for are always opened on the same line but closed on the next line.
The closing bracket is in the same column as the first letter of the loop
directive.</p></div>
<div class="literalblock">
<div class="content">
<pre><tt>Example:</tt></pre>
</div></div>
<div class="listingblock">
<div class="content">
<pre><tt> while(i &gt; 0) {
do_something();
}</tt></pre>
</div></div>
</div>
<h2 id="_credits">Credits</h2>
<div class="sectionbody">
<div class="paragraph"><p>We would like to thank the following people for giving contributions,
patches and bug reports, as well as suggestions and new ideas.</p></div>
<div class="listingblock">
<div class="content">
<pre><tt> Jon Anders Haugum (project founder)
Burkhard Arenfeld (release 1.2.0)
Tobias Weber (old maintainer)
Jerry Jacobs (release 1.3.0)
Bernt Hembre
Nils Strøm
Roberto Biancardi
Qwerty Jones
Ben Hitchcock (Maker of the mac port)
Daniel Drotos
Laurence Boyd II
Varuzhan Danielyan
Laurence Turner
Eugene R. O'Bryan
Dmitry Dicky
Bob Harris (Maker of coff support)
Tobias Weber (enhanced macro support)
Lesha Bogdanow
Jim Galbraith
Mark Brinicombe
Igor Nikolayenko
Peter Hettkamp
Herb Poppe
David Burke
Alexey Pavluchenko
Alan Probandt
Mariusz Matuszek
Arne Rossius
Marti Tichacek
Patrick Parity
Johannes Overmann
Roland Riegel
Peter Katzmann
Donald D. Davis</tt></pre>
</div></div>
<div class="paragraph"><p>And all the anonymous people who submitted patches!</p></div>
<div class="paragraph"><p>Thank you for your work and support.</p></div>
</div>
<h2 id="_references">References</h2>
<div class="sectionbody">
<div class="literalblock">
<div class="content">
<pre><tt>http://www.suprafluid.com/avra
http://www.avrfreaks.de
http://www.atmel.com</tt></pre>
</div></div>
</div>
</div>
<div id="footnotes"><hr /></div>
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<div id="footer-text">
Version 1.3.0<br />
Last updated 2010-06-28 16:04:26 CEST
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/contrib/toolchain/avra/doc/README.txt
0,0 → 1,679
README
======
 
General and licensing information
---------------------------------
AVRA v1.3.0 - Assember for the Atmel AVR microcontroller family
 
Licensing information
~~~~~~~~~~~~~~~~~~~~~
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version. Please read below for for information.
 
Disclaimer
~~~~~~~~~~
 
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
GNU General Public License
~~~~~~~~~~~~~~~~~~~~~~~~~~
 
You should have received a copy of the GNU General Public License
along with this program; see the file "COPYING". If not, visit
http://www.gnu.org or write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. You can
also contact the authors of AVRA to receive a copy of the COPYING file.
 
Trademarks and copyright
~~~~~~~~~~~~~~~~~~~~~~~~
 
Atmel, AVR, AVR Studio, Intel, Windows are registered enterprises, brands
and registered trademarks. The mentioned companies have no relation to
AVRA and are therefore not responslible for any problems that occur when
using AVRA. Many thanks for your products, support and efforts.
 
 
Introducion
-----------
 
AVRA is an assembler for Atmel AVR microcontrollers, and it is almost
compatible with Atmel's own assembler AVRASM32. The programming
principles and conceptions are based on the ANSI programming language "C".
 
The initial version of AVRA was written by John Anders Haugum. He released
all versions until v0.7. All later versions were released by Tobias Weber.
 
 
Differences between AVRA and AVRASM32
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
There are some differences between the original Atmel assembler AVRASM32 and AVRA. Basically AVRA is designed to replace AVRASM32 without special changes in your current Atmel AVR Studio enviroment.
Command line options have been adapted as far as it was possible until now. Jumping to fault containing line directly by double-clicking on the error message in the output window does work as with AVRASM32.
 
The differences in detail
~~~~~~~~~~~~~~~~~~~~~~~~~
 
- Support for some extra preprocessor directives.
 
.define, .undef, .ifdef, .ifndef, .if, .else, .endif, .elif, .elseif, .warning
 
- Not all command line options are supported.
Specifying an eeprom file (-e) is not supported. All eeprom data is
put out into a file called program.eep.hex and always Intel hex
format. Other hex file formats than Intel are currently not supported.
 
- Forward references not supported for .ifdef and .ifndef directives.
This makes sure, that directives like .ifdef and .undef are working
properly. If you are familiar with the C programming language, you
should get easily into AVRA. See chapter "Programming techniques" for
more information about how to write proper code.
 
- Enhanced macro support
AVRA has some new features for writing flexible macros. This should
increase the ability to reuse code e.g. build your own library.
 
- Debugging support
AVRA creates a coff file everytime the assembly was sucessful. This
file allows AVR Studio or any coff compatible debugger to simulate
or emulate the program.
 
- Meta tags for assembly time
This helps you tracking versions of your software and can also be
used to generate customer specific serial numbers.
 
 
Compatibility
~~~~~~~~~~~~~
 
Since AVRA is written in ANSI C, it should be possible to compile it on
most system platforms. If you have problems compiling AVRA, please leave
a message on the sourceforge message board or send a mail to the
authors of AVRA.
 
 
Installation
------------
 
To install avra you should copy the avra-executable to an apropriate
location. To compile you should rename the appropriate makefile, and
perform a make (use smake for Amiga SAS/C, and nmake for Mickeysoft
visual c++).
 
 
Linux
~~~~~
 
To compile avra you need gcc and the automake utilities. These will create
a ./configure script that evaluates your system enviroment. To get the
AVRA executable, you have to issue the following commands:
 
aclocal
autoconf
automake -a
./configure
make && make install
 
AmigaOS
~~~~~~~
 
avra can be copied any apropriate directory. If you are using the source
distribution a 'make install' will do the same.
 
 
Microsoft Windows
~~~~~~~~~~~~~~~~~
 
If you received the Windows binary package, look into the \bin
directory where you can find avra.exe. This should be copied to any
apropriate location. You can also overwrite AVRASM32.EXE in your
Atmel AVR Studio. If you want to compile it yourself you could download then
OpenWatcom C/C++ Toolchain for windows and create a new project and add the C
and H files to it and compile.
 
Apple OS X
~~~~~~~~~~
 
If you recieved the Apple OS X binary package, look into the bin directory this
file is compiled universal and should run on intel 32 and 64 bit and powerpc. If
you want to compile it yourself go to the src directory and invoke `make -f
makefiles/Makefiles.osx` and then the executable should be created.
 
 
Synopsis
--------
 
Command line usage
~~~~~~~~~~~~~~~~~~
 
usage: AVRA [-f][O|M|I|G] output file type
[-o <filename>] output file name
[-l <filename>] generate list file
[-m <mapfile>] generate map file
[--define <symbol>[=<value>]] [--includedir <dir>] [--listmac]
[--max_errors <number>] [--devices] [--version]
[-h] [--help] general help
[-W NoRegDef] supress register redefinition warnings
<file to assemble>
 
 
Parameter list
~~~~~~~~~~~~~~
 
--listfile -l : Create list file
--mapfile -m : Create map file
--define -D : Define symbol.
--includedir -I : Additional include dirs.
--listmac : List macro expansion in listfile.
--max_errors : Maximum number of errors before exit
(default: 10)
--devices : List out supported devices.
--version : Version information.
--help, -h : This help text.
 
 
Warning supression
~~~~~~~~~~~~~~~~~~
 
Since avra 1.1 there is a possibility to supress certain warnings.
Currently only register reassignment warnings can be supressed.
 
Example: avra -W NoRegDef
 
 
Programming techniques
----------------------
 
 
Using directives
~~~~~~~~~~~~~~~~
 
AVRA offers a number of directives that are not part of Atmel's
assembler. These directives should help you creating versatile code that
can be designed more modular.
 
Directive .define
^^^^^^^^^^^^^^^^^
 
To define a constant, use ".define". This does the same thing as ".equ",
it is just a little more C style. Keep in mind that AVRA is not case
sensitive. Do not mix ".def" and ".define", because ".def" is used to
assign registers only. This is due to backward compatibility to Atmel's
AVRASM32. Here is an example on how .define can be used.
 
.define network 1
 
Now "network" is set to the value 1. You may want to assemble a specific
part of your code depeding on a define or switch setting. You can test
your defined word on existence (.ifdef and .ifndef) as well as on the
value it represents. The following code shows a way to prevent error
messages due to testing undefined constants. Conditional directives must
always end with an .endif directive.
 
.ifndef network
.define network 0
.endif
 
Directive .if and .else
^^^^^^^^^^^^^^^^^^^^^^^
 
The three lines in the last example set the default value of "network".
In the next example, you see how we can use default values. If a constant
has not defined previously, it is set to zero. Now you can test wether
e.g. network support is included into the assemby process.
 
.if network = 1
.include "include\tcpip.asm"
.else
.include "include\dummynet.asm"
.endif
 
In the second part of the above listing you see the use of .else, which
defines the part of the condition that is being executed if the equation
of the preceding .if statement is not equal. You can also use the else
statement to test another equasion. For that purpose use .elif, which
means "else if". Always close this conditional part with ".endif"
 
Directive .error
^^^^^^^^^^^^^^^^
 
This directive can be used to throw errors if a part in the code has reached
that should not be reached. The following example shows how we can stop
the assembly process if a particular value has not been previously set.
 
.ifndef network
.error "network is not configured!" ;the assembler stops here
 
Directive .nolist and .list
^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
The ouput to the list file can be paused by this two directives. After
avra discovers a .nolist while assembling, it stops output to the list file.
After a .list directive is detected, it continues the normal list file output.
 
Directive .includepath
^^^^^^^^^^^^^^^^^^^^^^
 
By default, any file that is included from within the source file must
either be a single filename or a complete absolute path. With the directive
.includepath you can set an additional include path . Furthermore you can
set as many include paths as you want. Be sure not no use same filename
in separate includes, because then it is no longer clear which one avra
should take.
 
Using include files
-------------------
 
To avoid multiple inclusions of include files, you may use some pre-
processor directives. See example file stack.asm that is being included
into the main programm file as well as in other include files.
 
.ifndef _STACK_ASM_
.define _STACK_ASM_
.include "include/config.inc"
 
; *** stack macro ***
.dseg
m_stack: .byte __stack_size__
.cseg
 
.macro stack_setup
load [v:w,m_stack + __stack_size__]
outp [SPREG,v:w]
.endm
 
.endif ; avoid multiple inclusion of stack.asm
 
 
Using build date meta tags
~~~~~~~~~~~~~~~~~~~~~~~~~~
 
If you like to implement compiler build time and date into your
program, you can make use of some sepcial tags that avra supports.
%MINUTE% is being replaced by the current minute (00-59)
%HOUR% is being replaced by the current hour (00-23)
%DAY% is being replaced by the current day of month (01-31)
%MONTH% is being replaced by the current month (01-12)
%YEAR% is being replaced by the current year (2004-9999)
 
buildtime: .db "Release date %DAY%.%MONTH%.%YEAR% %HOUR%:%MINUTE%"
This line will then assembled by avra into:
buildtime: .db "Release date 10.05.2004 19:54"
You may also create a self defined serial number with meta tags:
.define serialnumber %DAY% + %MONTH%*31 + (%YEAR% - 2000) *31*12
 
The %TAG% is translated before any other parsing happens. The real
output can be found in the list file.
 
Macro features
--------------
 
Sometimes you have to work with 16 bit or greater variables stored
in 8 bit registers. The enhanced macro support allows you to write short
and flexible macros that simplify access to big variables. The extended
mode is active, as soon as you use parenthesis like this "[ ]" to wrap
macro parameters.
 
Auto type conversion for macros
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Values representing more than 8 Bits are usualy kept in a set of byte
wide registers. To simplify 16 Bit or greater operations, I added a new
language definitions. Words can be written as r16:r17, whereas register
r16 contains the higher part and register r17 the lower part of this
16 Bit value.
 
Macro data types
^^^^^^^^^^^^^^^^
 
There are 3 data types that can be used. They will be added as character
separated by one underline character.
 
immediate values _i
registers _8,_16,_24,_32,_40,_48,_56,_64
void parameter _v
 
16 Bit Source and Destionation registers 'dst' and 'src'
 
src = YH:YL
dst = ZH:ZL
 
Within the parenthesis, the two words src and dst are interpreted as YH:YL
and ZH:ZL. Normal code outside of the macro parameter parenthesis can
still make use of these special key words "src" and "dst".
 
Examples for automatic type conversion
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
To simplify the parameters in the demonstration below, we need to
redefine some registers.
 
.def a = r16 ; general purpose registers
.def b = r17
.def c = r18
.def d = r19
 
.def w = r20 ; working register
.def v = r21 ; working register
 
If we substract 16 Bit values stored in a, higher byte and b, lower byte
with that in c:d, we usually have to use the following command sequence:
 
sub b,d
sbc a,c
 
Now we can do the following steps to simplify 16 or more Bit manipulations
 
.macro subs
.message "no parameters specified"
.endm
 
.macro subs_16_16
sub @1,@3
sbc @0,@2
.endm
 
.macro subs_16_8
sub @1,@2
sbci @0,0
.endm
 
;now we can write a 16 Bit subraction as:
 
subs [a:b,c:d]
 
;or for calculating 16 minus 8 Bit
 
subs [a:b,c]
 
 
Overloading macros
~~~~~~~~~~~~~~~~~~
 
Like in you are used to C functions, you can write macros for different
parameter lists. If you would like to have a versatile macro, you can
specify a unique macro for each parameter situation. See the next sample.
 
.macro load
 
; this message is shown if you use the macro within your code
; specifying no parameters. If your macro allows the case where
; no parameters are given, exchange .message with your code.
 
.message "no parameters specified"
.endm
 
; Here we define the macro "load" for the case it is being used
; with two registers as first parameter and a immediate (constant)
; value as second parameter.
 
.macro load_16_i
ldi @0,high(@2)
ldi @1,low(@2)
.endm
 
; the same case, but now with a 32 bit register value as first
; parameter
 
.macro load_32_i
ldi @0,BYTE4(@4)
ldi @1,BYTE3(@4)
ldi @2,high(@4)
ldi @3,low(@4)
.endm
 
; Now let's see how these macros are being used in the code
 
load [a:b,15] ;uses macro load_16_i to load immediate
 
load [a:b:c:d,15] ;uses macro load_32_i to load immediate
 
 
More examples
~~~~~~~~~~~~~
 
.dseg
counter .byte 2
.cseg
 
.macro poke
.message "no parameters"
.endm
 
.macro poke_i_16_i
ldi @1,high(@3)
sts @0+0,@1
ldi @2,low(@3)
sts @0+1,@2
.endm
 
.macro poke_i_i
ldi w,@1
sts @0+0,w
.endm
 
.macro poke_i_v_i
ldi w,high(@3)
sts @0+0,w
ldi w,low(@3)
sts @0+1,w
.endm
 
.macro poke_i_v_v_v_i
ldi w,high(@3)
sts @0+0,w
ldi w,low(@3)
sts @0+1,w
ldi w,BYTE3(@3)
sts @0+2,w
ldi w,BYTE4(@3)
sts @0+3,w
.endm
 
 
; this writes '9999' into the memory at 'counter'
; uses only the working register for transfering the values.
 
poke [counter,w:w,9999]
 
; works same as above, but the transferred value '9999' is also
; kept in the pair of register a:b
 
poke [counter,a:b,9999]
 
; in my design 'w' is always working reg. which implies that
; it cannot be used for normal variables. The following example
; uses poke_i_i because the parameter contains two immediate values.
 
poke [counter,9999] ;uses poke_i_i
 
; to be able to choose between a 8,16 or 32 Bit operation, you just
; add a void parameter.
 
poke [counter,,9999] ;uses poke_i_v_i
 
; and the same for 32 Bit pokes
 
poke [counter,,,,9999] ;uses poke_i_v_v_v_i
 
Loops within macros
~~~~~~~~~~~~~~~~~~~
 
One problem you may have experienced, is that labels defined within macros
are defined twice if you call the macro for example two times. Now you can
use labels for macro loops. Loops within macros must end with '_%'. the
"%" symbol is replaced by a running number.
 
Loop example
^^^^^^^^^^^^
 
; Definition of the macro
 
.macro write_8_8
write_%:
st Z+,@0
dec @1
brne write_%
.endm
 
; Use in user code
 
write [a,b]
write [c,d]
 
; After assembling this code, the result looks like this
 
write_1:
st Z+,a
dec b
brne write_1
write_2:
st Z+,c
dec d
brne write_2
 
Warnings and Errors
-------------------
 
Some errors and warnings may confuse you a little bit so we will try to
clear some frequently asked questions about such cases.
 
Constant out of range
~~~~~~~~~~~~~~~~~~~~~
 
This warning occurs if a value exceeds the byte or word value of a assignment.
Read the comment posted by Jim Galbraith:
 
The expression (~0x80) is a Bitwise Not operation. This
operator returns the input expression with all its bits
inverted. If 0x80 represents -128, then 0x7f, or +127
should be ok. If this is considered as a 32-bit expression
(AVRA internal representation), then it appears to be more
like oxffffffff-0x80 or 0xffffffff^0x80. The result would then
be 0xffffff7f. The assembler would then have to be told or it
would have to decide, based on context, how much
significance to assign to the higher bits. I have also
encountered such conditions with various assemblers,
including AVRA. To make sure the assembler does what I
really want, I use a construct like 0xff-0x80 or 0xff^0x80.
This way the bit significance cannot extend beyond bit-7 and
there cannot be any misunderstanding.
 
Can't use .DB directive in data segment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
.DB and .DW is only used to assign constant data in eeprom or code space.
The reason why using it within data segment is forbidden is, that you
cannot set ram content at assembly time. The values must be programmed into
ROM area and at boot read from ROM into RAM. This is up to the user code.
You can only allocate memory for your variables using labels and the .byte
directive.
 
.dseg
my_string: .byte 15
 
BYTE directive
~~~~~~~~~~~~~~
 
.BYTE directive can only be used in data segment (.DSEG)
 
This directive cannot be used in code or eeprom region because this only
allocates memory without assgning distinct values to it. Please use .db
or .dw instead.
 
Internal assembler error
~~~~~~~~~~~~~~~~~~~~~~~~
 
If you get an "Internal assembler error" please contact the project maintainer
by sending him a code example and a description of your working enviroment.
 
 
AVRA internals
--------------
 
This section provides thoughts of the avra internal design. I have to admit
that the code of avra is anything else than clean and optimized. To increase
the code readability I will try to give you some standards that should improve
quality. The following standards are similar to what GNU proposes.
 
Coding standards
~~~~~~~~~~~~~~~~
 
Tab space is always 2 spaces. The Tab character (ascii 9) is not used.
if,while,for are always opened on the same line but closed on the next line.
The closing bracket is in the same column as the first letter of the loop
directive.
 
Example:
----
while(i > 0) {
do_something();
}
----
 
 
Credits
-------
 
We would like to thank the following people for giving contributions,
patches and bug reports, as well as suggestions and new ideas.
 
----
Jon Anders Haugum (project founder)
Burkhard Arenfeld (release 1.2.0)
Tobias Weber (old maintainer)
Jerry Jacobs (release 1.3.0)
Bernt Hembre
Nils Strøm
Roberto Biancardi
Qwerty Jones
Ben Hitchcock (Maker of the mac port)
Daniel Drotos
Laurence Boyd II
Varuzhan Danielyan
Laurence Turner
Eugene R. O'Bryan
Dmitry Dicky
Bob Harris (Maker of coff support)
Tobias Weber (enhanced macro support)
Lesha Bogdanow
Jim Galbraith
Mark Brinicombe
Igor Nikolayenko
Peter Hettkamp
Herb Poppe
David Burke
Alexey Pavluchenko
Alan Probandt
Mariusz Matuszek
Arne Rossius
Marti Tichacek
Patrick Parity
Johannes Overmann
Roland Riegel
Peter Katzmann
Donald D. Davis
----
 
And all the anonymous people who submitted patches!
 
Thank you for your work and support.
 
References
----------
 
http://www.suprafluid.com/avra
http://www.avrfreaks.de
http://www.atmel.com
/contrib/toolchain/avra/doc/asciidoc-xhtml11.js
0,0 → 1,128
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for (var i = el.firstChild; i != null; i = i.nextSibling) {
if (i.nodeType == 1 /* Node.ELEMENT_NODE */) {
var mo = re.exec(i.tagName);
if (mo && (i.getAttribute("class") || i.getAttribute("className")) != "float") {
result[result.length] = new TocEntry(i, getText(i), mo[1]-1);
}
iterate(i);
}
}
}
iterate(el);
return result;
}
 
var toc = document.getElementById("toc");
var entries = tocEntries(document.getElementById("content"), toclevels);
for (var i = 0; i < entries.length; ++i) {
var entry = entries[i];
if (entry.element.id == "")
entry.element.id = "_toc_" + i;
var a = document.createElement("a");
a.href = "#" + entry.element.id;
a.appendChild(document.createTextNode(entry.text));
var div = document.createElement("div");
div.appendChild(a);
div.className = "toclevel" + entry.toclevel;
toc.appendChild(div);
}
if (entries.length == 0)
toc.parentNode.removeChild(toc);
},
 
 
/////////////////////////////////////////////////////////////////////
// Footnotes generator
/////////////////////////////////////////////////////////////////////
 
/* Based on footnote generation code from:
* http://www.brandspankingnew.net/archive/2005/07/format_footnote.html
*/
 
footnotes: function () {
var cont = document.getElementById("content");
var noteholder = document.getElementById("footnotes");
var spans = cont.getElementsByTagName("span");
var refs = {};
var n = 0;
for (i=0; i<spans.length; i++) {
if (spans[i].className == "footnote") {
n++;
// Use [\s\S] in place of . so multi-line matches work.
// Because JavaScript has no s (dotall) regex flag.
note = spans[i].innerHTML.match(/\s*\[([\s\S]*)]\s*/)[1];
noteholder.innerHTML +=
"<div class='footnote' id='_footnote_" + n + "'>" +
"<a href='#_footnoteref_" + n + "' title='Return to text'>" +
n + "</a>. " + note + "</div>";
spans[i].innerHTML =
"[<a id='_footnoteref_" + n + "' href='#_footnote_" + n +
"' title='View footnote' class='footnote'>" + n + "</a>]";
var id =spans[i].getAttribute("id");
if (id != null) refs["#"+id] = n;
}
}
if (n == 0)
noteholder.parentNode.removeChild(noteholder);
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// Process footnoterefs.
for (i=0; i<spans.length; i++) {
if (spans[i].className == "footnoteref") {
var href = spans[i].getElementsByTagName("a")[0].getAttribute("href");
href = href.match(/#.*/)[0]; // Because IE return full URL.
n = refs[href];
spans[i].innerHTML =
"[<a href='#_footnote_" + n +
"' title='View footnote' class='footnote'>" + n + "</a>]";
}
}
}
}
 
}
/contrib/toolchain/avra/doc/build-website.sh
0,0 → 1,11
#!/bin/sh
 
VERS="1.3.0"
DATE="2010-06-28"
 
ASCIIDOC_HTML="asciidoc --unsafe --backend=xhtml11 --conf-file=layout1.conf --attribute icons --attribute iconsdir=./images/icons --attribute=badges --attribute=revision=$VERS --attribute=date=$DATE"
 
$ASCIIDOC_HTML -a index-only index.txt
$ASCIIDOC_HTML ChangeLog.txt
$ASCIIDOC_HTML downloads.txt
$ASCIIDOC_HTML README.txt
Property changes:
Added: svn:executable
+*
\ No newline at end of property
/contrib/toolchain/avra/doc/downloads.html
0,0 → 1,75
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN"
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
<meta name="generator" content="AsciiDoc 8.5.3" />
<link rel="stylesheet" href="./xhtml11.css" type="text/css" />
<link rel="stylesheet" href="./xhtml11-quirks.css" type="text/css" />
<link rel="stylesheet" href="./layout1.css" type="text/css" />
<script type="text/javascript">
/*<![CDATA[*/
window.onload = function(){asciidoc.footnotes();}
/*]]>*/
</script>
<script type="text/javascript" src="./asciidoc-xhtml11.js"></script>
<title>Downloads</title>
</head>
<body>
<div id="layout-banner">
<div id="layout-title">AVRA</div>
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div>
</div>
<table>
<tr valign="top">
<td id="layout-menu">
<div>&#187;<a href="index.html">Home</a></div>
<div>&#187;<a href="README.html">Readme</a></div>
<div>&#187;<a href="downloads.html">Downloads</a></div>
<div>&#187;<a href="ChangeLog.html">ChangeLog</a></div>
<div>&#187;<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div>
<div id="page-source">&#187;<a href="downloads.txt">Page&nbsp;Source</a></div>
</td>
<td>
<div id="layout-content">
<div id="header">
<h1>Downloads</h1>
</div>
<div id="content">
<div id="preamble">
<div class="sectionbody">
<div class="paragraph"><p>The latest release can always be downloaded from sourceforge.</p></div>
<div class="paragraph"><p><a href="http://sourceforge.net/projects/avra/files">http://sourceforge.net/projects/avra/files</a></p></div>
</div>
</div>
</div>
<div id="footnotes"><hr /></div>
<div id="footer">
<div id="footer-text">
Version 1.3.0<br />
Last updated 2010-06-28 16:04:25 CEST
</div>
<div id="footer-badges">
<a href="http://validator.w3.org/check?uri=referer">
<img style="border:0;width:88px;height:31px"
src="http://www.w3.org/Icons/valid-xhtml11-blue"
alt="Valid XHTML 1.1" height="31" width="88" />
</a>
<a href="http://jigsaw.w3.org/css-validator/">
<img style="border:0;width:88px;height:31px"
src="http://jigsaw.w3.org/css-validator/images/vcss-blue"
alt="Valid CSS!" />
</a>
<a href="http://www.mozilla.org/products/firefox/">
<img style="border:none; width:110px; height:32px;"
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif"
alt="Get Firefox!" />
</a>
</div>
</div>
</div>
</td>
</tr>
</table>
</body>
</html>
/contrib/toolchain/avra/doc/downloads.txt
0,0 → 1,6
Downloads
=========
 
The latest release can always be downloaded from sourceforge.
 
http://sourceforge.net/projects/avra/files
/contrib/toolchain/avra/doc/images/highlighter.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/README
0,0 → 1,5
Replaced the plain DocBook XSL admonition icons with Jimmac's DocBook
icons (http://jimmac.musichall.cz/ikony.php3). I dropped transparency
from the Jimmac icons to get round MS IE and FOP PNG incompatibilies.
 
Stuart Rackham
/contrib/toolchain/avra/doc/images/icons/callouts/1.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/10.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/11.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/12.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/13.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/14.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/15.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/2.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/3.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/4.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/5.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/6.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/7.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/8.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/callouts/9.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/caution.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/example.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/home.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/important.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/next.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/note.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/prev.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/tip.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/up.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/icons/warning.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/smallnew.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/images/tiger.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/contrib/toolchain/avra/doc/index.html
0,0 → 1,94
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN"
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
<meta name="generator" content="AsciiDoc 8.5.3" />
<meta name="description" content="Text based document generation" />
<meta name="keywords" content="text to HTML, text to DocBook, text to XML, AsciiDoc" />
<link rel="stylesheet" href="./xhtml11.css" type="text/css" />
<link rel="stylesheet" href="./xhtml11-quirks.css" type="text/css" />
<link rel="stylesheet" href="./layout1.css" type="text/css" />
<script type="text/javascript">
/*<![CDATA[*/
window.onload = function(){asciidoc.footnotes();}
/*]]>*/
</script>
<script type="text/javascript" src="./asciidoc-xhtml11.js"></script>
<title>AVRA Home Page</title>
</head>
<body>
<div id="layout-banner">
<div id="layout-title">AVRA</div>
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div>
</div>
<table>
<tr valign="top">
<td id="layout-menu">
<div>&#187;<a href="index.html">Home</a></div>
<div>&#187;<a href="README.html">Readme</a></div>
<div>&#187;<a href="downloads.html">Downloads</a></div>
<div>&#187;<a href="ChangeLog.html">ChangeLog</a></div>
<div>&#187;<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div>
<div id="page-source">&#187;<a href="index.txt">Page&nbsp;Source</a></div>
</td>
<td>
<div id="layout-content">
<div id="header">
<h1>AVRA Home Page</h1>
</div>
<div id="content">
<div id="preamble">
<div class="sectionbody">
<div class="sidebarblock">
<div class="sidebar-content">
<div class="sidebar-title">2010-06-28: AVRA 1.3.0 Released</div>
<div class="paragraph"><p>This release contains a few improvements, a couple of bug fixes and
documentation updates.</p></div>
<div class="paragraph"><p>Read the <a href="ChangeLog.html">ChangeLog</a> for a full list of all
additions, changes and bug fixes. Changes are documented in the
updated <a href="README.html">Readme</a>. See the
<a href="downloads.html">Downloads</a> page for sourcecode and binary releases.</p></div>
</div></div>
</div>
</div>
<h2 id="_introduction">Introduction</h2>
<div class="sectionbody">
<div class="paragraph"><p>AVRA is an assembler for Atmel AVR microcontrollers, and it is almost
compatible with Atmel&#8217;s own assembler AVRASM32. The programming
principles and conceptions are based on the ANSI programming language "C".</p></div>
<div class="paragraph"><p>The initial version of AVRA was written by John Anders Haugum in 1999. He
released all versions until v0.7. All later versions were released by Tobias
Weber. And version 1.3.0 is released by Jerry Jacobs.</p></div>
</div>
</div>
<div id="footnotes"><hr /></div>
<div id="footer">
<div id="footer-text">
Version 1.3.0<br />
Last updated 2010-06-28 16:04:24 CEST
</div>
<div id="footer-badges">
<a href="http://validator.w3.org/check?uri=referer">
<img style="border:0;width:88px;height:31px"
src="http://www.w3.org/Icons/valid-xhtml11-blue"
alt="Valid XHTML 1.1" height="31" width="88" />
</a>
<a href="http://jigsaw.w3.org/css-validator/">
<img style="border:0;width:88px;height:31px"
src="http://jigsaw.w3.org/css-validator/images/vcss-blue"
alt="Valid CSS!" />
</a>
<a href="http://www.mozilla.org/products/firefox/">
<img style="border:none; width:110px; height:32px;"
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif"
alt="Get Firefox!" />
</a>
</div>
</div>
</div>
</td>
</tr>
</table>
</body>
</html>
/contrib/toolchain/avra/doc/index.txt
0,0 → 1,23
AVRA Home Page
==============
 
.{revdate}: AVRA {revnumber} Released
************************************************************************
This release contains a few improvements, a couple of bug fixes and
documentation updates.
 
Read the link:ChangeLog.html[ChangeLog] for a full list of all
additions, changes and bug fixes. Changes are documented in the
updated link:README.html[Readme]. See the
link:downloads.html[Downloads] page for sourcecode and binary releases.
************************************************************************
 
Introduction
------------
AVRA is an assembler for Atmel AVR microcontrollers, and it is almost
compatible with Atmel's own assembler AVRASM32. The programming
principles and conceptions are based on the ANSI programming language "C".
 
The initial version of AVRA was written by John Anders Haugum in 1999. He
released all versions until v0.7. All later versions were released by Tobias
Weber. And version 1.3.0 is released by Jerry Jacobs.
/contrib/toolchain/avra/doc/layout1.conf
0,0 → 1,155
#
# AsciiDoc website.
# Three division table based layout (layout1).
#
# +-----------------------------------------------------+
# | #layout-banner |
# +--------------+--------------------------------------+
# | | |
# | | |
# | #layout-menu | #layout-content |
# | | |
# | | |
# | | |
# +--------------+--------------------------------------+
#
# - The #layout-menu and #layout-content divisions are contained in a
# two cell table.
# I would be nice to use pure CSS for the layout but the table is better for
# this layout because:
#
# * The column widths automatically size to fit column width (specifically
# the #layout-menu)
# * The column heights automatically size to the tallest.
#
# - The #layout-content division is a container for AsciiDoc page documents.
# - Documents rendered in the #layout-content use the standard AsciiDoc
# xhtml11 backend stylesheets.
 
[specialwords]
monospacedwords=(?u)\\?\basciidoc\(1\) (?u)\\?\ba2x\(1\)
 
[header]
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN"
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en">
<head>
<meta http-equiv="Content-Type" content="text/html; charset={encoding}" />
<meta name="generator" content="AsciiDoc {asciidoc-version}" />
ifdef::index-only[]
<meta name="description" content="Text based document generation" />
<meta name="keywords" content="text to HTML, text to DocBook, text to XML, AsciiDoc" />
endif::index-only[]
<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}.css" type="text/css" />
{doctype-manpage}<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}-manpage.css" type="text/css" />
<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}-quirks.css" type="text/css" />
<link rel="stylesheet" href="{stylesdir=.}/layout1.css" type="text/css" />
<script type="text/javascript">
/*<![CDATA[*/
window.onload = function()\{asciidoc.footnotes();{toc? asciidoc.toc({toclevels});}\}
/*]]>*/
</script>
<script type="text/javascript" src="{scriptsdir=.}/asciidoc-xhtml11.js"></script>
ifdef::asciimath[]
<script type="text/javascript" src="{scriptsdir=.}/ASCIIMathML.js"></script>
endif::asciimath[]
ifdef::latexmath[]
<script type="text/javascript" src="{scriptsdir=.}/LaTeXMathML.js"></script>
endif::latexmath[]
<title>{doctitle}</title>
</head>
<body{max-width? style="max-width:{max-width}"}>
<div id="layout-banner">
<div id="layout-title">AVRA</div>
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div>
</div>
<table>
<tr valign="top">
<td id="layout-menu">
<div>&#187;<a href="index.html">Home</a></div>
<div>&#187;<a href="README.html">Readme</a></div>
<div>&#187;<a href="downloads.html">Downloads</a></div>
<div>&#187;<a href="ChangeLog.html">ChangeLog</a></div>
<div>&#187;<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div>
<div id="page-source">&#187;<a href="{eval:os.path.basename('{infile}')}">Page&nbsp;Source</a></div>
</td>
<td>
<div id="layout-content">
# Article, book header.
ifndef::doctype-manpage[]
<div id="header">
<h1>{doctitle}</h1>
<span id="author">{author}</span><br />
<span id="email"><tt>&lt;<a href="mailto:{email}">{email}</a>&gt;</tt></span><br />
{authored}<span id="revision">version {revnumber}{revdate?,}</span>
{authored}{revdate}
ifdef::toc[]
<div id="toc">
<div id="toctitle">Table of Contents</div>
<noscript><p><b>JavaScript must be enabled in your browser to display the table of contents.</b></p></noscript>
</div>
endif::toc[]
</div>
endif::doctype-manpage[]
# Man page header.
ifdef::doctype-manpage[]
<div id="header">
<h1>
{doctitle} Manual Page
</h1>
ifdef::toc[]
<div id="toc">
<div id="toctitle">Table of Contents</div>
<noscript><p><b>JavaScript must be enabled in your browser to display the table of contents.</b></p></noscript>
</div>
endif::toc[]
<h2>NAME</h2>
<div class="sectionbody">
<p>{manname} -
{manpurpose}
</p>
</div>
</div>
endif::doctype-manpage[]
<div id="content">
 
[footer]
</div>
{disable-javascript%<div id="footnotes"><hr /></div>}
<div id="footer">
<div id="footer-text">
Version {revnumber}<br />
Last updated {localdate} {localtime}
</div>
ifdef::badges[]
<div id="footer-badges">
ifdef::textonly[]
Valid <a href="http://validator.w3.org/check?uri=referer">XHTML</a>
and <a href="http://jigsaw.w3.org/css-validator/check/referer">CSS</a>.
endif::textonly[]
ifndef::textonly[]
<a href="http://validator.w3.org/check?uri=referer">
<img style="border:0;width:88px;height:31px"
src="http://www.w3.org/Icons/valid-xhtml11-blue"
alt="Valid XHTML 1.1" height="31" width="88" />
</a>
<a href="http://jigsaw.w3.org/css-validator/">
<img style="border:0;width:88px;height:31px"
src="http://jigsaw.w3.org/css-validator/images/vcss-blue"
alt="Valid CSS!" />
</a>
<a href="http://www.mozilla.org/products/firefox/">
<img style="border:none; width:110px; height:32px;"
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif"
alt="Get Firefox!" />
</a>
endif::textonly[]
</div>
endif::badges[]
</div>
</div>
</td>
</tr>
</table>
</body>
</html>
/contrib/toolchain/avra/doc/layout1.css
0,0 → 1,65
body {
background-color: white;
margin: 1%;
}
 
h1 {
margin-top: 0.5em;
}
 
#layout-banner {
background-color: #73a0c5;
color: white;
font-family: sans-serif;
text-align: left;
padding: 0.8em 20px;
}
 
#layout-title {
font-family: monospace;
font-size: 3.5em;
font-weight: bold;
letter-spacing: 0.2em;
margin: 0;
}
 
#layout-description {
font-size: 1.2em;
letter-spacing: 0.1em;
}
 
#layout-menu {
background-color: #f4f4f4;
border-right: 3px solid #eeeeee;
padding-top: 0.8em;
padding-left: 20px;
padding-right: 0.8em;
font-size: 1.1em;
font-family: sans-serif;
font-weight: bold;
}
#layout-menu a {
line-height: 2em;
margin-left: 0.5em;
}
#layout-menu a:link, #layout-menu a:visited, #layout-menu a:hover {
color: #527bbd;
text-decoration: none;
}
#layout-menu a:hover {
color: navy;
text-decoration: none;
}
#layout-menu #page-source {
border-top: 2px solid silver;
margin-top: 0.2em;
}
 
#layout-content {
margin-left: 1.0em;
}
 
@media print {
#layout-banner { display: none; }
#layout-menu { display: none; }
}
/contrib/toolchain/avra/doc/xhtml11-manpage.css
0,0 → 1,18
/* Overrides for manpage documents */
h1 {
padding-top: 0.5em;
padding-bottom: 0.5em;
border-top: 2px solid silver;
border-bottom: 2px solid silver;
}
h2 {
border-style: none;
}
div.sectionbody {
margin-left: 5%;
}
 
@media print {
div#toc { display: none; }
}
 
/contrib/toolchain/avra/doc/xhtml11-quirks.css
0,0 → 1,41
/* Workarounds for IE6's broken and incomplete CSS2. */
 
div.sidebar-content {
background: #ffffee;
border: 1px solid silver;
padding: 0.5em;
}
div.sidebar-title, div.image-title {
color: #527bbd;
font-family: sans-serif;
font-weight: bold;
margin-top: 0.0em;
margin-bottom: 0.5em;
}
 
div.listingblock div.content {
border: 1px solid silver;
background: #f4f4f4;
padding: 0.5em;
}
 
div.quoteblock-attribution {
padding-top: 0.5em;
text-align: right;
}
 
pre.verseblock-content {
font-family: inherit;
}
div.verseblock-attribution {
padding-top: 0.75em;
text-align: left;
}
 
div.exampleblock-content {
border-left: 3px solid #dddddd;
padding-left: 0.5em;
}
 
/* IE6 sets dynamically generated links as visited. */
div#toc a:visited { color: blue; }
/contrib/toolchain/avra/doc/xhtml11.css
0,0 → 1,367
/* Debug borders */
p, li, dt, dd, div, pre, h1, h2, h3, h4, h5, h6 {
/*
border: 1px solid red;
*/
}
 
body {
margin: 1em 5% 1em 5%;
}
 
a {
color: blue;
text-decoration: underline;
}
a:visited {
color: fuchsia;
}
 
em {
font-style: italic;
color: navy;
}
 
strong {
font-weight: bold;
color: #083194;
}
 
tt {
color: navy;
}
 
h1, h2, h3, h4, h5, h6 {
color: #527bbd;
font-family: sans-serif;
margin-top: 1.2em;
margin-bottom: 0.5em;
line-height: 1.3;
}
 
h1, h2, h3 {
border-bottom: 2px solid silver;
}
h2 {
padding-top: 0.5em;
}
h3 {
float: left;
}
h3 + * {
clear: left;
}
 
div.sectionbody {
font-family: serif;
margin-left: 0;
}
 
hr {
border: 1px solid silver;
}
 
p {
margin-top: 0.5em;
margin-bottom: 0.5em;
}
 
ul, ol, li > p {
margin-top: 0;
}
 
pre {
padding: 0;
margin: 0;
}
 
span#author {
color: #527bbd;
font-family: sans-serif;
font-weight: bold;
font-size: 1.1em;
}
span#email {
}
span#revnumber, span#revdate, span#revremark {
font-family: sans-serif;
}
 
div#footer {
font-family: sans-serif;
font-size: small;
border-top: 2px solid silver;
padding-top: 0.5em;
margin-top: 4.0em;
}
div#footer-text {
float: left;
padding-bottom: 0.5em;
}
div#footer-badges {
float: right;
padding-bottom: 0.5em;
}
 
div#preamble {
margin-top: 1.5em;
margin-bottom: 1.5em;
}
div.tableblock, div.imageblock, div.exampleblock, div.verseblock,
div.quoteblock, div.literalblock, div.listingblock, div.sidebarblock,
div.admonitionblock {
margin-top: 1.0em;
margin-bottom: 1.5em;
}
div.admonitionblock {
margin-top: 2.0em;
margin-bottom: 2.0em;
margin-right: 10%;
color: #606060;
}
 
div.content { /* Block element content. */
padding: 0;
}
 
/* Block element titles. */
div.title, caption.title {
color: #527bbd;
font-family: sans-serif;
font-weight: bold;
text-align: left;
margin-top: 1.0em;
margin-bottom: 0.5em;
}
div.title + * {
margin-top: 0;
}
 
td div.title:first-child {
margin-top: 0.0em;
}
div.content div.title:first-child {
margin-top: 0.0em;
}
div.content + div.title {
margin-top: 0.0em;
}
 
div.sidebarblock > div.content {
background: #ffffee;
border: 1px solid silver;
padding: 0.5em;
}
 
div.listingblock > div.content {
border: 1px solid silver;
background: #f4f4f4;
padding: 0.5em;
}
 
div.quoteblock, div.verseblock {
padding-left: 1.0em;
margin-left: 1.0em;
margin-right: 10%;
border-left: 5px solid #dddddd;
color: #777777;
}
 
div.quoteblock > div.attribution {
padding-top: 0.5em;
text-align: right;
}
 
div.verseblock > pre.content {
font-family: inherit;
}
div.verseblock > div.attribution {
padding-top: 0.75em;
text-align: left;
}
/* DEPRECATED: Pre version 8.2.7 verse style literal block. */
div.verseblock + div.attribution {
text-align: left;
}
 
div.admonitionblock .icon {
vertical-align: top;
font-size: 1.1em;
font-weight: bold;
text-decoration: underline;
color: #527bbd;
padding-right: 0.5em;
}
div.admonitionblock td.content {
padding-left: 0.5em;
border-left: 3px solid #dddddd;
}
 
div.exampleblock > div.content {
border-left: 3px solid #dddddd;
padding-left: 0.5em;
}
 
div.imageblock div.content { padding-left: 0; }
span.image img { border-style: none; }
a.image:visited { color: white; }
 
dl {
margin-top: 0.8em;
margin-bottom: 0.8em;
}
dt {
margin-top: 0.5em;
margin-bottom: 0;
font-style: normal;
color: navy;
}
dd > *:first-child {
margin-top: 0.1em;
}
 
ul, ol {
list-style-position: outside;
}
ol.arabic {
list-style-type: decimal;
}
ol.loweralpha {
list-style-type: lower-alpha;
}
ol.upperalpha {
list-style-type: upper-alpha;
}
ol.lowerroman {
list-style-type: lower-roman;
}
ol.upperroman {
list-style-type: upper-roman;
}
 
div.compact ul, div.compact ol,
div.compact p, div.compact p,
div.compact div, div.compact div {
margin-top: 0.1em;
margin-bottom: 0.1em;
}
 
div.tableblock > table {
border: 3px solid #527bbd;
}
thead, p.table.header {
font-family: sans-serif;
font-weight: bold;
}
tfoot {
font-weight: bold;
}
td > div.verse {
white-space: pre;
}
p.table {
margin-top: 0;
}
/* Because the table frame attribute is overriden by CSS in most browsers. */
div.tableblock > table[frame="void"] {
border-style: none;
}
div.tableblock > table[frame="hsides"] {
border-left-style: none;
border-right-style: none;
}
div.tableblock > table[frame="vsides"] {
border-top-style: none;
border-bottom-style: none;
}
 
 
div.hdlist {
margin-top: 0.8em;
margin-bottom: 0.8em;
}
div.hdlist tr {
padding-bottom: 15px;
}
dt.hdlist1.strong, td.hdlist1.strong {
font-weight: bold;
}
td.hdlist1 {
vertical-align: top;
font-style: normal;
padding-right: 0.8em;
color: navy;
}
td.hdlist2 {
vertical-align: top;
}
div.hdlist.compact tr {
margin: 0;
padding-bottom: 0;
}
 
.comment {
background: yellow;
}
 
.footnote, .footnoteref {
font-size: 0.8em;
}
 
span.footnote, span.footnoteref {
vertical-align: super;
}
 
#footnotes {
margin: 20px 0 20px 0;
padding: 7px 0 0 0;
}
 
#footnotes div.footnote {
margin: 0 0 5px 0;
}
 
#footnotes hr {
border: none;
border-top: 1px solid silver;
height: 1px;
text-align: left;
margin-left: 0;
width: 20%;
min-width: 100px;
}
 
 
@media print {
div#footer-badges { display: none; }
}
 
div#toc {
margin-bottom: 2.5em;
}
 
div#toctitle {
color: #527bbd;
font-family: sans-serif;
font-size: 1.1em;
font-weight: bold;
margin-top: 1.0em;
margin-bottom: 0.1em;
}
 
div.toclevel1, div.toclevel2, div.toclevel3, div.toclevel4 {
margin-top: 0;
margin-bottom: 0;
}
div.toclevel2 {
margin-left: 2em;
font-size: 0.9em;
}
div.toclevel3 {
margin-left: 4em;
font-size: 0.9em;
}
div.toclevel4 {
margin-left: 6em;
font-size: 0.9em;
}
/contrib/toolchain/avra/examples/testcode_avra-1_2_3.asm
0,0 → 1,19
.device ATmega8
+ .db 1,2
+ .message "The previous line is ignored with avra-1.2.2 because .org 0 is terminated with CR only. "
+ .message "This is line 5 but avra-1.2.2 shows line 4"
+ .db "X%MINUTE%YEAR%" ; Take a look at this percent chars too : % % % %
+ .db "%YEAR%HELLO%" ; Strange replacement, if one percent char is missing
+ .db "%HOUR%:%MINUTE%%"
+ .db "øC" ; Look at the special char. (Error in listing only. HEX-file was ok)
+ ; Additional warning : Don't use linux editors with UTF charset ! A single special char
+ ; (Code > 127 in codepage 850 e.g. german umlauts) could be an unvisible TWO bytes sequence
+ ; in UTF coding. To be on the save side never use chars with code > 127.
+ ; It's better to replace them by the code e.g. .db "M",129,"nchen" (german town 'Munich')
+ ldi R16, ';' ; This is wrong with avra-1.2.2.
+ ldi R16, 0x3b ; Should generate same code like above
+
+; TODO :
+; ldi R16,high (11111) ; "high(" is OK, "high (" isn't. Same with other functions...
+
/contrib/toolchain/avra/examples/testcode_avra-1_3_0.asm
0,0 → 1,27
; Test new device
.device ATmega328P
 
; Test number sign labels
#define TEST
.define DOTTEST
 
 
; Test whitespace between function name and value
ldi r16, high(0)
ldi r17, high (0)
 
;---
; Test data segment start with a number sign instead of a dot
;---
#DSEG
Buffer: .BYTE 8 ; Reserve 64 bits
 
;---
; EEPROM segment
;---
.ESEG
 
; Test line continuation
AVERAGE: .db 0xF0, 0xFF, \
0x55, 0xFF, \
0x55, 0x0F
/contrib/toolchain/avra/examples/throttle.asm
0,0 → 1,916
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * "throttle.asm" *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
; ***************************************************************************************
; * Fixed Version for avra >= 1.2.2 because .DSEG cannot be used, if device has no SRAM *
; * B.Arenfeld, 10.05.2007 *
; ***************************************************************************************
; ***************************************************************************************
; *For Attiny 15 *
; * *
; *For compilation with: Avra 0.70 or later *
; * *
; * Atmel avrasm32.exe will not work becaue of the *
; * use of preprocessor directives #ifdef, #ifndef *
; * , and #endif, which Atmel doesn't support! *
; * *
; *Compiling requires the following files: *
; * "tn15def.inc" Labels and identifiers for tiny15 *
; * "throttle_dev_set.inc" Tiny 15 device settings *
; * "throttle_op_set.inc" Operation settings (THIS IS THE ONE TO EDIT THE *
; * COMPLIE-TIME OPTIONS ON THE WAY THE THROTTLE *
; * PERFORMS *
; * *
; *Depending on the compile time options, the following files are also required: *
; * "throttle_divide.asm" Two division routines. (one from atmel) *
; * "throttle_set_lowpass.asm" Lowpass filter on throttle handle *
; * "throttle_momentum.asm" Compute speed according to momentum *
; * "throttle_momentum_lowpass.asm" Lowpass filter on momentum handle *
; * "throttle_backemf.asm" Adjust pwm based on motor speed *
; * "throttle_pulse.asm" Provide pulse assist at low motor speeds *
; * "throttle_multiply.asm" atmel multiplication routine *
; * *
; *Subroutine Categories and Stack *
; * *
; * The Tiny 15 has a three level stack which handles return addresses for *
; * subroutine calls and for interrupt service routines. The categories below *
; * ensure that the stack does not overflow. The four (4) categories are: *
; * *
; * -- Top Level Routines: These routines are never called, and never *
; * return ("ret") and so the stack is, "empty" *
; * These routines may call any subroutine. *
; * Register Variables: Temp, Temp1, ... *
; * *
; * -- First Level Subroutines: Stack has 1 entry. These routines may call *
; * Second Level Subroutines only. *
; * Register Variables: A_Temp, A_Temp1, ... *
; * *
; * -- Second Level Subroutines: Stack has 2 entries. These routines may NOT *
; * call any subroutines. *
; * Register Variables: B_Temp, B_Temp1, ... *
; * *
; * -- Interrupt Service These occur assynchronously, and therefor may *
; * occur during Second Level Subroutines. If so, *
; * the stack has 3 entries and IS FULL. These routines *
; * may NOT call any subroutines. *
; * Register Variables: I_Temp, I_Temp1, ... *
; * *
; * Register variables are reserved for each level of routine. Each level may freely *
; * use the register variables for it's own level. Some sharing of variables may *
; * occur subject to these guidelines: *
; * -- No category execpt Interrupt Service may use Interrupt Service variables. This *
; * is because ISRs occur asynchronously. *
; * -- A category may NOT use variables reserved for higher level categories. *
; * -- A category may use lower level routine variables as long as their use does not *
; * span any subroutine calls. *
; * *
; *Other settings *
; * There is no way to put these settings into this file, but these must also be *
; * done: *
; * *
; * BODLEVEL: 0 4.0V *
; * BOODEN: 0 ENABLED (brown out detection) *
; * SPIEN: 0 ENABLED (in circuit programming) *
; * RSTDISBL 0 DISABLED (reset on PB5) *
; * CKSEL 11 (very quickly rising power) *
; * LB1 1 (LB1 & LB2: No lock) *
; * LB2 1 *
; * *
; * Calibration byte into flash byte address as specified in *
; * osccal_location. *
; * *
; * Notes regarding these settings: *
; * --Brown out detection. The datasheet warns against using the EEPROM without *
; * brownout detection because of the possibility of errant execution at very low *
; * voltage levels. *
; * *
; **************************************************************************************
 
 
 
;*****************************************************************************************
;*****************************************************************************************
;* Included files *
;*****************************************************************************************
;*****************************************************************************************
.INCLUDE "tn15def.inc" ; Labels and identifiers for tiny15
.INCLUDE "throttle_op_set.inc" ; Operation settings
.INCLUDE "throttle_dev_set.inc" ; Tiny 15 device settings
 
;*****************************************************************************************
;*****************************************************************************************
;* DATA TABLE *
;*****************************************************************************************
;*****************************************************************************************
;.CSEG
;.ORG 0x01E0 ; Program .ORG 0x01E0 actually means byte
; location 0x03C0.
 
;*****************************************************************************************
;*****************************************************************************************
;* Data: reserved for OSCCAL byte *
;*****************************************************************************************
;*****************************************************************************************
 
; Fix : The Tiny15 has NO SRAM. Use of .DSEG is invalid !
;.DSEG
;
;.SET osccal_location = 0x3FF ;Place in the last byte of program memory.
; ;High byte of program memory 1FF
;
;.ORG osccal_location ;reserve this byte for oscillator
;.BYTE 1 ;calibration value
 
 
; Fixed Version for avra >= 1.2.2
.CSEG
.EQU osccal_location = 0x3FF ; The last flash byte is used for the calibration
; value and is replaced by the programmer
 
; Now reserve the last word in flash memory. If you are sure, that the program doesn't use
; the last flash word, you can disable the following lines. If not, it's better to enable
; them to check for overlapping code segments.
 
.ORG 0x01FF ; Last word in flash memory
.DB 0xff,0xff ; Fill with dummy values. Only last byte is used
; but flash is organized in words.
; 0xff is the value of unprogrammed flash
 
 
;*****************************************************************************************
;*****************************************************************************************
;* Reset and Interrupt Vectors *
;*****************************************************************************************
;*****************************************************************************************
.CSEG
.ORG 0x000
rjmp ST_RESET
 
.ifdef OVERLOAD_ENABLED
rjmp ST_PWM_LEVEL_OFF ; INT0 interrupt handler
.else
reti ; Not used.
.endif ;OVERLOAD_ENABLED
 
reti ; Not used. rjmp PIN_CHANGE
reti ; Not used. rjmp TIM1_CMP
reti ; Not used. rjmp TIM1_OVF
reti ; Not used. rjmp TIM0_OVF
reti ; Not used. rjmp EE_RDY
reti ; Not used. rjmp ANA_COMP
reti ; Not used. rjmp ADC
 
 
;*****************************************************************************************
;*****************************************************************************************
;* Top level routines. The basic program is a state machine, with states all being *
;* top level routines. These routines are never used as subroutines *
;* and therefore can call any subroutine. *
;*****************************************************************************************
;*****************************************************************************************
 
;********************************************************************************
;* ST_RESET *
;* This is power on reset. The reset vector points here. *
;* *
;* Inputs: none *
;* Returns: none *
;* Changed: B_Temp *
;* Calls: *
;* Goto: ST_MOTOR_OFF *
;********************************************************************************
ST_RESET:
cli ; Disable interrupts
 
ldi B_Temp,(dir_out_port_bit | pwm_port_bit | dir_in_port_bit | momentum_port_bit)
out DDRB,B_Temp ; Assign output port directions.
; Inclusion in the above list makes the
; port an output port
 
ldi B_Temp,0x00 ; A "1" makes output logic level high
out PORTB,B_Temp ; A "1" assigns pullups on inputs
; Therefore all outputs are at logic low, and
; all inputs do not have a pullup assigned
 
ldi B_Temp,acsr_val ; Disable comparator and interrupt
out ACSR,B_Temp ; Using port for PWM
; (comparator defaults to powered up)
 
ldi B_Temp,0b01000010 ; Disable pullups.
out MCUCR,B_Temp ; Set sleep mode (moot)
; INT0 interrupt on falling edge
ldi ZL,low(osccal_location) ; r30
ldi ZH,high(osccal_location) ; r31
lpm
out OSCCAL,Implicit ; Place calibration byte
 
ldi B_Temp,0b00001010 ; Enable watchdog
out WDTCR,B_Temp ; timout 64mS (nom)
 
ldi B_Temp1,pwm_period ; Set pwm oscillator period
out OCR1B,B_Temp1
 
ldi B_Temp1,tccr1_enable_t1 ; Turn on the PWM oscillator
out TCCR1,B_Temp1
 
ldi Flags_1,(0b00000000 | F_stop) ; Set emergency stop flag so that
; throttle doesn't start on powerup
.ifdef TRADITIONAL_ENABLED
.ifdef MOMENTUM_LOWPASS_ENABLED
clr momentum_lo_prev ; MOMENTUM LOWPASS
clr momentum_hi_prev ; Clear the history
.endif ;MOMENTUM_LOWPASS_ENABLED
.endif ;TRADITIONAL_ENABLED
 
; rjmp ST_EMERGENCY_STOP ; ***EXIT STATE***
 
;********************************************************************************
;* ST_EMERGENCY_STOP *
;* *
;* Reset to "off" state. *
;* Clear global variables associated with momentum and lowpass filters. *
;* *
;* Inputs: none *
;* Returns: none *
;* Changed: Global variables cleared *
;* Calls: None *
;* Goto: ST_PWM_LEVEL_OFF If throttle is zero *
;********************************************************************************
ST_EMERGENCY_STOP:
 
.ifdef BACKEMF_ENABLED
.ifdef LOWPASS_ENABLED ; BACKEMF LOWPASS
clr error_hi_prev ; Clear the history
clr error_lo_prev
.endif ;LOWPASS_ENABLED
.endif ;BACKEMF_ENABLED
 
.ifdef MOMENTUM_ENABLED ; MOMENTUM
clr speed_lo_prev ; Clear the history
clr speed_hi_prev
.endif ;MOMENTUM_ENABLED
 
.ifdef TRADITIONAL_ENABLED
.ifdef WALKAROUND_ENABLED
clr throttle_hold ; Clear the history
.endif ;WALKAROUND_ENABLED
 
.ifdef THROTTLE_LOWPASS_ENABLED
clr throttle_lo_prev ; THROTTLE LOWPASS
clr throttle_hi_prev ; Clear the history
.endif ;THROTTLE_LOWPASS_ENABLED
 
.endif ;TRADITIONAL_ENABLED
 
; rjmp ST_PWM_LEVEL_OFF ; ***EXIT STATE***
 
 
;********************************************************************************
;* ST_PWM_LEVEL_OFF *
;* ST_MEASUREMENT_SETTLE *
;* 1. If entered at ST_PWM_LEVEL_OFF turn pwm off *
;* 2. Set the ADC ports to input *
;* 3. Pause to let ADC inputs (including back-emf) settle. *
;* 4. Read the throttle controller. *
;* 5. Set LED ports and overload ports (also ADC inputs) to output *
;* 6. If throttle_set is not zero, or if motor is still running by momentum *
;* continue running motor (jump to ST_SET_NEW_PWM) *
;* 7. If throttle set is zero and motor is not running, then set the direction *
;* relay and test backemf input to determine backemf mode. *
;* 8. Turn of motor (jump to ST_PWM_LEVEL_OFF) *
;* *
;* Inputs: none *
;* Returns: none *
;* Changed: B_Temp, B_Temp1 *
;* Calls: READ_THROTTLE *
;* Goto: ST_PWM_LEVEL_OFF If throttle is zero *
;* ST_SET_NEW_PWM After delay *
;********************************************************************************
ST_PWM_LEVEL_OFF:
clr B_Temp ; Set PWM duty = 0.
rcall SET_PWM_DUTY ; i.e. turn off the power
 
ST_MEASUREMENT_SETTLE:
;********************************************
;* Set all measurement ports for input and pause.
;* During the pause:
;* 1. inductive current in the locomotive falls to zero, and
;* the backemf voltage appears on the backemf port
;* 2. the momentum, direction, and throttle voltages stabilize
;********************************************
.ifdef TRADITIONAL_ENABLED
.ifdef LEDS_ENABLED
cbi DDRB,momentum_port ; Make input port (pullup must be disabled)
cbi DDRB,dir_in_port ; Make input port (pullup must be disabled)
.endif ;LEDS_ENABLED
 
.ifdef OVERLOAD_ENABLED
in B_Temp,GIMSK ; disable INT0 interrupt
andi B_Temp,0b10111111
out GIMSK,B_Temp
 
cbi DDRB,throttle_port ; Make input port (pullup must be disabled)
.endif ;OVERLOAD_ENABLED
.endif ;TRADITIONAL_ENABLED
 
sei ; Enable interrupts
wdr ; Reset watchdog timer
 
ldi B_Temp1,pwm_full_count ; Pause for inputs to settle
rcall COUNT_PWM_CYCLES
clr Cycle_count
 
;********************************************
;* Read the input ports and make some
;* mode decisions based on those inputs.
;********************************************
 
rcall READ_THROTTLE ; Find throttle handle position in throttle_set
 
.ifdef TRADITIONAL_ENABLED
.ifdef MOMENTUM_ENABLED
.ifdef MOMENTUM_LOWPASS_ENABLED
.include "throttle_momentum_lowpass.asm"
.endif;MOMENTUM_LOWPASS_ENABLED
.endif; MOMENTUM_ENABLED
.endif ;TRADITIONAL_ENABLED
 
.ifdef DIRECTION_ENABLED ; Check Stop, and Adjust Direction
CHECKING_STOP:
sbrs Flags_1,BF_stop ; Check stop flag is set
rjmp DONE_CHECKING_STOP
 
cpi throttle_set,0x00 ; If throttle handle is at zero
brne ST_EMERGENCY_STOP ; reset the emergency stop flag
cbr Flags_1,F_stop ; reset emergency stop flag.
rjmp ST_EMERGENCY_STOP ; ALWAYS STOP
DONE_CHECKING_STOP:
 
CHECKING_DIRECTION:
 
.ifdef MOMENTUM_ENABLED
mov B_Temp,speed_hi_prev ; Don't set direction unless the actual
cpi B_Temp,direction_threshold ; speed is less than direction_threshold
brsh DONE_CHECKING_DIRECTION
.else
cpi throttle_set,0x00 ; Don't set direction unless the throttle
brne DONE_CHECKING_DIRECTION ; handle is at zero
.endif ;MOMENTUM_ENABLED
 
sbic PORTB,dir_out_port ; Find port direction
rjmp PORT_REVERSE
;rjmp PORT_FORWARD
 
PORT_FORWARD:
sbrs Flags_1,BF_reverse ; If port says forward
rjmp DONE_CHECKING_DIRECTION
sbi PORTB,dir_out_port ; But flag says reverse, then reverse
rjmp ST_EMERGENCY_STOP
PORT_REVERSE:
sbrc Flags_1,BF_reverse ; If port says reverse
rjmp DONE_CHECKING_DIRECTION
cbi PORTB,dir_out_port ; But flag says foreward, then forward
rjmp ST_EMERGENCY_STOP
 
DONE_CHECKING_DIRECTION:
.endif ;DIRECTION_ENABLED
 
.ifdef TRADITIONAL_ENABLED
.ifdef THROTTLE_LOWPASS_ENABLED
.include "throttle_set_lowpass.asm"
.endif ;THROTTLE_LOWPASS_ENABLED
.endif ;TRADITIONAL_ENABLED
 
cpi throttle_set,0x00 ; Run the pwm unless the throttle
brne ST_SET_NEW_PWM ; is zero
 
.ifdef MOMENTUM_ENABLED
mov B_Temp,speed_hi_prev ; In momentum mode, run the pwm unless
cpi B_Temp,0x00 ; the actual throttle setting reaches zero
brne ST_SET_NEW_PWM
.endif ;MOMENTUM_ENABLED
 
;********************************************
;* Only arrive here if the throttle is set for 0 speed
;* and the locomotive is actually stopped (momentum)
;********************************************
 
.ifdef BACKEMF_ENABLED
;********************************************
;* The backemf measurement should be at or near zero,
;* since the locomotive is stopped. If it isn't,
;* do not use backemf speed control.
;********************************************
sbr Flags_1,F_use_backemf ; Default to use backemf
 
rcall ADC_SETUP_EMF ; 4 lines read the backemf
WAIT_FOR_VALID:
sbis ADCSR,ADIF
rjmp WAIT_FOR_VALID
in B_Temp,ADCH ; Read the measurement
 
cpi B_Temp,0x40 ; Test measurement
brlo END_CHECK_BACKEMF_MODE ; If small, use backemf adjustment.
 
cbr Flags_1,F_use_backemf ; Otherwise, don't use backemf
END_CHECK_BACKEMF_MODE:
.endif ;BACKEMF_ENABLED
 
.ifdef TRADITIONAL_ENABLED
.ifdef LOCO_LIGHT_ENABLED
ldi throttle_set,light_pwm
rjmp STABLE_PWM_SET
.else
rjmp ST_PWM_LEVEL_OFF
.endif ;LOCO_LIGHT_ON
.else
rjmp ST_PWM_LEVEL_OFF
.endif ;TRADITIONAL_ENABLED
 
 
;********************************************************************************
;* ST_SET_NEW_PWM *
;* Compute the pwm setting based upon momentum, backemf, and throttle setting *
;* Inputs: throttle_set *
;* Returns: none *
;* Changed: throttle_set, other variables in included files *
;* Calls: various in included files *
;* Goto: ST_PWM_LEVEL_ON *
;********************************************************************************
ST_SET_NEW_PWM:
 
.ifdef TRADITIONAL_ENABLED
.ifdef LEDS_ENABLED
cbi PORTB,dir_in_port ; logic low out (turn off LED)
sbi DDRB,dir_in_port ; Assign output to drive led (output is low)
 
cbi PORTB,momentum_port ; logic low out (turn off LED)
sbi DDRB,momentum_port ; Assign output to drive led (output is low)
.endif ;LEDS_ENABLED
 
.ifdef OVERLOAD_ENABLED
;********************************************
;* The thottle port is driven to logic high. If this port gets pulled
;* low (overload), this triggers the INT0 interrupt, which will shut off
;* the pwm.
;********************************************
sbi PORTB,throttle_port ; Logic hi out.
sbi DDRB,throttle_port ; Make output port.
.endif ;OVERLOAD_ENABLED
.endif ;TRADITIONAL_ENABLED
 
.ifdef MOMENTUM_ENABLED
.include "throttle_momentum.asm" ; momentum adjustment
.endif ;MOMENTUM_ENABLED
 
.ifdef TRADITIONAL_ENABLED
.ifdef WALKAROUND_ENABLED
mov throttle_hold,throttle_set
.endif ;WALKAROUND_ENABLED
.endif ;TRADITIONAL_ENABLED
 
.ifdef BACKEMF_ENABLED ;********************************************
; Adjust throttle_set according to
; measured backemf.
;********************************************
sbrs Flags_1,BF_use_backemf ; If the flag is set, use backemf
rjmp DONT_BACKEMF ; Otherwise, don't
 
.include "throttle_backemf.asm"
; If using backemf, don't use throttle_scale
rjmp ST_PWM_LEVEL_ON ; ***EXIT STATE***
 
DONT_BACKEMF:
.endif ;BACKEMF
 
 
;*****************************************************************
;* Scale the throttle_set between 0 and pwm_period *
;* multiply pwm_period and throttle_set and divide by 256 *
;* read answer from hi byte of return. *
;*****************************************************************
 
 
HILOCAL1 _main_scale_multiplicand
B_TEMPLOCAL _main_scale_multiplier
B_TEMPLOCAL1 _main_scale_result_hi
 
ldi _main_scale_multiplicand,pwm_period - pwm_min
mov _main_scale_multiplier,throttle_set
rcall mpy8u ; multiply
mov throttle_set,_main_scale_result_hi ; read result
 
; rjmp ST_PWM_LEVEL_ON ; ***EXIT STATE***
 
 
;********************************************************************************
;* ST_PWM_LEVEL_ON *
;* 1. Enable overload testing *
;* 2. Produce pulse if required *
;* 3. Run pwm at throttle_set *
;* 4. Wait for a while *
;* *
;* Inputs: throttle_set *
;* Returns: none *
;* Changed: B_Temp, B_Temp1, various *
;* Calls: SET_PWM_DUTY *
;* COUNT_PWM_CYCLES *
;* Goto: ST_PWM_LEVEL_OFF After PWM goes to off state *
;********************************************************************************
ST_PWM_LEVEL_ON:
 
.ifdef TRADITIONAL_ENABLED
.ifdef OVERLOAD_ENABLED
ldi B_Temp,0b01000000 ; clear INT0 interrupt
out GIFR,B_Temp
 
in B_Temp,GIMSK ; enable INT0 interrupt
ori B_Temp,0b01000000
out GIMSK,B_Temp
.endif ;OVERLOAD_ENABLED
.endif ;TRADITIONAL_ENABLED
 
cpi throttle_set,light_pwm ; never run pwm lower than light_pwm level
brsh DONE_CHECKING_MINIMUM
ldi throttle_set,light_pwm
rjmp STABLE_PWM_SET
 
DONE_CHECKING_MINIMUM:
 
.ifdef PULSE_ENABLED ; Produce pulses during output
.ifdef BACKEMF_ENABLED
sbrc Flags_1,BF_use_backemf ; If the flag is set to use backemf
rjmp STABLE_PWM_SET ; don't pulse
.endif ;BACKEMF_ENABLED
; Pass in: throttle_set
.include "throttle_pulse.asm"
.endif ;PULSE_ENABLED
 
 
STABLE_PWM_SET:
mov B_Temp,throttle_set ; Stabilize at throttle_set
rcall SET_PWM_DUTY
 
ldi B_Temp1,pwm_full_count-pwm_settle_count
rcall COUNT_PWM_CYCLES ; Wait for end of interval
 
.ifdef BACKEMF_ENABLED
sbrc Flags_1,BF_use_backemf ; If the flag is set to use backemf
rjmp ST_PWM_LEVEL_OFF ; ***EXIT STATE***
.endif ;BACKEMF_ENABLED
rjmp ST_MEASUREMENT_SETTLE ; ***EXIT STATE***
 
;*****************************************************************************************
;*****************************************************************************************
;* First Level Subroutines. *
;* These routines include the routines which are called by other code and also call *
;* Second Level Subroutines. *
;*****************************************************************************************
;*****************************************************************************************
 
;********************************************************************************
;* READ_THROTTLE *
;* First Level Subroutine *
;* *
;* Read the throttle controls, which are: *
;* Momentum level (analog): Returned in "momentum_set" *
;* Returns and 8 bit number, with '0' meaning minimum momentum. *
;* *
;* Direction, brake, and stop switch. *
;* Returns value in flags: F_brake, F_reverse, and F_stop *
;* *
;* Throttle setting (analog: Returned in "throttle_set" *
;* Returns an 8 bit number (0x00 to 0xFF; 0 to 255), *
;* where '0' means "motor off" and 0xFF (255) means full speed. *
;* *
;* If a speed table is implemented, it will be in this routine *
;* *
;* Just now, this value comes from the analog input and is converted by the *
;* ADC. The raw 8 bit number is returned. *
;* *
;* Inputs: None *
;* Returns: Momentum setting in "momentum_set" *
;* Switch positions in F_brake, F_reverse, and F_stop *
;* Throttle setting in "throttle_set" *
;* Changed: Cycle_count incremented by up to 5 *
;* Calls: ADC_SETUP_MOMENTUM *
;* ADC_SETUP_DIRECTION *
;* ADC_SETUP_THROTTLE *
;********************************************************************************
READ_THROTTLE:
.ifdef TRADITIONAL_ENABLED
.ifdef DIRECTION_ENABLED
;********************************************
;* Measure the direction, brake, and stop switches and
;* set the flags appropriately
;********************************************
rcall ADC_SETUP_DIRECTION ; Setup to read
WAIT_FOR_VALID_DIRECTION:
sbis ADCSR,ADIF ; Check for ADC completion
rjmp WAIT_FOR_VALID_DIRECTION
 
in B_Temp,ADCH ; Read value
 
.ifdef WALKAROUND_ENABLED
cpi B_Temp,0x90 ; Above this threshold
; deactivates handheld controller
; brsh HOLD_THROTTLE
 
brlo HOLD_THROTTLE_NOT
rjmp HOLD_THROTTLE
HOLD_THROTTLE_NOT:
.endif ;WALKAROUND_ENABLED
 
cpi B_Temp,0x1B ; Below this threshold (0.53V) sets 'stop' flag
brsh TEST_BRAKE_LEVEL ; Typical stop voltage is 0.30V
 
.ifdef SWITCH_LOWPASS_ENABLED
sbrs Flags_2,BF_stop_count ; If the stop count flag is not set, then
clr Flags_2 ; set the counter to zero
 
cbr Flags_2,F_stop_count ; clear the stop count flag
inc Flags_2 ; increment the counter
 
cpi Flags_2,stop_count_max ; compare the count to the maximum
sbr Flags_2,F_stop_count ; set the stop count flag
 
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag
 
dec Flags_2,F_stop_count ; decrement stop count flag
.endif;SWITCH_LOWPASS_ENABLED
 
sbr Flags_1,F_stop
rjmp END_READ_DIRECTION
 
TEST_BRAKE_LEVEL:
cpi B_Temp,0x37 ; Below this threshold (1.07V) sets 'brake' flag
brsh TEST_REVERSE_LEVEL ; Typical brake voltage 0.87V
 
.ifdef SWITCH_LOWPASS_ENABLED
sbrs Flags_2,BF_brake_count ; If the brake count flag is not set, then
clr Flags_2 ; set the counter to zero
 
cbr Flags_2,F_brake_count ; clear the break count flag
inc Flags_2 ; increment the counter
 
cpi Flags_2,brake_count_max ; compare the count to the maximum
sbr Flags_2,F_brake_count ; set the break count flag
 
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag
 
dec Flags_2,F_brake_count ; decrement break count flag
.endif;SWITCH_LOWPASS_ENABLED
 
sbr Flags_1,F_brake
rjmp END_READ_DIRECTION
 
TEST_REVERSE_LEVEL:
cpi B_Temp,0x53 ; Below this threshold (1.62V) sets 'reverse' flag
brsh TEST_FOREWARD_LEVEL ; Typical reverse level 1.40V
 
.ifdef SWITCH_LOWPASS_ENABLED
sbrs Flags_2,BF_reverse_count ; If the reverse count flag is not set, then
clr Flags_2 ; set the counter to zero
 
cbr Flags_2,F_reverse_count ; clear the reverse count flag
inc Flags_2 ; increment the counter
 
cpi Flags_2,reverse_count_max ; compare the count to the maximum
sbr Flags_2,F_reverse_count ; set the reverse count flag
 
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag
 
dec Flags_2,F_reverse_count ; decrement reverse count flag
.endif;SWITCH_LOWPASS_ENABLED
 
cbr Flags_1,F_brake ; Clear brake flag
sbr Flags_1,F_reverse ; Set brake flag
rjmp END_READ_DIRECTION
 
TEST_FOREWARD_LEVEL: ; Typical "nothing" 1.95V
;no test required
 
.ifdef SWITCH_LOWPASS_ENABLED
sbrs Flags_2,BF_foreward_count ; If the foreward count flag is not set, then
clr Flags_2 ; set the counter to zero
 
cbr Flags_2,F_foreward_count ; clear the foreward count flag
inc Flags_2 ; increment the counter
 
cpi Flags_2,foreward_count_max ; compare the count to the maximum
sbr Flags_2,F_foreward_count ; set the foreward count flag
 
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag
 
dec Flags_2,F_foreward_count ; decrement forward count flag
.endif;SWITCH_LOWPASS_ENABLED
 
cbr Flags_1,F_brake ; Clear brake flag
cbr Flags_1,F_reverse ; Clear reverse flag (i.e., foreward)
 
END_READ_DIRECTION:
.endif ;DIRECTION_ENABLED
 
.ifdef MOMENTUM_ENABLED
;********************************************
;* Measure and adjust the momentum input
;********************************************
rcall ADC_SETUP_MOMENTUM ; Setup to read
WAIT_FOR_VALID_MOMENTUM:
sbis ADCSR,ADIF ; Wait for ADC completion
rjmp WAIT_FOR_VALID_MOMENTUM
in momentum_set,ADCH ; Read value
 
.ifdef WALKAROUND_ENABLED
ldi B_Temp,0x90
cp momentum_set,B_Temp ; Above this threshold
; deactivates handheld controller
brsh HOLD_THROTTLE
.endif ;WALKAROUND_ENABLED
 
ldi B_Temp,0x40
sub momentum_set,B_Temp ; Subtract offset (1/4 of 0xFF)
brsh END_READ_MOMENTUM
sub momentum_set,momentum_set ; If smaller than offset, make zero
 
END_READ_MOMENTUM:
.endif ;MOMENTUM_ENABLED
 
;********************************************
;* Read the throttle level
;********************************************
rcall ADC_SETUP_THROTTLE
WAIT_FOR_VALID_THROTTLE:
sbis ADCSR,ADIF ; Check for ADC completion
rjmp WAIT_FOR_VALID_THROTTLE
 
in throttle_set,ADCH ; Read throttle value
 
subi throttle_set,0x08 ; Subtract offset (force zero)
brcc DONE_READ_THROTTLE ; If new throttle is negative,
 
clr throttle_set ; make throttle zero.
DONE_READ_THROTTLE:
 
subi Cycle_count,256-3 ; Normal arrival here occurs after 3 adc
ret ; conversions, which take 195uS, or 4.875
; pwm cycles
.ifdef WALKAROUND_ENABLED
HOLD_THROTTLE: ; Normal arrival here occurs after 1 adc
; conversion, which takes 65uS, or 1.625
; pwm cycles
 
cbr Flags_1,F_brake ; Clear brake flag
mov throttle_set,throttle_hold ; Use previous value.
 
.ifdef SWITCH_LOWPASS_ENABLED
clr Flags_2
.endif;SWITCH_LOWPASS_ENABLED
 
.ifdef MOMENTUM_ENABLED
ldi B_Temp,0x40
mov momentum_set,B_Temp ; 'long' momentum
.endif ;MOMENTUM_ENABLED
ret
.endif ;WALKAROUND_ENABLED
 
.else ;NOT TRADITIONAL_THROTTLE
sbr Flags_1,F_stop
ret
.endif ;TRADITIONAL_THROTTLE
 
 
;********************************************************************************
;* COUNT_PWM_CYCLES *
;* First evel Subroutine *
;* *
;* Increment Cycle_count timer each PWM cycle. *
;* Return when Cycle_count = B_Temp1 *
;* *
;* Inputs: B_Temp1 Exit when count reaches this number *
;* Returns: None *
;* Changed: B_Temp,Cycle_count *
;* Calls: None *
;********************************************************************************
COUNT_PWM_CYCLES:
in B_Temp,TIFR ; Wait for pwm timer to reset
sbrs B_Temp,OCF1A
rjmp COUNT_PWM_CYCLES
ldi B_Temp,0b01000000 ; reset interrupt flag
out TIFR,B_Temp
 
inc Cycle_count ; increment counter and repeat
cp Cycle_count,B_Temp1
brne COUNT_PWM_CYCLES
ret
 
;*****************************************************************************************
;*****************************************************************************************
;* Second Level Subroutines. *
;* These routines make no further subroutine calls. *
;*****************************************************************************************
;*****************************************************************************************
 
.include "throttle_divide.asm"
 
.include "throttle_multiply.asm"
 
;********************************************************************************
;* SET_PWM_DUTY *
;* Second Level Subroutine *
;* *
;* Inputs: B_Temp PWM on count *
;* Returns: None *
;* Changed: None *
;* Calls: Not allowed *
;********************************************************************************
SET_PWM_DUTY:
 
out OCR1A,B_Temp ; Set the PWM equal to the input B_Temp
ret
 
;********************************************************************************
;* ADC_SETUP_DIRECTION *
;* ADC_SETUP_MOMENTUM *
;* ADC_SETUP_THROTTLE *
;* ADC_SETUP_BACK_EMF *
;* Second Level Subroutine *
;* *
;* The ADC is switched off, and restarted on the selected port. *
;* *
;* Inputs: None *
;* Returns: None *
;* Changed: Various B_Temp variables *
;* Calls: Not allowed *
;********************************************************************************
.ifdef DIRECTION_ENABLED
ADC_SETUP_DIRECTION:
ldi B_Temp,admux_direction ; Setup MUX for direction/brake measurement
rjmp ADC_SETUP
.endif ;DIRECTION_ENABLED
 
.ifdef MOMENTUM_ENABLED
ADC_SETUP_MOMENTUM:
ldi B_Temp,admux_momentum ; Setup MUX for momentum set measurement
rjmp ADC_SETUP
.endif ;MOMENUTM_ENABLED
 
.ifdef BACKEMF_ENABLED
ADC_SETUP_EMF:
ldi B_Temp,admux_emf ; Setup MUX for back_emf measurement
rjmp ADC_SETUP
.endif ;BACKEMF_ENABLED
 
.ifdef TRADITIONAL_ENABLED
ADC_SETUP_THROTTLE:
ldi B_Temp,admux_throttle ; Setup MUX for analog measure
; rjmp ADC_SETUP ; of throttle.
.endif ;TRADITIONAL_ENABLED
ADC_SETUP:
ldi B_Temp1,adcsr_off ; Turn off the ADC
out ADCSR,B_Temp1 ;
out ADMUX,B_Temp ; Setup MUX as per entry point
ldi B_Temp,adcsr_enable ; enable ADC, disable interrupt, clear
out ADCSR,B_Temp ; interrupt flag, free-running.
ret
 
 
;*****************************************************************************************
;*****************************************************************************************
;* Interrupt Service routines. *
;* These routines can occur assynchronously. Therfore, they might occur during a second *
;* level routine. Therefore THEY MAY NOT CALL ANY SUBROUTINES. *
;*****************************************************************************************
;*****************************************************************************************
/contrib/toolchain/avra/examples/throttle_backemf.asm
0,0 → 1,328
;throttle_backemf.asm
 
.NOLIST
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
.LIST
 
.ifdef BACKEMF_ENABLED
;********************************************************************************
;* BACKEMF_ADJUST *
;* Top level routine *
;* *
;* The throttle_set is compared against the back emf generated by the motor *
;* and adjusted to reduce the error *
;* *
;* Inputs: throttle_set Target speed *
;* Returns: throttle_set Adjusted target speed *
;* Changed: error_hi Adjusted throttle, upper 8 bits (local) *
;* error_lo Adjusted throttle, lower 8 bits (local) *
;* error_hi_prev Previous throttle, for filter (global) *
;* error_lo_prev Previous throttle, for filter (global) *
;* emf_hi Measured emf, upper 8 bits (local) *
;* emf_lo Measured emf, lower 8 bits (local) *
;* B_Temp,B_Temp1 *
;* Calls: ADC_SETUP_EMF *
;* div16u *
;* DIVIDE_16_SIMPLE *
;* Goto: none *
;********************************************************************************
 
HILOCAL1 error_lo ; assign local variables
HILOCAL2 error_hi
 
;*****************************************************************
;*Convert throttle setting into 2 byte 2's compl. *
;* *
;* This is a 7 bit number plus 1 more bits after the radix *
;* It is in (error_hi) -radix- (error_lo) *
;*****************************************************************
mov error_hi,throttle_set ; Put throttle into 16 bit form
clr error_lo
 
lsr error_hi ; Convert to 2's compliment
ror error_lo
 
;********************************************************************************
;* READ_BACKEMF *
;* Returns a 2 byte 2's compliment measurement of the motor backemf. *
;* *
;* 1. Add together 8 samples of the (8 bit) pwm value in the two byte *
;* emf_hi--emf_lo register. *
;* 2. Multiply by 16. *
;* 3. Result: Minimum value = 0x000 (decimal 0) *
;* Maximum value = 0x7F8 (decimal 2040) *
;* *
;* Time required: *
;* 1. 1st Sample: 125uS *
;* 2. next 7 Samples: 455uS *
;* 3. balance of Subroutine: 10's of uS *
;* TOTAL 580uS min *
;* *
;* Each cycle of the 25kHz PWM takes 40uS, therefore, this routine takes *
;* at least 14.5 cycles of the 25kHz pwm. *
;* *
;* Inputs: None *
;* Returns: emf_hi--emf_lo: 2 Byte 2's compl (but always positive) *
;* measure of motor backemf. *
;* Changed: B_Temp,B_Temp1 *
;* Calls: ADC_SETUP_EMF *
;********************************************************************************
LOWLOCAL1 emf_hi ; Names of local registers
LOWLOCAL2 emf_lo
 
;READ_BACKEMF:
rcall ADC_SETUP_EMF ; Setup ADC to measure back_emf.
clr emf_lo ; Clear the value of emf.
clr emf_hi
 
ldi B_Temp,8 ; Add 8 samples
WAIT_FOR_EMF_MEASURE: ; Wait for a measurement of the EMF
sbis ADCSR,ADIF
rjmp WAIT_FOR_EMF_MEASURE
in B_Temp1,ADCH ; Read the measurement
 
sbi ADCSR,4 ; Clear the interrupt
 
add emf_lo,B_Temp1 ; Add to low byte (no carry)
 
clr B_Temp1
adc emf_hi,B_Temp1 ; Add carry to high byte.
 
dec B_Temp
brne WAIT_FOR_EMF_MEASURE ; Measure for complete set
; Sum of 8 samples.
 
ldi B_Temp,4 ; Convert 11 bit number into a 15 bit
COMPUTE_EMF_AVERAGE: ; number (only 11 significant figures
lsl emf_lo ; though)
rol emf_hi
dec B_Temp
brne COMPUTE_EMF_AVERAGE
 
;*****************************************************************
;* Compute the error. That is, throttle = throttle - emf *
;* *
;* The result is a two byte number (signed two's compl) in *
;* error_hi -radix- error_lo *
;*****************************************************************
sub error_lo,emf_lo ; subtract low bytes (after radix)
sbc error_hi,emf_hi ; subtract high bytes (before radix)
 
.ifdef BACKEMF_SCALE_ENABLED
;*****************************************************************
;* Error multiplier (complex) *
;* *
;* Error gain is equal to: *
;* *
;* Error err_scale err_mult *
;* ------------------------ * 2 * 2 *
;* err_scale *
;* 2 + throttle_set *
;* *
;* The maximum gain when throttle_set = 0 is 2^err_mult *
;* is cut in half when throttle_set = 2^err_scale *
;* *
;* Result is signed two's compliment in *
;* error_hi--error_lo -radix- *
;*****************************************************************
cbr Flags_1,F_negative_err ; Assume error is positive
sbrs error_hi,7 ; Test algebraic sign
rjmp POSITIVE_ERR
 
sbr Flags_1,F_negative_err ; If error is negative, set flag.
com error_lo ; Convert to positive
com error_hi
subi error_lo,0xFF
sbci error_hi,0xFF
 
POSITIVE_ERR:
 
B_TEMPLOCAL _bemf_lo_byte
B_TEMPLOCAL1 _bemf_hi_byte
 
mov _bemf_lo_byte,throttle_set ; Divisor = throttle_set+2^err_scale
clr _bemf_hi_byte
ldi B_Temp2,EXP2(err_scale)
add _bemf_lo_byte,B_Temp2
adc _bemf_hi_byte,_bemf_hi_byte
 
; mov dd16uL,error_lo ; Dividend = error (same register)
; mov dd16uH,error_hi
 
rcall div16u ; Divide error by (throttle+offset)
; (almost 4 pwm cycles)
; adds 3 to Cycle_count
 
; mov error_lo,dres16uL ; Same register
; mov error_hi,dres16uH
 
sbrs Flags_1,BF_negative_err ; Check sign flag
rjmp POSITIVE_ERR_1
 
com error_lo ; Convert back to negative
com error_hi ; if necessary
subi error_lo,0xFF
sbci error_hi,0xFF
 
POSITIVE_ERR_1: ; Scale for maximum
ldi _bemf_lo_byte, 7 - error_mult - err_scale
rcall DIVIDE_16_SIMPLE
 
.else ;case BACKEMF_SCALE_ENABLED is NOT enabled
;*****************************************************************
;* Error multiplier (simple) *
;* *
;* The error multiplier setting (error_mult) can range *
;* from -8 to +7, and the actual error multiplier is *
;* 2^(error_mult), which therefore ranges from 1/256 to 128. *
;* *
;* Step 1. Multiply by 2^8. *
;* Equivalent to moving the radix point to after *
;* error_lo. THIS STEP REQUIRES NO CODE *
;* *
;* Step 2. Divide by 2^(error_mult - 8) *
;* *
;* Result is signed two's compliment in *
;* error_hi--error_lo -radix- *
;*****************************************************************
 
ldi _bemf_lo_byte, 7 - error_mult
rcall DIVIDE_16_SIMPLE
 
.endif ;BACKEMF_SCALE_ENABLED
 
 
COMPUTE_NEW_PWM:
;*****************************************************************
;* Add in the original throttle *
;*****************************************************************
add error_lo,throttle_set
clr B_Temp
adc error_hi,B_Temp
 
;*****************************************************************
;* Clamp to between 0 and +255 *
;*****************************************************************
brmi SET_ZERO_PWM ; If result is NEGATIVE, set to zero.
 
cpi error_hi,0x00 ; If hi byte is zero, result is ok.
breq LOWPASS
ldi error_lo,0xFF ; otherwise, clamp
rjmp LOWPASS
 
SET_ZERO_PWM:
clr error_lo
 
LOWPASS:
 
.ifdef LOWPASS_ENABLED
;*****************************************************************
;* A transversal low pass filter *
;* Lowpass on the emf-adjusted pwm *
;* *
;* gain input "emf_lowpass_gain", range = 0 to 8 *
;* *
;* The actual filter time constant "tau" is equal to *
;* tau = 2^emf_lowpass_gain * sample_interval *
;* *
;* The sample interval is nominally 10mS, so the time *
;* constant values are: *
;* 0 1 2 3 4 5 6 7 8 *
;* 10mS,20mS,40mS,80mS,160mS,320mS,640mS,1.28S,2.56S *
;* *
;* The current sample is added to an attenuated sum of previous *
;* samples as follows: *
;* *
;* Adjusted Value = 1/(2^gain) x *
;* ( 1x sample number (i) *
;* + gain x sample number (i-1) *
;* + gain^2 x sample number (i-2) *
;* + gain^3 x sample number (i-3) *
;* + .... *
;* ) *
;* Where: *
;* Gain values: gain = (2^emf_lowpass_gain - 1) / 2^n *
;* 0,1/2,3/4,7/8,15/16 ... 255/256 *
;* *
;* Algorithm: *
;* *
;* -Input (current sample) in error_lo (error_hi=0) *
;* 0x00FF max *
;* *
;* -Input (scaled sum of previous samples) in *
;* error_hi_prev--error_lo_prev. *
;* 0x00FF * (2^emf_lowpass_gain - 1 ) max *
;* *
;* 1. The error_hi_prev--error_lo_prev is added to *
;* error_hi--error_lo *
;* 0x00FF * (2^emf_lowpass_gain) max *
;* *
;* 2. This value is also stored in *
;* error_hi_prev--error_lo_prev *
;* *
;* 3. The value (error_hi--error_lo) is divided by *
;* 2^emf_lowpass_gain (resulting in lowpass value, *
;* max 0x00FF) *
;* *
;* 4. The value (error_hi--error_lo) is subtracted from *
;* error_hi_prev--error_lo_prev. This is the new *
;* stored value. *
;*****************************************************************
clr error_hi
 
;****
;* 1. Add in cumulative previous error
;****
add error_lo,error_lo_prev ; Add in scaled previous samples
adc error_hi,error_hi_prev ;
 
;****
;* 2. Store
;****
mov error_lo_prev,error_lo ; Store new value
mov error_hi_prev,error_hi ; Store new value
 
;****
;* 3. Divide new value
;****
ldi _bemf_lo_byte,emf_lowpass_gain
rcall DIVIDE_16_SIMPLE
 
;****
;* 4. New value in error_prev
;****
ADJUST_STORED:
sub error_lo_prev,error_lo
sbc error_hi_prev,error_hi
 
.endif ;LOWPASS_FILTER
 
mov throttle_set,error_lo
subi Cycle_count,256-15 ; Normal arrival here occurs after 3.5 + 14.5 +
; pwm cycles. Add 15 counts here, also 3 added in
; div16u
 
.endif BACKEMF_ENABLED
/contrib/toolchain/avra/examples/throttle_dev_set.inc
0,0 → 1,348
;throttle_dev_set.inc
 
.NOLIST
 
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
 
;*********************************************************
;* Hardware Settings *
;*********************************************************
 
;
; REGISTER ASSGINMENTS
; Note that registes 16 - 31 are acessed by a larger instruction
; set than registers 0 - 15.
;
 
 
;*********************************************************
; REGISTER ASSIGNMENTS
; GLOBAL VISIBILITY ;all functions have access to this NAME of the register
; GLOBAL DURATION ;the register always MEANS the same thing.
;*********************************************************
.DEF Flags_1= r16 ; Global. Status flags
.DEF Cycle_count= r17 ; Global. Count PWM cycles
.DEF throttle_set= r18 ; Global. Current Throttle Setting
 
.ifdef SWITCH_LOWPASS ENABLED
.DEF Flags_2= r19 ; Global. Switch "status" flags
.endif SWITCH_LOWPASS_ENABLED
 
.ifdef MOMENTUM_ENABLED
.DEF momentum_set= r4 ; Global. Input control
.endif ;MOMENTUM_ENABLED
 
.ifdef TRADITIONAL_ENABLED
.ifdef WALKAROUND_ENABLED
.DEF throttle_hold= r14 ; Global. Previous throttle setting
.DEF Flags_2= r19 ; Global. Switch "status" flags
.endif ;WALKAROUND_ENABLED
.endif ;TRADITIONAL_ENABLED
 
;*********************************************************
; REGISTER ASSIGNMENTS
; LOCAL VISIBILITY ;only the translation unit has (should have)
; access to any NAME of the register
; GLOBAL DURATION ;the register always MEANS the same thing.
;*********************************************************
.ifdef MOMENTUM_ENABLED
.ifdef LOWPASS_ENABLED
.DEF error_hi_prev= r2 ; Global. History of error
.DEF error_lo_prev= r3 ; Global. History of error
.endif ;LOWPASS_ENABLED
.endif ;MOMENTUM_ENABLED
 
.ifdef TRADITIONAL_ENABLED
 
.ifdef THROTTLE_LOWPASS_ENABLED
.DEF throttle_hi_prev= r9 ; Global. History of throttle handle
.DEF throttle_lo_prev= r10 ; Global. History of throttle handle
.endif ;THROTTLE_LOWPASS_ENABLED
 
.ifdef MOMENTUM_LOWPASS_ENABLED
.DEF momentum_hi_prev= r11 ; Global. History of momentum handle
.DEF momentum_lo_prev= r12 ; Global. History of momentum handle
.endif ;THROTTLE_LOWPASS_ENABLED
 
.endif ;TRADITIONAL_ENABLED
 
.ifdef MOMENTUM_ENABLED
.DEF speed_hi_prev= r5 ; Global. Speed at last sample time
.DEF speed_lo_prev= r6 ; Global. Speed at last sample time
.endif ;MOMENTUM_ENABLED
 
 
;*********************************************************
; REGISTER ASSIGNMENTS
; LOCAL VISIBILITY ;only the translation unit has (should have)
; access to any NAME of the register
; LOCAL DURATION ;the register has different meanings in different contexts
;*********************************************************
.DEF Implicit= r0 ; Local. Used for implicit lpm
.DEF Sreg_stack= r1 ; Local. "stack" for SREG during interrupts
 
; .DEF ZL= r30 ; Local. Used for Z pointer (low byte)
; .DEF ZH= r31 ; Local. Used for Z pointer (high byte)
 
.MACRO LOWLOCAL1
.DEF @0 = r7 ; Local. General Use
.ENDMACRO
 
.MACRO LOWLOCAL2
.DEF @0 = r8 ; Local. General Use
.ENDMACRO
 
.MACRO HILOCAL1
.DEF @0 = r26 ; Local. General Use
.ENDMACRO
 
.MACRO HILOCAL2
.DEF @0 = r27 ; Local. General Use
.ENDMACRO
 
;*********************************************************
; REGISTER ASSIGNMENTS
; GLOBAL VISIBILITY ;all functions have access to this NAME of the register
; LOCAL DURATION ;the register has different meanings in different contexts
;*********************************************************
.MACRO B_TEMPLOCAL
.DEF @0 = r23 ; Local. Second Level Routine Safe
.ENDMACRO
 
.MACRO B_TEMPLOCAL1
.DEF @0 = r24 ; Local. Second Level Routine Safe
.ENDMACRO
 
.MACRO B_TEMPLOCAL2
.DEF @0 = r25 ; Local. Second Level Routine Safe
.ENDMACRO
 
B_TEMPLOCAL B_Temp ; General use names
B_TEMPLOCAL1 B_Temp1
B_TEMPLOCAL2 b_Temp2
 
;ISR LOCALS
 
; UNUSED
 
;.DEF Not_used= r29
 
; GLOBALS
 
 
;FLAGS_1 flag data
 
;.SET F_Flags_1= 0b11111111 ; All flags
 
.SET F_accel= 0b00000001 ; Accelerating if 1, decel if 0
.SET BF_accel= 0x00 ; Flag bit location
.SET F_brake= 0b00000010 ; Brake set if 1
.SET BF_brake= 0x01 ;
.SET F_stop= 0b00000100
.SET BF_stop= 0x02
.SET F_reverse= 0b00001000
.SET BF_reverse= 0x03
.SET F_negative_err= 0b00010000
.SET BF_negative_err= 0x04
.SET F_use_backemf= 0b00100000
.SET BF_use_backemf= 0x05
;.SET F_= 0b01000000
;.SET BF_= 0x06
;.SET F_= 0b10000000
;.SET BF_= 0x07
 
.ifdef SWITCH_LOWPASS_ENABLED
;FLAGS_2 flag data - count and status for forward/reverse/brake/stop
 
.SET F_Flags_2= 0b00001111 ; All flags
 
.SET F_stop_count= 0b00010000
.SET BF_stop_count= 0x04
.SET F_brake_count= 0b00100000
.SET BF_brake_count= 0x05
.SET F_reverse_count= 0b01000000
.SET BF_reverse_count= 0x06
.SET F_foreward_count= 0b10000000
.SET BF_foreward_count= 0x07
 
;bits 0-3 the count- from 0-16
 
.endif SWITCH_LOWPASS_ENABLED
 
;PORT SETUP STUFF
.SET emf_port= 0x05 ;PB5 - INPUT -- Back EMF input
.SET emf_port_bit= 0b00100000 ;PIN1 ADC0
 
.SET momentum_port= 0x04 ;PB4 - INPUT -- Momentum Level input
.SET momentum_port_bit= 0b00010000 ;PIN2 ADC3 Acceleration-indicator output
 
.SET dir_in_port= 0x03 ;PB3 - INPUT -- Direction/Brake
.SET dir_in_port_bit= 0b00001000 ;PIN3 ADC2 Deceleration-indicator output
 
.SET throttle_port= 0x02 ;PB2 - INPUT -- Throttle Handle MAY USE INT0
.SET throttle_port_bit= 0b00000100 ;PIN7 ADC1 (Could also use INTO
; INT0 as DCC input.)
 
.SET pwm_port= 0x01 ;PB1 - OUTPUT -- PWM (off L)
.SET pwm_port_bit= 0b00000010 ;PIN6 NO ADC
; ONLY PWM PIN.
 
.SET dir_out_port= 0x00 ;PB0 - OUTPUT -- '1' = forward
.SET dir_out_port_bit= 0b00000001 ;PIN5 NO ADC '0' = reverse
 
 
 
 
.SET acsr_val= 0b10000000 ; bit 7 --AC0 1 --comparator disabled
 
.SET eecr_read_enable= 0b00000001 ; bit 4,5,6,7 --unused
; bit 3 --EERIE 0 --interrupt disabled
; bit 2 --EEMWE 0 --master write disabled
; bit 1 --EEWE 0 --write disabled
; bit 0 --EERE 1 --read ENABLED
.SET eecr_mwrite_enable= 0b00000100 ; bit 4,5,6,7 --unused
; bit 3 --EERIE 0 --interrupt disabled
; bit 2 --EEMWE 1 --master write ENABLED
; bit 1 --EEWE 0 --write disabled
; bit 0 --EERE 0 --read disabled
.SET eecr_write_enable= 0b00000110 ; bit 4,5,6,7 --unused
; bit 3 --EERIE 0 --interrupt disabled
; bit 2 --EEMWE 1 --master write ENABLED
; bit 1 --EEWE 1 --write ENABLED
; bit 0 --EERE 0 --read disabled
 
.SET admux_emf= 0b00100000 ; bit 4,3 --unused
; bit 7 --REFS1 0 Two bits:
; bit 6 --REFS0 0 Select VCC volt reference
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
; bit 2 --MUX2 0 Three bits:
; bit 1 --MUX1 0
; bit 0 --MUX0 0 Select ADC0 from PB5
 
.SET admux_throttle= 0b00100001 ; bit 4,3 --unused
; bit 7 --REFS1 0 Two bits:
; bit 6 --REFS0 0 Select VCC volt reference
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
; bit 2 --MUX2 0 Three bits:
; bit 1 --MUX1 0
; bit 0 --MUX0 1 Select ADC1 from PB2
 
.SET admux_direction= 0b00100010 ; bit 4,3 --unused
; bit 7 --REFS1 0 Two bits:
; bit 6 --REFS0 0 Select VCC volt reference
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
; bit 2 --MUX2 0 Three bits:
; bit 1 --MUX1 1
; bit 0 --MUX0 0 Select ADC2 from PB3
 
.SET admux_momentum= 0b00100011 ; bit 4,3 --unused
; bit 7 --REFS1 0 Two bits:
; bit 6 --REFS0 0 Select VCC volt reference
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH
; bit 2 --MUX2 0 Three bits:
; bit 1 --MUX1 1
; bit 0 --MUX0 1 Select ADC3 from PB4
 
.SET admux_off= 0b00000000 ; bit 4,3 --unused
; bit 7 --REFS1 0 Two bits:
; bit 6 --REFS0 0 Select VCC volt reference
; bit 5 --ADLAR 0 right adjust
; bit 2 --MUX2 0 Three bits:
; bit 1 --MUX1 0
; bit 0 --MUX0 0 Select ADC0 from PB5
 
.SET adcsr_off= 0b00010011 ; bit 7 --ADCEN 0 ADC enable disable
; bit 6 --ADSC 0 Start conversion no
; bit 5 --ADFR 0 Free running mode disable
; bit 4 --ADIF 1 Interrupt flag clear
; bit 3 --ADIE 0 Interrupt enable disabled
; bit 2 --ADPS2 0 Three bits:
; bit 1 --ADPS1 1
; bit 0 --ADPS0 1 Prescaler div 8 (200kHz)
 
.SET adcsr_enable= 0b11110011 ; bit 7 --ADCEN 1 ADC enable ENABLED
; bit 6 --ADSC 1 Start conversion yes
; bit 5 --ADFR 1 Free running mode ENABLED
; bit 4 --ADIF 1 Interrupt flag clear
; bit 3 --ADIE 0 Interrupt enable disabled
; bit 2 --ADPS2 0 Three bits:
; bit 1 --ADPS1 1
; bit 0 --ADPS0 1 Prescaler div 8 (200kHz)
 
.SET mcucr_power_down_mode= 0b00110000
; bit 7 --unused
; bit 6 --PUD 0 pullups ENABLED
; bit 5 --SE 1 sleep ENABLED
; bit 4 --SM1 1 Two bits:
; bit 3 --SM0 0 Sleep in power down mode
; bit 2 --unused
; bit 1 --ISC01 0 Two bits:
; bit 0 --ISC00 0 INTO interrupt on logic
; low input
 
 
.SET wdtcr_off_enable= 0b00011000 ; enable watchdog turn off
.SET wdtcr_off= 0b00010000 ; watchdog turn off
 
.SET gimsk_val_off= 0b00000000 ; bit 7,4,3,2,1,0 --unused
; bit 6 --INTO 0 INTO interrupt disabled
; bit 5 --PCIE 0 pin change interrupt disabled
 
.SET gimsk_val_pcie= 0b00100000 ; bit 7,4,3,2,1,0 --unused
; bit 6 --INTO 0 INTO interrupt disabled
; bit 5 --PCIE 1 pin change interrupt ENABLED
.SET gifr_clear= 0b01100000 ; bit 7,4,3,2,1,0 --unused
; bit 6 --INTF0 1 INTO interrupt flag cleared
; bit 5 --PCIF 1 pin ch. interrupt flag cleared
.SET timsk_val_off= 0b00000000 ; bit 7,5,4,3,0 --unused
; bit 6 --OCIE1A 0 TC1 compare interrupt disabled
; bit 2 --TOIE1 0 TC1 overflow interrupt disabled
; bit 1 --TOIE0 0 TC0 overflow interrupt disabled
 
.SET timsk_enable_t1= 0b01000000 ; bit 7,5,4,3,0 --unused
; bit 6 --OCIE1A 0 TC1 compare interrupt disabled
; bit 2 --TOIE1 0 TC1 overflow interrupt disabled
; bit 1 --TOIE0 0 TC0 overflow interrupt disabled
 
.SET tifr_clear_tov0= 0b00000010 ; bit 7,5,4,3,0 --unused
; bit 6 --OCF1A 0 OCF1A flag not cleared
; bit 2 --TOV1 0 TOV1 flag not cleared
; bit 1 --TOV0 1 TOV0 flag CLEARED
 
.SET tccr1_enable_t1= 0b01100011
; bit 7 --CTC1 0 Clear on compare match no
; bit 6 --PWM1 1 PWM mode ENABLED
; bit 5 --COM1A1 1 Two bits:
; bit 4 --COM1A0 0 Clear output on OCR1A match
; Set output when TCNT1 = 0
; bit 3 --CS13 0 Four bits:
; bit 2 --CS12 0
; bit 3 --CS11 1
; bit 4 --CS10 1 CK*4: 156.25nS
; 256cnt = 25kHz
.LIST
/contrib/toolchain/avra/examples/throttle_divide.asm
0,0 → 1,135
;throttle_divide.asm
;
;********************************************************************************
;* div16u *
;* Second Level Subroutine *
;* *
;* Program from Atmel file avr200.asm *
;* *
;* Since the 25kHz pwm cycle is 64 clock cycles long, this subroutine *
;* requires 3.67 to 3.92 25kHz clock cycles. *
;* *
;* A single line was added which adds 3 to Cycle_count *
;* *
;* Inputs: HILOCAL2:HILOCAL1 and B_TEMPLOCAL1:B_TEMPLOCAL *
;* Returns: HILOCAL2:HILOCAL1 = HILOCAL2:HILOCAL1 / B_TEMPLOCAL1:B_TEMPLOCAL *
;* LOLOCAL2:LOLOCAL1 = remainder *
;* Changed: B_TEMPLOCAL2 *
;* *
;* Calls: Not allowed *
;********************************************************************************
 
 
B_TEMPLOCAL2 dcnt16u ; Local counter
 
HILOCAL1 dd16uL ; 16 bit Innput
HILOCAL2 dd16uH
 
B_TEMPLOCAL dv16uL ; 16 bit Input
B_TEMPLOCAL1 dv16uH
 
HILOCAL1 dres16uL ; 16 bit Output
HILOCAL2 dres16uH
 
LOWLOCAL1 drem16uL ; 16 bit Remainder
LOWLOCAL2 drem16uH ;
 
 
 
;<ATMEL ROUTINE>
;***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd16uH:dd16uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :19
;* Number of cycles :235/251 (Min/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH,
;* dcnt16u)
;*
;***************************************************************************
 
;***** Subroutine Register Variables
 
;.def drem16uL= r14 ; Reassigned
;.def drem16uH= r15
;.def dres16uL= r16
;.def dres16uH= r17
;.def dd16uL= r16
;.def dd16uH= r17
;.def dv16uL= r18
;.def dv16uH= r19
;.def dcnt16u= r20
 
;***** Code
 
div16u:
clr drem16uL ; clear remainder Low byte
sub drem16uH,drem16uH ; clear remainder High byte and carry
ldi dcnt16u,17 ; init loop counter
 
d16u_1:
rol dd16uL ; shift left dividend
rol dd16uH
dec dcnt16u ; decrement counter
brne d16u_2 ; if done
 
subi Cycle_count,256-3 ; Add 3 to Cycle_count
 
ret ; return
 
d16u_2:
rol drem16uL ; shift dividend into remainder
rol drem16uH
 
sub drem16uL,dv16uL ; remainder = remainder - divisor
sbc drem16uH,dv16uH ;
 
brcc d16u_3 ;
 
add drem16uL,dv16uL ; if result negative
adc drem16uH,dv16uH ; restore remainder
clc ; clear carry to be shifted into result
rjmp d16u_1 ;
 
d16u_3: ; if result NOT negative
sec ; set carry to be shifted into result
rjmp d16u_1
 
;<END ATMEL ROUTINE>
 
;********************************************************************************
;* DIVIDE_16_SIMPLE *
;* Second Level Subroutine *
;* *
;* Inputs: dd16uH:dd16ul and dv16uL *
;* Returns: dres16uH:dres16uL = dd8uH:dd8uL / 2^dv16uL *
;* *
;* Changed: nothing else *
;* N.B that dd16uH, dd16uL, dv16uH and dv16uL are aliases for: *
;* dd16uH=error_hi *
;* dd16uL=error_lo *
;* dv16uH=B_TempX *
;* dv16uL=B_TempX *
;* dcnt16u=B_TempX *
;* Calls: Not allowed *
;********************************************************************************
 
 
DIVIDE_16_SIMPLE:
inc dv16uL
DIVIDE_16_SIMPLE_LOOP:
dec dv16uL ; decrement counter
brne DIVIDE_BY_2
ret
 
DIVIDE_BY_2:
asr dd16uH ; divide by two
ror dd16uL
rjmp DIVIDE_16_SIMPLE_LOOP
/contrib/toolchain/avra/examples/throttle_momentum.asm
0,0 → 1,314
;throttle_momentum.asm
 
.NOLIST
 
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************:
.LIST
 
.ifdef MOMENTUM_ENABLED
;********************************************************************************
;* MOMENTUM_ADJUST *
;* Top level routine *
;* *
;* Momentum simulates the mass of the train. Since model trains have little *
;* mass, the locomotive speed can directly follow the throttle setting; in *
;* other words, a model train can accelerate and decelerate instantly. *
;* Real trains are very massive, and therefore they do not accelerate or *
;* decelerate quickly. *
;* *
;* According to Newtons law, the acceleration is proportional to the force, *
;* and inversely proportional to the mass. Therefore, the more massive the *
;* train, the more slowly the train will accelerate or decelerate. Also, the *
;* more force the locomotive can provide, the faster the train will accelerate. *
;* Deceler depends on the braking capability of the overall train. *
;* *
;* If force were constant, Newtons law states that acceleration would be *
;* constant too. This subroutine assumes that somewhat more force is *
;* available at low speeds than at high speeds, so that acceleration will be *
;* greater at low speeds. The subroutine also assumes that opposing forces *
;* (friction, wind resistance, etc) are stronger at higher speeds. This *
;* assumption also means that acceleration will be greater at low speeds. *
;* *
;* This subroutine calculates acceleration/deceleration by this simple *
;* Method: *
;* *
;* The rate of speed change (accleration and deceleration) depends on the *
;* current speed as *
;* {Speed_Max (0xFF) - Current_Speed} / {Tau*Rate} *
;* *
;* Where T = index of sample time *
;* t = real time *
;* Tau = time constant *
;* Rate = Update rate (nominally 100Hz) *
;* *
;* That is, the acceleration/deceleration is maximum at zero speed, and *
;* approaches zero at maximum speed. *
;* *
;* When accelerating, the speed at the next sample period is *
;* Speed(T) = Speed(T-1) + {0xFF - Speed(T-1)} / {Tau*Rate} *
;* *
;* Giving an acceleration curve that looks like a normal exponential. *
;* Speed(t) = 0xFF { 1 - exp( - t / Tau) } *
;* *
;* * * *
;* * *
;* * *
;* * *
;* * *
;* * *
;* * *
;* * *
;* *
;* *
;* When decelerating, the change rate equation is the same, but the change *
;* is subtracted, as *
;* Speed(T) = Speed(T) - {0xFF - Speed(T-1)} / {Tau*Rate} *
;* *
;* Giving a deceleration curve that looks like *
;* Speed(t) = 0xFF { 1 - exp( -(T1 - t) / Tau) } *
;* which is a mirror image of the acceleration, NOT a normal exponential. *
;* *
;* * * *
;* * *
;* * *
;* * *
;* * *
;* * *
;* * *
;* *
;* *
;* In each case, the acceleration or deceleration is "clipped" at the current *
;* throttle setting so that the speed doesn't overshoot or undershoot. *
;* *
;* Three different values of Tau are used, that is *
;* Tau_accel Corresponding to acceleration under power *
;* Tau_coast Corresponding to deceleration when coasting *
;* Tau_brake Corresponding to deceleration when braking *
;* *
;* To permit finer control of momentum, the throttle setting is converted to a *
;* 16 bit number, where the 8 msb's correspond to the throttle setting from *
;* the throttle handle and sent forward. *
;* *
;* Inputs: throttle_set Throttle handle position ( 0x00 to 0xFF ) *
;* speed_hi_prev Hi byte of (T-1) throttle setting (stored) *
;* speed_lo_prev Lo byte of (T-1) throttle setting (stored) *
;* Returns: throttle_set Adjusted throttle setting (T) *
;* speed_hi_prev Hi byte of (T) throttle setting (stored) *
;* speed_lo_prev Lo byte of (T) throttle setting (stored) *
;* Changed: B_Temp *
;* B_Temp1 *
;* B_Temp2 *
;* B_Temp3 *
;* Calls: NONE *
;* Goto: MOMENTUM_ADJUST_RETURN *
;********************************************************************************
B_TEMPLOCAL2 _time_constant_adj
 
 
.ifdef TRADITIONAL_ENABLED
.ifdef LEDS_ENABLED
sbrc Flags_1,BF_brake ; If the brake flag is set,
sbi PORTB,dir_in_port ; Port Output: Indicate deceleration
.endif ;LEDS_ENABLED
.endif ;TRADITIONAL_ENABLED
 
;*******************************************************************
;* Adjust the value of "momentum_set".
;* This adjustment makes it easier to fine adjust low momentum settings
;* while still permitting large momentum settings.
;*
;* The ammount of momentum to apply comes in in "momentum_set"
;* which is read in READ_THROTTLE. The nominal range is
;* 0x00 to 0x40. This value is multiplied by two and squared,
;* giving a new range from 0x00 to 0x4000. The update rate is 100Hz,
;* and so the new range corresponds to a time constant from
;* 0(decimal) to 164(decimal) seconds. Since the adjustment was
;* done by performing a square, the adjusted value is non-linear
;* with the input value.
;*******************************************************************
lsl momentum_set ; multiply by two
 
HILOCAL1 _mset_multiplier ; supply to mpy8u
B_TEMPLOCAL _mset_multiplicand ; supply to mpy8u
 
mov _mset_multiplier,momentum_set ;
mov _mset_multiplicand,momentum_set ;
rcall mpy8u ; square
 
B_TEMPLOCAL1 _mset_hi_byte ; return from mpy8u
B_TEMPLOCAL _mset_lo_byte ; return from mpy8u
 
;*******************************************************************
;* Compute the difference between the maximum throttle and
;* the current throttle
;*******************************************************************
HILOCAL2 _mset_diff_hi_byte
HILOCAL1 _mset_diff_lo_byte
 
ldi _mset_diff_hi_byte,0xFF ; Maximum possible speed
ldi _mset_diff_lo_byte,0xFF ;
 
sub _mset_diff_lo_byte,speed_lo_prev ; Difference between max speed
sbc _mset_diff_hi_byte,speed_hi_prev ; and current speed
 
;*******************************************************************
;* Determine whether to accelerate, decelerate, or remain unchanged.
;* Compare the throttle handle setting with the actual speed
;*******************************************************************
cp throttle_set,speed_hi_prev ; Test if throttle position is larger
; or smaller than the speed.
 
breq EVEN_SPEED ; If the throttle position is the same
; as the speed.
brlo SETUP_DECELERATE ; If the throttle position is smaller
; than the speed, then need to decelerate.
 
; brsh SETUP_ACCELERATE ; If the throttle position is larger
; than the speed, then need to accelerate.
 
SETUP_ACCELERATE:
.ifdef TRADITIONAL_ENABLED
.ifdef LEDS_ENABLED
cpi throttle_set,accel_led_threshold ; If the throttle is less than minimum
brlo END_SET_ACCEL_LED ; don't light led
 
mov B_Temp2,throttle_set ; If the throttle is closer than led_threshold
subi B_Temp2,accel_led_threshold ; don't light led
cp B_Temp2,speed_hi_prev
brlo END_SET_ACCEL_LED
 
sbi PORTB,momentum_port ; Port Output: Indicate acceleration
END_SET_ACCEL_LED:
.endif LEDS_ENABLED
.endif TRADITIONAL_ENABLED
 
sbr Flags_1,F_accel ; Set accelerating flag
; Indicate acceleration
 
ldi _time_constant_adj,accel_offset+1 ; Acceleration time constant adjust
 
rjmp CHECK_BRAKE
 
EVEN_SPEED: ; Arrive here if throttle_set=current speed
 
sbrc Flags_1,BF_brake ; If the brake flag is set, decelerate
rjmp CHECK_BRAKE ;
rjmp DONE_WITH_MOMENTUM ; Otherwise adjustment is necessary
 
 
SETUP_DECELERATE:
cbr Flags_1,F_accel ; Clear accelerating flag
 
.ifdef TRADITIONAL_ENABLED
.ifdef LEDS_ENABLED
 
cpi throttle_set,0xff-decel_led_threshold ; If the throttle is more than maximum
brsh END_SET_DECEL_LED ; don't light led
 
mov B_Temp2,throttle_set
subi B_Temp2,0x00-decel_led_threshold ; If the throttle is closer than the led
cp B_Temp2,speed_hi_prev ; threshold, don't light the led
brsh END_SET_DECEL_LED
 
sbi PORTB,dir_in_port ; Port Output: Indicate deceleration
END_SET_DECEL_LED:
.endif LEDS_ENABLED
.endif TRADITIONAL_ENABLED
 
ldi _time_constant_adj,0+1 ; Coasting deceleration time const. adjust.
; rjmp CHECK_BRAKE
 
CHECK_BRAKE: ; Always check for the brake.
 
sbrs Flags_1,BF_brake ; If brake flag is not set,
rjmp ADJUST_TAU ; proceed.
 
; Brake overrides acceleration
; or coasting.
cbr Flags_1,F_accel ; clear accelerating flag
; Indicate deceleration
 
ldi _time_constant_adj,brake_offset+1 ; Braking deceleration time const. adjust.
 
; rjmp ADJUST_TAU
 
ADJUST_TAU:
;B_TEMP2=B_TEMPLOCAL2
dec _time_constant_adj ; Divide tau_base by 2^_time_constant_adj
breq DIVIDE_TAU ; to produce adjusted tau.
 
lsr _mset_hi_byte
ror _mset_lo_byte
rjmp ADJUST_TAU
 
DIVIDE_TAU:
sbr _mset_lo_byte,0b00000001 ; Force last bit 1. Prevent divide by zero.
 
rcall div16u ; Divide _mset_diff_hi_byte:_mset_diff_lo_byte
; (difference)
; by _mset_hi_byte:_mset_lo_byte (dividor)
 
sbrs Flags_1,BF_accel ; add or subtract change depending
rjmp SUBTRACT_CHANGE ; on F_accel flag
;rjmp ADD_CHANGE
 
ADD_CHANGE: ; Case accelerating
 
; HILOCAL2 _mset_diff_hi_byte
; HILOCAL1 _mset_diff_lo_byte
 
add speed_lo_prev,_mset_diff_lo_byte ; Add in the change
adc speed_hi_prev,_mset_diff_hi_byte
 
cp throttle_set,speed_hi_prev ; If larger than the throttle_set value
brlo USE_SET_SPEED ; clamp at throttle_set value
 
rjmp DONE_WITH_MOMENTUM
 
SUBTRACT_CHANGE: ; Case decelerating
 
sbrc Flags_1,BF_brake ; If the brake flag is set,
clr throttle_set ; decelerate all the way to zero
 
sub speed_lo_prev,_mset_diff_lo_byte ; Subtract the change
sbc speed_hi_prev,_mset_diff_hi_byte ;
 
brlo USE_SET_SPEED ; If less than zero
; clamp at throttle_set value
 
cp speed_hi_prev,throttle_set ; If less than the throttle_set value
brlo USE_SET_SPEED ; clamp at throttle_set value
 
rjmp DONE_WITH_MOMENTUM
 
USE_SET_SPEED: ; Use the throttle_set value directly
mov speed_hi_prev,throttle_set
clr speed_lo_prev
 
DONE_WITH_MOMENTUM:
mov throttle_set,speed_hi_prev ; Put the new value into throttle_set.
 
.endif ;MOMENTUM_ENABLED
/contrib/toolchain/avra/examples/throttle_momentum_lowpass.asm
0,0 → 1,69
;throttle_momentum_lowpass.asm
 
.NOLIST
 
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
.LIST
 
.ifdef MOMENTUM_LOWPASS_ENABLED
;*****************************************************************
;* A transversal low pass filter *
;* *
;* This is copied from throttle_backemf.asm. *
;* See the documentation there. *
;*****************************************************************
HILOCAL1 _momentum_lo ; assign local variables
HILOCAL2 _momentum_hi
 
mov _momentum_lo,momentum_set
clr _momentum_hi
 
;****
;* 1. Add in cumulative previous throttle
;****
add _momentum_lo,momentum_lo_prev ; Add in scaled previous samples
adc _momentum_hi,momentum_hi_prev ;
 
;****
;* 2.
;****
mov momentum_lo_prev,_momentum_lo ; Store new value
mov momentum_hi_prev,_momentum_hi ; Store new value
 
;****
;* 3.
;****
 
B_TEMPLOCAL _lowpass_lo_byte
ldi _lowpass_lo_byte, momentum_lowpass_gain
rcall DIVIDE_16_SIMPLE
 
;****
;* 4.
;****
sub momentum_lo_prev,_momentum_lo
sbc momentum_hi_prev,_momentum_hi
 
mov momentum_set,_momentum_lo
.endif ;MOMENTUM_LOWPASS_ENABLED
/contrib/toolchain/avra/examples/throttle_multiply.asm
0,0 → 1,74
;throttle_multiply.asm
;
;********************************************************************************
;* mpy8u *
;* Second Level Subroutine *
;* *
;* Program from Atmel file avr200.asm *
;* *
;* Since the 25kHz pwm cycle is 64 clock cycles long, this subroutine *
;* requires just under 1 25kHz clock cycles. *
;* *
;* A single line was added which adds 3 to Cycle_count *
;* *
;* Inputs: HILOCAL1 and B_TEMPLOCAL *
;* *
;* Returns: HILOCAL1 x B_TEMPLOCAL = B_TEMPLOCAL1:B_TEMPLOCAL *
;* *
;* Changed: B_TEMPLOCAL2 *
;* *
;* Calls: Not allowed *
;********************************************************************************
 
HILOCAL1 mc8u ; multiplicand
B_TEMPLOCAL mp8u ; multiplier
B_TEMPLOCAL m8uL ; result Low byte
B_TEMPLOCAL1 m8uH ; result High byte
B_TEMPLOCAL2 mcnt8u ; loop counter
 
 
;<ATMEL ROUTINE>
;***************************************************************************
;*
;* "mpy8u" - 8x8 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two register variables mp8u and mc8u.
;* The result is placed in registers m8uH, m8uL
;*
;* Number of words :9 + return
;* Number of cycles :58 + return
;* Low registers used :None
;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u)
;*
;* Note: Result Low byte and the multiplier share the same register.
;* This causes the multiplier to be overwritten by the result.
;*
;***************************************************************************
 
;***** Subroutine Register Variables
 
;.def mc8u =r16 ;multiplicand
;.def mp8u =r17 ;multiplier
;.def m8uL =r17 ;result Low byte
;.def m8uH =r18 ;result High byte
;.def mcnt8u =r19 ;loop counter
 
;***** Code
 
 
mpy8u:
clr m8uH ;clear result High byte
ldi mcnt8u,8 ;init loop counter
lsr mp8u ;rotate multiplier
m8u_1:
brcc m8u_2 ;carry set
add m8uH,mc8u ;add multiplicand to result High byte
m8u_2:
ror m8uH ;rotate right result High byte
ror m8uL ;rotate right result L byte and multiplier
dec mcnt8u ;decrement loop counter
brne m8u_1 ;if not done, loop more
ret
 
;<END ATMEL ROUTINE>
/contrib/toolchain/avra/examples/throttle_op_set.inc
0,0 → 1,227
;throttle_op_set.inc
 
.NOLIST
 
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
 
;*********************************************************
;* Operation Settings *
;*********************************************************
 
 
 
;*********************************************************
;* Compile time options
;*********************************************************
.define TRADITIONAL_ENABLED ; A traditional throttle. NOT
; a dcc decoder
 
.define WALKAROUND_ENABLED ; Removable, walkaround throttle
; (Does nothing unless the
; TRADITIONAL_ENABLED is also defined)
 
.define THROTTLE_LOWPASS_ENABLED ; Lowpass filter on throttle handle
; (Does nothing unless the
; TRADITIONAL_ENABLED is also defined)
 
.define MOMENTUM_LOWPASS_ENABLED ; Lowpass filter on momentum handle
; (Does nothing unless the
; TRADITIONAL_ENABLED and
; MOMENTUM_ENABLED are defined)
 
.define SWITCH_LOWPASS_ENABLED ; Lowpass filter on direction switches
 
.define LEDS_ENABLED ; Acceleration/Deceleration indicators
; (Does nothing unless the
; TRADITIONAL_ENABLED is also defined)
 
.define LOCO_LIGHT_ENABLED ; Keep pwm on at low level so light
; remains on.
; (Does nothing unless the
; TRADITIONAL_ENABLED is also defined)
 
.define BACKEMF_ENABLED ; If enabled, speed is compensated
; according to motor back emf
 
.define BACKEMF_SCALE_ENABLED ; If enabled, the speed compensation
; is reduced as the throttle setting
; is increased.
; (Does nothing unless the
; BACKEMF_ENABLED is also defined)
 
 
.define LOWPASS_ENABLED ; Provide a lowpass filter on the
; the back-emf error amplifier
; (Does nothing unless the
; BACKEMF_ENABLED is also defined)
 
.define OVERLOAD_ENABLED ; Enable overload protection
 
.define PULSE_ENABLED ; Pulse power at low throttle
 
;.define PULSE_AMPLITUDE_SCALE ; Increase pulse size at lowest throttle
; (Does nothing unless the
; PULSE_ENABLED is also defined)
 
.define PULSE_WIDTH_SCALE ; Increase pulse width at higher throttle
; (Does nothing unless the
; PULSE_ENABLED is also defined)
 
.define MOMENTUM_ENABLED ; Simulate momentum
 
.define DIRECTION_ENABLED ; Direction/brake/STOP input
;*********************************************************
 
;*********************************************************
;* Variables for all compilations
;*********************************************************
 
;*******************
;* High frequency pwm settings
;*******************
.SET pwm_period= 0xFF ; The pwm clock ticks at 156.25nS per tick
; The pwm runs at pwm_period * 156.25nS
; The pwm frequency is 1/ (156.25nS * pwm_period)
; Maximum is 255 (0xFF)
 
.SET pwm_max= 0xFF ; Maximum pwm "duty cycle" is equal to
; pwm_max / pwm_period
 
.SET pwm_min= 0x08 ; Minimum PWM "duty cycle" is equal to
; pwm_min / pwm_period
 
;*******************
;* Sample rate for throttle/ backemf/ pulses, etc
;*******************
.SET pwm_settle_count= 16 ; settling time for analog measurements
; (x 40uS)
.SET pwm_full_count= 250 ; time (x 40uS) between recalculations
; (255 max)
 
;*********************************************************
;* Variables associated with backemf speed control
;*********************************************************
.ifdef BACKEMF_ENABLED
 
;*******************
;* General settings
;*******************
 
.SET error_mult= 2 ; Error Multiplier. The error between
; the throttle_set and back_emf is
; multiplied by 2^error_mult
; limit -8 < n < 7
; 1/256 to 128
 
.ifdef BACKEMF_SCALE_ENABLED
.SET err_scale= 5 ; Maximum error gain is as set by error_mult.
; Error gain decreases exponentially toward
; zero. When the throttle is set at 2^err_scale
; the error be reduced by 2
; Err scale must not be less than 0.
; The sum of err_scale and err_mult MUST NOT
; exceed 7.
.endif ;BACKEMF_SCALE_ENABLED
 
.ifdef LOWPASS_ENABLED
 
.SET emf_lowpass_gain= 2 ; tau is about 2^emf_lowpass_gain / 100
; emf_lowpass_gain 0 to 8 (7?)
.endif ;LOWPASS_ENABLED
 
.endif ;BACKEMF_ENABLED
 
;*********************************************************
;* Variables associated with lowspeed pulses
;*********************************************************
.ifdef PULSE_ENABLED
.SET pwm_min= 0x00 ; override previous setting
.SET pulse_slope_up= 0x0C
.SET pulse_slope_down= 0x08
.SET pulse_width_min= 0x08 ; minimum 0x01
.endif ; PULSE_ENABLED
 
;*********************************************************
;* Variables associated with momentum
;*********************************************************
.ifdef MOMENTUM_ENABLED
; MAY NOT BE MORE THAN 7
 
.SET accel_offset=1 ; divide tau_base by 2^accel_offset to give
; acceleration time constant
.SET brake_offset=2 ; divide tau_base by 2^brake_offset to give
; brake time constant
 
 
.endif MOMENTUM_ENABLED
 
 
;*********************************************************
;* Variables associated with direction
;*********************************************************
.ifdef DIRECTION_ENABLED
 
.SET direction_threshold= 16 ; direction relay will switch as long as
; the throttle (handle and momentum) are
; less than this value
.endif ;DIRECTION_ENABLED
 
;*********************************************************
;* Variables associated with traditional throttle
;*********************************************************
.ifdef TRADITIONAL_ENABLED
 
 
.ifdef SWITCH_LOWPASS_ENABLED
.SET stop_count_max= 10 ; number of identical samples to indicate
.SET brake_count_max= 10 ; number of identical samples to indicate
.SET reverse_count_max= 10 ; number of identical samples to indicate
.SET foreward_count_max= 10 ; number of identical samples to indicate
.endif ;SWITCH_LOWPASS_ENABLED
 
.ifdef THROTTLE_LOWPASS_ENABLED
.SET throttle_lowpass_gain= 5 ; tau is about 2^throttle_lowpass_gain / 100
; throttle_lowpass_gain range 0 to 8 (7?)
.endif ;THROTTLE_LOWPASS_ENABLED
 
.ifdef MOMENTUM_LOWPASS_ENABLED
.SET momentum_lowpass_gain= 7 ; tau is about 2^momentum_lowpass_gain / 100
; momentum_lowpass_gain range 0 to 8 (7?)
.endif ;MOMENTUM_LOWPASS_ENABLED
 
.ifdef LEDS_ENABLED
 
.SET accel_led_threshold=2 ; dont light led when acceleration/deceleration
; is closer than this to the actual speed
.SET decel_led_threshold=2 ; dont light led when acceleration/deceleration
; is closer than this to the actual speed
.endif;LEDS_ENABLED
 
.ifdef LOCO_LIGHT_ENABLED
.SET light_pwm= 6 ; run this pwm "duty cycle when throttle is off
.endif ;LOCO_LIGHT_ENABLED ; to keep loco light on
.endif ;TRADITIONAL_ENABLED
 
.LIST
/contrib/toolchain/avra/examples/throttle_pulse.asm
0,0 → 1,140
;throttle_pulse.asm
 
.NOLIST
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
.LIST
 
.ifdef PULSE_ENABLED
;********************************************************************************
;* PULSE_GENERATE *
;* Top level routine *
;* *
;* Inputs: throttle_set *
;* Returns: none *
;* Changed: B_Temp,ramp_target,ramp_target1 *
;* Calls: SET_PWM_DUTY *
;* COUNT_PWM_CYCLES *
;* Goto: none *
;********************************************************************************
 
HILOCAL1 ramp_target
HILOCAL2 ramp_target1
 
;*****************************************************************
;* If throttle_set is less than 128 (0x80)
;* Ramp up from wherever the pwm is up to (255 - throttle)
;* If throttle_set is greater than 127 0x7F)
;* Ramp up to throttle_set
;*****************************************************************
 
mov ramp_target1,throttle_set
sbrs ramp_target1,7
 
.ifdef PULSE_AMPLITUDE_SCALE
com ramp_target1 ; Ramp up to this value
.else
ldi ramp_target1,0x80
.endif
 
mov ramp_target,ramp_target1
 
subi ramp_target,pulse_slope_up ; Ramp up value - pulse_slope
 
WAIT_FOR_PWM_1: ; Wait for PWM to reset to 0
in B_Temp,TIFR
sbrs B_Temp,OCF1A
rjmp WAIT_FOR_PWM_1
ldi B_Temp,0b01000000
out TIFR,B_Temp
 
inc Cycle_count
 
in B_Temp,OCR1A ; Find PWM value
cp B_Temp,ramp_target ; Make sure won't go past max.
brsh DONE_SLOPING_UP
 
subi B_Temp, 0x100-pulse_slope_up ; OCR1A + pulse_slope_up
 
rcall SET_PWM_DUTY
rjmp WAIT_FOR_PWM_1
 
DONE_SLOPING_UP:
mov B_Temp,ramp_target1
rcall SET_PWM_DUTY
 
;*****************************************************************
;* See if we need to slope down to the throttle setting
;*****************************************************************
in B_Temp,OCR1A ; Find PWM value
cp B_Temp,throttle_set
breq PULSE_GENERATE_RETURN ; Do nothing if already at final voltage
 
;*****************************************************************
;* Hang about at the top of the pulse for a while...
;*****************************************************************
 
.ifdef PULSE_WIDTH_SCALE
mov ramp_target1,throttle_set
.else
clr ramp_target1
.endif
 
add ramp_target1,Cycle_count
 
subi ramp_target1,0x100-pulse_width_min ; ramp_target1 + pulse_width_min
 
mov B_Temp1,ramp_target1
 
rcall COUNT_PWM_CYCLES
 
;*****************************************************************
;* Slope down
;*****************************************************************
 
mov ramp_target,throttle_set ; Ramp DOWN to this value
 
subi ramp_target,0x100-pulse_slope_down ;ramp_target + pulse_slope_down
 
WAIT_FOR_PWM_2: ; Wait for PWM to reset to 0
in B_Temp,TIFR
sbrs B_Temp,OCF1A
rjmp WAIT_FOR_PWM_2
ldi B_Temp,0b01000000
out TIFR,B_Temp
 
inc Cycle_count
 
in B_Temp,OCR1A ; Find PWM value
cp ramp_target,B_Temp ; Make sure won't go past min
brsh PULSE_GENERATE_RETURN
 
subi B_Temp,pulse_slope_down
 
rcall SET_PWM_DUTY
rjmp WAIT_FOR_PWM_2
 
PULSE_GENERATE_RETURN:
.endif ;PULSE_ENABLED
/contrib/toolchain/avra/examples/throttle_set_lowpass.asm
0,0 → 1,69
;throttle_set_lowpass.asm
 
.NOLIST
 
; ***************************************************************************************
; * PWM MODEL RAILROAD THROTTLE *
; * *
; * WRITTEN BY: PHILIP DEVRIES *
; * *
; * Copyright (C) 2003 Philip DeVries *
; * *
; * This program is free software; you can redistribute it and/or modify *
; * it under the terms of the GNU General Public License as published by *
; * the Free Software Foundation; either version 2 of the License, or *
; * (at your option) any later version. *
; * *
; * This program is distributed in the hope that it will be useful, *
; * but WITHOUT ANY WARRANTY; without even the implied warranty of *
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
; * GNU General Public License for more details. *
; * *
; * You should have received a copy of the GNU General Public License *
; * along with this program; if not, write to the Free Software *
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA *
; * *
; ***************************************************************************************
.LIST
 
.ifdef THROTTLE_LOWPASS_ENABLED
;*****************************************************************
;* A transversal low pass filter *
;* *
;* This is copied from throttle_backemf.asm. *
;* See the documentation there. *
;*****************************************************************
HILOCAL1 throttle_lo ; assign local variables
HILOCAL2 throttle_hi
 
mov throttle_lo,throttle_set
clr throttle_hi
 
;****
;* 1. Add in cumulative previous throttle
;****
add throttle_lo,throttle_lo_prev ; Add in scaled previous samples
adc throttle_hi,throttle_hi_prev ;
 
;****
;* 2.
;****
mov throttle_lo_prev,throttle_lo ; Store new value
mov throttle_hi_prev,throttle_hi ; Store new value
 
;****
;* 3.
;****
 
B_TEMPLOCAL _lowpass_lo_byte
ldi _lowpass_lo_byte, throttle_lowpass_gain
rcall DIVIDE_16_SIMPLE
 
;****
;* 4.
;****
sub throttle_lo_prev,throttle_lo
sbc throttle_hi_prev,throttle_hi
 
mov throttle_set,throttle_lo
.endif ;THROTTLE_LOWPASS_FILTER
/contrib/toolchain/avra/examples/tn15def.inc
0,0 → 1,195
.NOLIST
 
;***************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number :AVR000
;* File Name :"tn15def.inc"
;* Title :Register/Bit Definitions for the ATtiny15
;* Date :99.07.05
;* Version :1.00
;* Support telephone :+47 72 88 87 20 (ATMEL Norway)
;* Support fax :+47 72 88 87 18 (ATMEL Norway)
;* Support E-mail :avr@atmel.com
;* Target MCU :ATtiny15
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;***************************************************************************
 
;***** Specify Device
.device ATtiny15
 
;***** I/O Register Definitions
.equ SREG =$3f
.equ GIMSK =$3b
.equ GIFR =$3a
.equ TIMSK =$39
.equ TIFR =$38
.equ MCUCR =$35
.equ MCUSR =$34
.equ TCCR0 =$33
.equ TCNT0 =$32
.equ OSCCAL =$31
.equ TCCR1 =$30
.equ TCNT1 =$2f
.equ OCR1A =$2e
.equ OCR1B =$2d
.equ SFIOR =$2c
.equ WDTCR =$21
.equ EEAR =$1e
.equ EEDR =$1d
.equ EECR =$1c
.equ PORTB =$18
.equ DDRB =$17
.equ PINB =$16
.equ ACSR =$08
.equ ADMUX =$07
.equ ADCSR =$06
.equ ADCH =$05
.equ ADCL =$04
 
 
;***** Bit Definitions
.equ INT0 =6
.equ PCIE =5
 
.equ INTF0 =6
.equ PCIF =5
 
.equ OCIE1 =6
.equ TOIE1 =2
.equ TOIE0 =1
 
.equ OCF1A =6
.equ TOV1 =2
.equ TOV0 =1
 
.equ PUD =6
.equ SE =5
.equ SM =4
.equ SM1 =4
.equ SM0 =3
.equ ISC01 =1
.equ ISC00 =0
 
.equ WDRF =3
.equ BORF =2
.equ EXTRF =1
.equ PORF =0
 
.equ CS02 =2
.equ CS01 =1
.equ CS00 =0
 
.equ CAL7 =7
.equ CAL6 =6
.equ CAL5 =5
.equ CAL4 =4
.equ CAL3 =3
.equ CAL2 =2
.equ CAL1 =1
.equ CAL0 =0
 
.equ CTC1 =7
.equ PWM1 =6
.equ COM11 =5
.equ COM10 =4
.equ CS13 =3
.equ CS12 =2
.equ CS11 =1
.equ CS10 =0
 
.equ FOCM =2
.equ PSR1 =1
.equ PSR0 =0
 
.equ WDTOE =4
.equ WDE =3
.equ WDP2 =2
.equ WDP1 =1
.equ WDP0 =0
 
.equ EERIE =3
.equ EEMWE =2
.equ EEWE =1
.equ EERE =0
 
.equ PB4 =4
.equ PB3 =3
.equ PB2 =2
.equ PB1 =1
.equ PB0 =0
 
.equ DDB5 =5
.equ DDB4 =4
.equ DDB3 =3
.equ DDB2 =2
.equ DDB1 =1
.equ DDB0 =0
 
.equ PINB5 =5
.equ PINB4 =4
.equ PINB3 =3
.equ PINB2 =2
.equ PINB1 =1
.equ PINB0 =0
 
.equ ACD =7
.equ ACO =5
.equ ACI =4
.equ ACIE =3
.equ ACIS1 =1
.equ ACIS0 =0
 
.equ REFS1 =7
.equ REFS0 =6
.equ ADLAR =5
.equ MUX2 =2
.equ MUX1 =1
.equ MUX0 =0
 
.equ ADEN =7
.equ ADSC =6
.equ ADFR =5
.equ ADIF =4
.equ ADIE =3
.equ ADPS2 =2
.equ ADPS1 =1
.equ ADPS0 =0
 
.def ZL =r30
.def ZH =r31
 
.equ INT0addr=$001 ;External Interrupt0 Vector Address
.equ PCINTaddr=$002 ;Pin change Interrupt Vector Address
.equ T1COMPaddr=$003 ;Timer1 Compare match interrupt vector address
.equ OVF1addr=$004 ;Overflow 1 Interrupt Vector Address
.equ OVF0addr=$005 ;Overflow 1 Interrupt Vector Address
.equ EERDYaddr =$006 ;EEPROM Interrupt Vector Address
.equ ACIaddr =$007 ;Analog Comparator Interrupt Vector Address
.equ ADCCaddr =$008 ;ADC Interrupt Vector Address
 
.LIST
/contrib/toolchain/avra/includes/1200def.inc
0,0 → 1,297
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S1200.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "1200def.inc"
;* Title : Register/Bit Definitions for the AT90S1200
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S1200
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _1200DEF_INC_
#define _1200DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S1200
#pragma AVRPART ADMIN PART_NAME AT90S1200
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x90
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V0
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ GIMSK = 0x3b
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ ACSR = 0x08
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Data Register, Port D
.equ PORTD0 = 0 ;
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ;
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ;
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ;
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ;
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ;
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ;
.equ PD6 = 6 ; For compatibility
 
; DDRD
.equ DDD0 = 0 ;
.equ DDD1 = 1 ;
.equ DDD2 = 2 ;
.equ DDD3 = 3 ;
.equ DDD4 = 4 ;
.equ DDD5 = 5 ;
.equ DDD6 = 6 ;
 
; PIND - Input Pins, Port D
.equ PIND0 = 0 ;
.equ PIND1 = 1 ;
.equ PIND2 = 2 ;
.equ PIND3 = 3 ;
.equ PIND4 = 4 ;
.equ PIND5 = 5 ;
.equ PIND6 = 6 ;
 
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x01ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_SIZE = 0
.equ RAMEND = 0x0000
.equ XRAMEND = 0x0000
.equ E2END = 0x003f
.equ EEPROMEND = 0x003f
.equ EEADRBITS = 6
#pragma AVRPART MEMORY PROG_FLASH 1024
#pragma AVRPART MEMORY EEPROM 64
#pragma AVRPART MEMORY INT_SRAM SIZE 0
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow
.equ ACIaddr = 0x0003 ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 4 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _1200DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/2313def.inc
0,0 → 1,406
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2313.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "2313def.inc"
;* Title : Register/Bit Definitions for the AT90S2313
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S2313
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _2313DEF_INC_
#define _2313DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S2313
#pragma AVRPART ADMIN PART_NAME AT90S2313
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x91
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ ICR1H = 0x25
.equ ICR1L = 0x24
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ ICF1 = 3 ; Input Capture Flag 1
.equ OCF1A = 6 ; Output Compare Flag 1A
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select bit 0
.equ CS11 = 1 ; Clock Select 1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; SPL - Stack Pointer Low
.equ SP0 = 0 ; Stack pointer bit 0
.equ SP1 = 1 ; Stack pointer bit 1
.equ SP2 = 2 ; Stack pointer bit 2
.equ SP3 = 3 ; Stack pointer bit 3
.equ SP4 = 4
.equ SP5 = 5 ; Stack pointer bit 5
.equ SP6 = 6 ; Stack pointer bit 6
.equ SP7 = 7 ; Stack pointer bit 7
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
 
 
; ***** PORTD ************************
; PORTD - Data Register, Port D
.equ PORTD0 = 0 ;
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ;
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ;
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ;
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ;
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ;
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ;
.equ PD6 = 6 ; For compatibility
 
; DDRD
.equ DDD0 = 0 ;
.equ DDD1 = 1 ;
.equ DDD2 = 2 ;
.equ DDD3 = 3 ;
.equ DDD4 = 4 ;
.equ DDD5 = 5 ;
.equ DDD6 = 6 ;
 
; PIND - Input Pins, Port D
.equ PIND0 = 0 ;
.equ PIND1 = 1 ;
.equ PIND2 = 2 ;
.equ PIND3 = 3 ;
.equ PIND4 = 4 ;
.equ PIND5 = 5 ;
.equ PIND6 = 6 ;
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEARL = EEAR ; For compatibility
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x03ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 128
.equ RAMEND = 0x00df
.equ XRAMEND = 0x0000
.equ E2END = 0x007f
.equ EEPROMEND = 0x007f
.equ EEADRBITS = 7
#pragma AVRPART MEMORY PROG_FLASH 2048
#pragma AVRPART MEMORY EEPROM 128
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt Request 0
.equ INT1addr = 0x0002 ; External Interrupt Request 1
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
.equ URXCaddr = 0x0007 ; UART, Rx Complete
.equ UDREaddr = 0x0008 ; UART Data Register Empty
.equ UTXCaddr = 0x0009 ; UART, Tx Complete
.equ ACIaddr = 0x000a ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 11 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _2313DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/2323def.inc
0,0 → 1,248
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2323.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "2323def.inc"
;* Title : Register/Bit Definitions for the AT90S2323
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S2323
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _2323DEF_INC_
#define _2323DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S2323
#pragma AVRPART ADMIN PART_NAME AT90S2323
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x91
.equ SIGNATURE_002 = 0x02
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; SPL - Stack Pointer Low
.equ SP0 = 0 ; Stack pointer bit 0
.equ SP1 = 1 ; Stack pointer bit 1
.equ SP2 = 2 ; Stack pointer bit 2
.equ SP3 = 3 ; Stack pointer bit 3
.equ SP4 = 4
.equ SP5 = 5 ; Stack pointer bit 5
.equ SP6 = 6 ; Stack pointer bit 6
.equ SP7 = 7 ; Stack pointer bit 7
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
 
; MCUSR -
.equ PORF = 0 ; Power On Reset Flag
.equ EXTRF = 1 ; Externl Reset Flag
 
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
 
; GIFR - General Interrupt Flag Register
.equ INTF0 = 6 ; External Interrupt Flag 0
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** PORTB ************************
; PORTB - Data Register, Port B
.equ PORTB0 = 0 ;
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ;
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ;
.equ PB2 = 2 ; For compatibility
 
; DDRB - Data Direction Register, Port B
.equ DDB0 = 0 ;
.equ DDB1 = 1 ;
.equ DDB2 = 2 ;
 
; PINB - Input Pins, Port B
.equ PINB0 = 0 ;
.equ PINB1 = 1 ;
.equ PINB2 = 2 ;
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x03ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 128
.equ RAMEND = 0x00df
.equ XRAMEND = 0x0000
.equ E2END = 0x007f
.equ EEPROMEND = 0x007f
.equ EEADRBITS = 7
#pragma AVRPART MEMORY PROG_FLASH 2048
#pragma AVRPART MEMORY EEPROM 128
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow
 
.equ INT_VECTORS_SIZE = 3 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _2323DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/2343def.inc
0,0 → 1,256
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2343.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "2343def.inc"
;* Title : Register/Bit Definitions for the AT90S2343
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S2343
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _2343DEF_INC_
#define _2343DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S2343
#pragma AVRPART ADMIN PART_NAME AT90S2343
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x91
.equ SIGNATURE_002 = 0x03
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; SPL - Stack Pointer Low
.equ SP0 = 0 ; Stack pointer bit 0
.equ SP1 = 1 ; Stack pointer bit 1
.equ SP2 = 2 ; Stack pointer bit 2
.equ SP3 = 3 ; Stack pointer bit 3
.equ SP4 = 4
.equ SP5 = 5 ; Stack pointer bit 5
.equ SP6 = 6 ; Stack pointer bit 6
.equ SP7 = 7 ; Stack pointer bit 7
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
 
; MCUSR -
.equ PORF = 0 ; Power On Reset Flag
.equ EXTRF = 1 ; Externl Reset Flag
 
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
 
; GIFR - General Interrupt Flag Register
.equ INTF0 = 6 ; External Interrupt Flag 0
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** PORTB ************************
; PORTB - Data Register, Port B
.equ PORTB0 = 0 ;
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ;
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ;
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ;
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ;
.equ PB4 = 4 ; For compatibility
 
; DDRB - Data Direction Register, Port B
.equ DDB0 = 0 ;
.equ DDB1 = 1 ;
.equ DDB2 = 2 ;
.equ DDB3 = 3 ;
.equ DDB4 = 4 ;
 
; PINB - Input Pins, Port B
.equ PINB0 = 0 ;
.equ PINB1 = 1 ;
.equ PINB2 = 2 ;
.equ PINB3 = 3 ;
.equ PINB4 = 4 ;
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x03ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 128
.equ RAMEND = 0x00df
.equ XRAMEND = 0x0000
.equ E2END = 0x007f
.equ EEPROMEND = 0x007f
.equ EEADRBITS = 7
#pragma AVRPART MEMORY PROG_FLASH 2048
#pragma AVRPART MEMORY EEPROM 128
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow
 
.equ INT_VECTORS_SIZE = 3 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _2343DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/4414def.inc
0,0 → 1,528
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4414.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "4414def.inc"
;* Title : Register/Bit Definitions for the AT90S4414
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S4414
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _4414DEF_INC_
#define _4414DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S4414
#pragma AVRPART ADMIN PART_NAME AT90S4414
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x92
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x25
.equ ICR1L = 0x24
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ ICF1 = 3 ; Input Capture Flag 1
.equ OCF1B = 5 ; Output Compare Flag 1B
.equ OCF1A = 6 ; Output Compare Flag 1A
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
.equ SRW = 6 ; External SRAM Wait State
.equ SRE = 7 ; External SRAM Enable
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ SPIEN = 1 ; Serial Program Downloading Enabled
.equ FSTRT = 2 ; Short Start-up time selected
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x07ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 256
.equ RAMEND = 0x015f
.equ XRAMEND = 0xffff
.equ E2END = 0x00ff
.equ EEPROMEND = 0x00ff
.equ EEADRBITS = 8
#pragma AVRPART MEMORY PROG_FLASH 4096
#pragma AVRPART MEMORY EEPROM 256
#pragma AVRPART MEMORY INT_SRAM SIZE 256
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt Request 0
.equ INT1addr = 0x0002 ; External Interrupt Request 1
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB
.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0008 ; Serial Transfer Complete
.equ URXCaddr = 0x0009 ; UART, Rx Complete
.equ UDREaddr = 0x000a ; UART Data Register Empty
.equ UTXCaddr = 0x000b ; UART, Tx Complete
.equ ACIaddr = 0x000c ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 13 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _4414DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/4433def.inc
0,0 → 1,522
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4433.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "4433def.inc"
;* Title : Register/Bit Definitions for the AT90S4433
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S4433
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _4433DEF_INC_
#define _4433DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S4433
#pragma AVRPART ADMIN PART_NAME AT90S4433
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x92
.equ SIGNATURE_002 = 0x03
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SP = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1H = 0x2b
.equ OCR1L = 0x2a
.equ ICR1H = 0x27
.equ ICR1L = 0x26
.equ WDTCR = 0x21
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ UCSRA = 0x0b
.equ UCSRB = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSR = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
.equ UBRRHI = 0x03
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ AINBG = 6 ; Analog Comparator Bandgap Select
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ ADCBG = 6 ; ADC Bandgap Select
 
; ADCSR - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADFR = 5 ; ADC Free Running Select
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
 
; ADCH - ADC Data Register High Byte
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
 
; ADCL - ADC Data Register Low Byte
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; UCSRA - UART Control and Status register A
.equ MPCM = 0 ; Mulit-processor Communication Mode
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmitt Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCSRB - UART Control an Status register B
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRRHI - UART Baud Rate Register High Byte
.equ UBRRHI0 = 0 ; UART Baud Rate Register High Byte bit 0
.equ UBRRHI1 = 1 ; UART Baud Rate Register High Byte bit 1
.equ UBRRHI2 = 2 ; UART Baud Rate Register High Byte bit 2
.equ UBRRHI3 = 3 ; UART Baud Rate Register High Byte bit 3
 
; UBRR - UART Baud Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; SP - Stack Pointer
.equ SP0 = 0 ; Stack pointer bit 0
.equ SP1 = 1 ; Stack pointer bit 1
.equ SP2 = 2 ; Stack pointer bit 2
.equ SP3 = 3 ; Stack pointer bit 3
.equ SP4 = 4 ; Stack pointer bit 4
.equ SP5 = 5 ; Stack pointer bit 5
.equ SP6 = 6 ; Stack pointer bit 6
.equ SP7 = 7 ; Stack pointer bit 7
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM = 4 ; Sleep Mode Select
.equ SE = 5 ; Sleep Enable
 
; MCUSR -
.equ PORF = 0 ; Power-on Reset Flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-Out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7
 
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
 
 
; ***** PORTB ************************
; PORTB - Data Register, Port B
.equ PORTB0 = 0 ;
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ;
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ;
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ;
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ;
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ;
.equ PB5 = 5 ; For compatibility
 
; DDRB - Data Direction Register, Port B
.equ DDB0 = 0 ;
.equ DDB1 = 1 ;
.equ DDB2 = 2 ;
.equ DDB3 = 3 ;
.equ DDB4 = 4 ;
.equ DDB5 = 5 ;
 
; PINB - Input Pins, Port B
.equ PINB0 = 0 ;
.equ PINB1 = 1 ;
.equ PINB2 = 2 ;
.equ PINB3 = 3 ;
.equ PINB4 = 4 ;
.equ PINB5 = 5 ;
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
.equ OCIE1 = 6 ; Timer/Counter1 Output Compare Match Interrupt Enable
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ ICF1 = 3 ; Input Capture Flag 1
.equ OCF1 = 6 ; Output Compare Flag 1
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM10 = 6 ; Compare Ouput Mode 1, bit 0
.equ COM11 = 7 ; Compare Output Mode 1, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x07ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 128
.equ RAMEND = 0x00df
.equ XRAMEND = 0x0000
.equ E2END = 0x00ff
.equ EEPROMEND = 0x00ff
.equ EEADRBITS = 8
#pragma AVRPART MEMORY PROG_FLASH 4096
#pragma AVRPART MEMORY EEPROM 256
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ INT1addr = 0x0002 ; External Interrupt 1
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0007 ; Serial Transfer Complete
.equ URXCaddr = 0x0008 ; UART, Rx Complete
.equ UDREaddr = 0x0009 ; UART Data Register Empty
.equ UTXCaddr = 0x000a ; UART, Tx Complete
.equ ADCCaddr = 0x000b ; ADC Conversion Complete
.equ ERDYaddr = 0x000c ; EEPROM Ready
.equ ACIaddr = 0x000d ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 14 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _4433DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/4434def.inc
0,0 → 1,613
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4434.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "4434def.inc"
;* Title : Register/Bit Definitions for the AT90S4434
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S4434
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _4434DEF_INC_
#define _4434DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S4434
#pragma AVRPART ADMIN PART_NAME AT90S4434
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x93
.equ SIGNATURE_002 = 0x03
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x27
.equ ICR1L = 0x26
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ ASSR = 0x22
.equ WDTCR = 0x21
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSR = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 3 ; Output Compare Flag 1B
.equ OCF1A = 4 ; Output Compare Flag 1A
.equ ICF1 = 5 ; Input Capture Flag 1
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** TIMER_COUNTER_2 **************
; TCCR2 - Timer/Counter Control Register
.equ CS20 = 0 ; Clock Select
.equ CS21 = 1 ; Clock Select
.equ CS22 = 2 ; Clock Select
.equ CTC2 = 3 ; Clear Timer/Counter Compare Match
.equ COM20 = 4 ; Compare Match Output Mode
.equ COM21 = 5 ; Compare Match Output Mode
.equ PWM2 = 6 ; Pulse Width Modulator Enable
 
; TCNT2 - Timer/Counter Register
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
 
; OCR2 - Output Compare Register
.equ OCR2_0 = 0 ; Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Output Compare Register Bit 7
 
; ASSR - Asynchronous Status Register
.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
.equ AS2 = 3 ; Asynchronous Timer 2
 
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
 
; ADCSR - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADFR = 5 ; ADC Free Running Select
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
 
; ADCH - ADC Data Register High Byte
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
 
; ADCL - ADC Data Register Low Byte
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EEWEE = EEMWE ; For compatibility
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM0 = 4 ; Sleep Mode Select 0
.equ SM1 = 5 ; Sleep Mode Select 1
.equ SE = 6 ; Sleep Enable
 
; MCUSR -
.equ PORF = 0 ; Power-on Reset Flag
.equ EXTRF = 1 ; External Reset Flag
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ SPIEN = 1 ; Serial Program Downloading Enabled
.equ FSTRT = 2 ; Short Start-up time selected
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x07ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 256
.equ RAMEND = 0x015f
.equ XRAMEND = 0x0000
.equ E2END = 0x00ff
.equ EEPROMEND = 0x00ff
.equ EEADRBITS = 8
#pragma AVRPART MEMORY PROG_FLASH 4096
#pragma AVRPART MEMORY EEPROM 256
#pragma AVRPART MEMORY INT_SRAM SIZE 256
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ INT1addr = 0x0002 ; External Interrupt 1
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete
.equ URXCaddr = 0x000b ; UART, RX Complete
.equ UDREaddr = 0x000c ; UART Data Register Empty
.equ UTXCaddr = 0x000d ; UART, TX Complete
.equ ADCCaddr = 0x000e ; ADC Conversion Complete
.equ ERDYaddr = 0x000f ; EEPROM Ready
.equ ACIaddr = 0x0010 ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 17 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _4434DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/8515def.inc
0,0 → 1,519
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S8515.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "8515def.inc"
;* Title : Register/Bit Definitions for the AT90S8515
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S8515
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _8515DEF_INC_
#define _8515DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S8515
#pragma AVRPART ADMIN PART_NAME AT90S8515
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x93
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x25
.equ ICR1L = 0x24
.equ WDTCR = 0x21
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ ICF1 = 3 ; Input Capture Flag 1
.equ OCF1B = 5 ; Output Compare Flag 1B
.equ OCF1A = 6 ; Output Compare Flag 1A
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM = 4 ; Sleep Mode
.equ SE = 5 ; Sleep Enable
.equ SRW = 6 ; External SRAM Wait State
.equ SRE = 7 ; External SRAM Enable
 
 
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ SPIEN = 1 ; Serial Program Downloading Enabled
.equ FSTRT = 2 ; Short Start-up time selected
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x0fff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 512
.equ RAMEND = 0x025f
.equ XRAMEND = 0xffff
.equ E2END = 0x01ff
.equ EEPROMEND = 0x01ff
.equ EEADRBITS = 9
#pragma AVRPART MEMORY PROG_FLASH 8192
#pragma AVRPART MEMORY EEPROM 512
#pragma AVRPART MEMORY INT_SRAM SIZE 512
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt Request 0
.equ INT1addr = 0x0002 ; External Interrupt Request 1
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB
.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0008 ; Serial Transfer Complete
.equ URXCaddr = 0x0009 ; UART, Rx Complete
.equ UDREaddr = 0x000a ; UART Data Register Empty
.equ UTXCaddr = 0x000b ; UART, Tx Complete
.equ ACIaddr = 0x000c ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 13 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _8515DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/8535def.inc
0,0 → 1,613
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: AT90S8535.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "8535def.inc"
;* Title : Register/Bit Definitions for the AT90S8535
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90S8535
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _8535DEF_INC_
#define _8535DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device AT90S8535
#pragma AVRPART ADMIN PART_NAME AT90S8535
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x93
.equ SIGNATURE_002 = 0x03
 
#pragma AVRPART CORE CORE_VERSION V1
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x27
.equ ICR1L = 0x26
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ ASSR = 0x22
.equ WDTCR = 0x21
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSR = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
 
; TCCR0 - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
 
; TCNT0 - Timer Counter 0
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 3 ; Output Compare Flag 1B
.equ OCF1A = 4 ; Output Compare Flag 1A
.equ ICF1 = 5 ; Input Capture Flag 1
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** TIMER_COUNTER_2 **************
; TCCR2 - Timer/Counter Control Register
.equ CS20 = 0 ; Clock Select
.equ CS21 = 1 ; Clock Select
.equ CS22 = 2 ; Clock Select
.equ CTC2 = 3 ; Clear Timer/Counter Compare Match
.equ COM20 = 4 ; Compare Match Output Mode
.equ COM21 = 5 ; Compare Match Output Mode
.equ PWM2 = 6 ; Pulse Width Modulator Enable
 
; TCNT2 - Timer/Counter Register
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
 
; OCR2 - Output Compare Register
.equ OCR2_0 = 0 ; Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Output Compare Register Bit 7
 
; ASSR - Asynchronous Status Register
.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
.equ AS2 = 3 ; Asynchronous Timer 2
 
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
 
; ADCSR - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADFR = 5 ; ADC Free Running Select
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
 
; ADCH - ADC Data Register High Byte
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
 
; ADCL - ADC Data Register Low Byte
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EEWEE = EEMWE ; For compatibility
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM0 = 4 ; Sleep Mode Select 0
.equ SM1 = 5 ; Sleep Mode Select 1
.equ SE = 6 ; Sleep Enable
 
; MCUSR -
.equ PORF = 0 ; Power-on Reset Flag
.equ EXTRF = 1 ; External Reset Flag
 
 
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
 
; GIFR - General Interrupt Flag register
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ SPIEN = 1 ; Serial Program Downloading Enabled
.equ FSTRT = 2 ; Short Start-up time selected
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x0fff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 512
.equ RAMEND = 0x025f
.equ XRAMEND = 0x0000
.equ E2END = 0x01ff
.equ EEPROMEND = 0x01ff
.equ EEADRBITS = 9
#pragma AVRPART MEMORY PROG_FLASH 8192
#pragma AVRPART MEMORY EEPROM 512
#pragma AVRPART MEMORY INT_SRAM SIZE 512
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ INT1addr = 0x0002 ; External Interrupt 1
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete
.equ URXCaddr = 0x000b ; UART, RX Complete
.equ UDREaddr = 0x000c ; UART Data Register Empty
.equ UTXCaddr = 0x000d ; UART, TX Complete
.equ ADCCaddr = 0x000e ; ADC Conversion Complete
.equ ERDYaddr = 0x000f ; EEPROM Ready
.equ ACIaddr = 0x0010 ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 17 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _8535DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/m103def.inc
0,0 → 1,713
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: ATmega103.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m103def.inc"
;* Title : Register/Bit Definitions for the ATmega103
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega103
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _M103DEF_INC_
#define _M103DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device ATmega103
#pragma AVRPART ADMIN PART_NAME ATmega103
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x97
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V2
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED movw:break:lpm rd,z:spm
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ XDIV = 0x3c
.equ RAMPZ = 0x3b
.equ EICR = 0x3a
.equ EIMSK = 0x39
.equ EIFR = 0x38
.equ TIMSK = 0x37
.equ TIFR = 0x36
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ OCR0 = 0x31
.equ ASSR = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x27
.equ ICR1L = 0x26
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ WDTCR = 0x21
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ USR = 0x0b
.equ UCR = 0x0a
.equ UBRR = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSR = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
.equ PORTE = 0x03
.equ DDRE = 0x02
.equ PINE = 0x01
.equ PINF = 0x00
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
 
; ADCSR - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
 
; ADCH - ADC Data Register High Byte
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
 
; ADCL - ADC Data Register Low Byte
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
 
 
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Comparator Output
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** UART *************************
; UDR - UART I/O Data Register
.equ UDR0 = 0 ; UART I/O Data Register bit 0
.equ UDR1 = 1 ; UART I/O Data Register bit 1
.equ UDR2 = 2 ; UART I/O Data Register bit 2
.equ UDR3 = 3 ; UART I/O Data Register bit 3
.equ UDR4 = 4 ; UART I/O Data Register bit 4
.equ UDR5 = 5 ; UART I/O Data Register bit 5
.equ UDR6 = 6 ; UART I/O Data Register bit 6
.equ UDR7 = 7 ; UART I/O Data Register bit 7
 
; USR - UART Status Register
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; UART Data Register Empty
.equ TXC = 6 ; UART Transmit Complete
.equ RXC = 7 ; UART Receive Complete
 
; UCR - UART Control Register
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ CHR9 = 2 ; 9-bit Characters
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
 
; UBRR - UART BAUD Rate Register
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ SM0 = 3 ; Sleep Mode Select
.equ SM1 = 4 ; Sleep Mode Select
.equ SE = 5 ; Sleep Enable
.equ SRW = 6 ; External SRAM Wait State Select
.equ SRE = 7 ; External SRAM Enable
 
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ EXTREF = EXTRF ; For compatibility
 
; XDIV - XTAL Divide Control Register
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
.equ XDIVEN = 7 ; XTAL Divide Enable
 
; RAMPZ - RAM Page Z Select Register
.equ RAMPZ0 = 0 ; RAMPZ0 = 0: Program memory address $0000 - $7FFF. RAMPZ0 = 1, program memory address $8000 - $FFFF.
 
 
; ***** EXTERNAL_INTERRUPT ***********
; EICR - External Interrupt Control Register B
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
 
; EIMSK - External Interrupt Mask Register
.equ INT0 = 0 ; External Interrupt Request 0 Enable
.equ INT1 = 1 ; External Interrupt Request 1 Enable
.equ INT2 = 2 ; External Interrupt Request 2 Enable
.equ INT3 = 3 ; External Interrupt Request 3 Enable
.equ INT4 = 4 ; External Interrupt Request 4 Enable
.equ INT5 = 5 ; External Interrupt Request 5 Enable
.equ INT6 = 6 ; External Interrupt Request 6 Enable
.equ INT7 = 7 ; External Interrupt Request 7 Enable
 
; EIFR - External Interrupt Flag Register
.equ INTF4 = 4 ; External Interrupt Flag 4
.equ INTF5 = 5 ; External Interrupt Flag 5
.equ INTF6 = 6 ; External Interrupt Flag 6
.equ INTF7 = 7 ; External Interrupt Flag 7
 
 
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
 
; ***** PORTE ************************
; PORTE - Data Register, Port E
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
.equ PORTE3 = 3 ;
.equ PE3 = 3 ; For compatibility
.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
 
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
 
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
 
 
; ***** PORTF ************************
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
 
 
; ***** TIMER_COUNTER_2 **************
; TIMSK - Timer/Counter Interrupt Mask register
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
 
; TCCR2 - Timer/Counter2 Control Register
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match
.equ COM20 = 4 ; Compare Output Mode bit 0
.equ COM21 = 5 ; Compare Output Mode bit 1
.equ PWM2 = 6 ; Pulse Width Modulator Enable
 
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
 
; OCR2 - Timer/Counter2 Output Compare Register
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
 
 
; ***** TIMER_COUNTER_0 **************
; TCCR0 - Timer/Counter Control Register
.equ CS00 = 0 ; Clock Select 1
.equ CS01 = 1 ; Clock Select 1
.equ CS02 = 2 ; Clock Select 2
.equ CTC0 = 3 ; CLear Timer/Counter on Compare Match
.equ COM00 = 4 ; Compare match Output Mode 0
.equ COM01 = 5 ; Compare Match Output Mode 1
.equ PWM0 = 6 ; Pulse Width Modulator Enable
 
; TCNT0 - Timer/Counter Register
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
 
; OCR0 - Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
 
; ASSR - Asynchronus Status Register
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
.equ OCR0UB = 1 ; Output Compare register 0 Busy
.equ TCN0UB = 2 ; Timer/Couner0 Update Busy
.equ AS0 = 3 ; Asynchronus Timer/Counter 0
 
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0 = 1 ; Output Compare Flag 0
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 3 ; Output Compare Flag 1B
.equ OCF1A = 4 ; Output Compare Flag 1A
.equ ICF1 = 5 ; Input Capture Flag 1
 
; TCCR1A - Timer/Counter1 Control Register A
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDTOE = 4 ; RW
.equ WDDE = WDTOE ; For compatibility
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ BODEN = 6 ; Brown out detector enable
.equ BODLEVEL = 7 ; Brown out detector trigger level
 
; HIGH fuse bits
 
; EXTENDED fuse bits
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0xffff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 4000
.equ RAMEND = 0x0fff
.equ XRAMEND = 0xffff
.equ E2END = 0x0fff
.equ EEPROMEND = 0x0fff
.equ EEADRBITS = 12
#pragma AVRPART MEMORY PROG_FLASH 131072
#pragma AVRPART MEMORY EEPROM 4096
#pragma AVRPART MEMORY INT_SRAM SIZE 4000
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
 
 
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0002 ; External Interrupt 0
.equ INT1addr = 0x0004 ; External Interrupt 1
.equ INT2addr = 0x0006 ; External Interrupt 2
.equ INT3addr = 0x0008 ; External Interrupt 3
.equ INT4addr = 0x000a ; External Interrupt 4
.equ INT5addr = 0x000c ; External Interrupt 5
.equ INT6addr = 0x000e ; External Interrupt 6
.equ INT7addr = 0x0010 ; External Interrupt 7
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x001a ; Timer/Counter1 Compare Match B
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
.equ URXCaddr = 0x0024 ; UART, Rx Complete
.equ UDREaddr = 0x0026 ; UART Data Register Empty
.equ UTXCaddr = 0x0028 ; UART, Tx Complete
.equ ADCCaddr = 0x002a ; ADC Conversion Complete
.equ ERDYaddr = 0x002c ; EEPROM Ready
.equ ACIaddr = 0x002e ; Analog Comparator
 
.equ INT_VECTORS_SIZE = 48 ; size in words
 
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
 
#endif /* _M103DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/m128def.inc
0,0 → 1,1175
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: ATmega128.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m128def.inc"
;* Title : Register/Bit Definitions for the ATmega128
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega128
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _M128DEF_INC_
#define _M128DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device ATmega128
#pragma AVRPART ADMIN PART_NAME ATmega128
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x97
.equ SIGNATURE_002 = 0x02
 
#pragma AVRPART CORE CORE_VERSION V2E
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ UCSR1C = 0x9d ; MEMORY MAPPED
.equ UDR1 = 0x9c ; MEMORY MAPPED
.equ UCSR1A = 0x9b ; MEMORY MAPPED
.equ UCSR1B = 0x9a ; MEMORY MAPPED
.equ UBRR1L = 0x99 ; MEMORY MAPPED
.equ UBRR1H = 0x98 ; MEMORY MAPPED
.equ UCSR0C = 0x95 ; MEMORY MAPPED
.equ UBRR0H = 0x90 ; MEMORY MAPPED
.equ TCCR3C = 0x8c ; MEMORY MAPPED
.equ TCCR3A = 0x8b ; MEMORY MAPPED
.equ TCCR3B = 0x8a ; MEMORY MAPPED
.equ TCNT3H = 0x89 ; MEMORY MAPPED
.equ TCNT3L = 0x88 ; MEMORY MAPPED
.equ OCR3AH = 0x87 ; MEMORY MAPPED
.equ OCR3AL = 0x86 ; MEMORY MAPPED
.equ OCR3BH = 0x85 ; MEMORY MAPPED
.equ OCR3BL = 0x84 ; MEMORY MAPPED
.equ OCR3CH = 0x83 ; MEMORY MAPPED
.equ OCR3CL = 0x82 ; MEMORY MAPPED
.equ ICR3H = 0x81 ; MEMORY MAPPED
.equ ICR3L = 0x80 ; MEMORY MAPPED
.equ ETIMSK = 0x7d ; MEMORY MAPPED
.equ ETIFR = 0x7c ; MEMORY MAPPED
.equ TCCR1C = 0x7a ; MEMORY MAPPED
.equ OCR1CH = 0x79 ; MEMORY MAPPED
.equ OCR1CL = 0x78 ; MEMORY MAPPED
.equ TWCR = 0x74 ; MEMORY MAPPED
.equ TWDR = 0x73 ; MEMORY MAPPED
.equ TWAR = 0x72 ; MEMORY MAPPED
.equ TWSR = 0x71 ; MEMORY MAPPED
.equ TWBR = 0x70 ; MEMORY MAPPED
.equ OSCCAL = 0x6f ; MEMORY MAPPED
.equ XMCRA = 0x6d ; MEMORY MAPPED
.equ XMCRB = 0x6c ; MEMORY MAPPED
.equ EICRA = 0x6a ; MEMORY MAPPED
.equ SPMCSR = 0x68 ; MEMORY MAPPED
.equ PORTG = 0x65 ; MEMORY MAPPED
.equ DDRG = 0x64 ; MEMORY MAPPED
.equ PING = 0x63 ; MEMORY MAPPED
.equ PORTF = 0x62 ; MEMORY MAPPED
.equ DDRF = 0x61 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ XDIV = 0x3c
.equ RAMPZ = 0x3b
.equ EICRB = 0x3a
.equ EIMSK = 0x39
.equ EIFR = 0x38
.equ TIMSK = 0x37
.equ TIFR = 0x36
.equ MCUCR = 0x35
.equ MCUCSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ OCR0 = 0x31
.equ ASSR = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29
.equ OCR1BL = 0x28
.equ ICR1H = 0x27
.equ ICR1L = 0x26
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ OCDR = 0x22
.equ WDTCR = 0x21
.equ SFIOR = 0x20
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR0 = 0x0c
.equ UCSR0A = 0x0b
.equ UCSR0B = 0x0a
.equ UBRR0L = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSRA = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
.equ PORTE = 0x03
.equ DDRE = 0x02
.equ PINE = 0x01
.equ PINF = 0x00
 
 
; ***** BIT DEFINITIONS **************************************************
 
; ***** ANALOG_COMPARATOR ************
; SFIOR - Special Function IO Register
.equ ACME = 3 ; Analog Comparator Multiplexer Enable
 
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ ACBG = 6 ; Analog Comparator Bandgap Select
.equ ACD = 7 ; Analog Comparator Disable
 
 
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
 
; ADCSRA - The ADC Control and Status register
.equ ADCSR = ADCSRA ; For compatibility
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADFR = 5 ; ADC Free Running Select
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
 
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
 
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
 
 
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
 
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
 
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
 
 
; ***** TWI **************************
; TWBR - TWI Bit Rate register
.equ I2BR = TWBR ; For compatibility
.equ TWBR0 = 0 ;
.equ TWBR1 = 1 ;
.equ TWBR2 = 2 ;
.equ TWBR3 = 3 ;
.equ TWBR4 = 4 ;
.equ TWBR5 = 5 ;
.equ TWBR6 = 6 ;
.equ TWBR7 = 7 ;
 
; TWCR - TWI Control Register
.equ I2CR = TWCR ; For compatibility
.equ TWIE = 0 ; TWI Interrupt Enable
.equ I2IE = TWIE ; For compatibility
.equ TWEN = 2 ; TWI Enable Bit
.equ I2EN = TWEN ; For compatibility
.equ ENI2C = TWEN ; For compatibility
.equ TWWC = 3 ; TWI Write Collition Flag
.equ I2WC = TWWC ; For compatibility
.equ TWSTO = 4 ; TWI Stop Condition Bit
.equ I2STO = TWSTO ; For compatibility
.equ TWSTA = 5 ; TWI Start Condition Bit
.equ I2STA = TWSTA ; For compatibility
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
.equ I2EA = TWEA ; For compatibility
.equ TWINT = 7 ; TWI Interrupt Flag
.equ I2INT = TWINT ; For compatibility
 
; TWSR - TWI Status Register
.equ I2SR = TWSR ; For compatibility
.equ TWPS0 = 0 ; TWI Prescaler
.equ TWS0 = TWPS0 ; For compatibility
.equ I2GCE = TWPS0 ; For compatibility
.equ TWPS1 = 1 ; TWI Prescaler
.equ TWS1 = TWPS1 ; For compatibility
.equ TWS3 = 3 ; TWI Status
.equ I2S3 = TWS3 ; For compatibility
.equ TWS4 = 4 ; TWI Status
.equ I2S4 = TWS4 ; For compatibility
.equ TWS5 = 5 ; TWI Status
.equ I2S5 = TWS5 ; For compatibility
.equ TWS6 = 6 ; TWI Status
.equ I2S6 = TWS6 ; For compatibility
.equ TWS7 = 7 ; TWI Status
.equ I2S7 = TWS7 ; For compatibility
 
; TWDR - TWI Data register
.equ I2DR = TWDR ; For compatibility
.equ TWD0 = 0 ; TWI Data Register Bit 0
.equ TWD1 = 1 ; TWI Data Register Bit 1
.equ TWD2 = 2 ; TWI Data Register Bit 2
.equ TWD3 = 3 ; TWI Data Register Bit 3
.equ TWD4 = 4 ; TWI Data Register Bit 4
.equ TWD5 = 5 ; TWI Data Register Bit 5
.equ TWD6 = 6 ; TWI Data Register Bit 6
.equ TWD7 = 7 ; TWI Data Register Bit 7
 
; TWAR - TWI (Slave) Address register
.equ I2AR = TWAR ; For compatibility
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
 
 
; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ UDR00 = 0 ; USART I/O Data Register bit 0
.equ UDR01 = 1 ; USART I/O Data Register bit 1
.equ UDR02 = 2 ; USART I/O Data Register bit 2
.equ UDR03 = 3 ; USART I/O Data Register bit 3
.equ UDR04 = 4 ; USART I/O Data Register bit 4
.equ UDR05 = 5 ; USART I/O Data Register bit 5
.equ UDR06 = 6 ; USART I/O Data Register bit 6
.equ UDR07 = 7 ; USART I/O Data Register bit 7
 
; UCSR0A - USART Control and Status Register A
.equ MPCM0 = 0 ; Multi-processor Communication Mode
.equ U2X0 = 1 ; Double the USART transmission speed
.equ UPE0 = 2 ; Parity Error
.equ DOR0 = 3 ; Data overRun
.equ FE0 = 4 ; Framing Error
.equ UDRE0 = 5 ; USART Data Register Empty
.equ TXC0 = 6 ; USART Transmitt Complete
.equ RXC0 = 7 ; USART Receive Complete
 
; UCSR0B - USART Control and Status Register B
.equ TXB80 = 0 ; Transmit Data Bit 8
.equ RXB80 = 1 ; Receive Data Bit 8
.equ UCSZ02 = 2 ; Character Size
.equ UCSZ2 = UCSZ02 ; For compatibility
.equ TXEN0 = 3 ; Transmitter Enable
.equ RXEN0 = 4 ; Receiver Enable
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
 
; UCSR0C - USART Control and Status Register C
.equ UCPOL0 = 0 ; Clock Polarity
.equ UCSZ00 = 1 ; Character Size
.equ UCSZ01 = 2 ; Character Size
.equ USBS0 = 3 ; Stop Bit Select
.equ UPM00 = 4 ; Parity Mode Bit 0
.equ UPM01 = 5 ; Parity Mode Bit 1
.equ UMSEL0 = 6 ; USART Mode Select
 
 
; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
.equ UDR10 = 0 ; USART I/O Data Register bit 0
.equ UDR11 = 1 ; USART I/O Data Register bit 1
.equ UDR12 = 2 ; USART I/O Data Register bit 2
.equ UDR13 = 3 ; USART I/O Data Register bit 3
.equ UDR14 = 4 ; USART I/O Data Register bit 4
.equ UDR15 = 5 ; USART I/O Data Register bit 5
.equ UDR16 = 6 ; USART I/O Data Register bit 6
.equ UDR17 = 7 ; USART I/O Data Register bit 7
 
; UCSR1A - USART Control and Status Register A
.equ MPCM1 = 0 ; Multi-processor Communication Mode
.equ U2X1 = 1 ; Double the USART transmission speed
.equ UPE1 = 2 ; Parity Error
.equ DOR1 = 3 ; Data overRun
.equ FE1 = 4 ; Framing Error
.equ UDRE1 = 5 ; USART Data Register Empty
.equ TXC1 = 6 ; USART Transmitt Complete
.equ RXC1 = 7 ; USART Receive Complete
 
; UCSR1B - USART Control and Status Register B
.equ TXB81 = 0 ; Transmit Data Bit 8
.equ RXB81 = 1 ; Receive Data Bit 8
.equ UCSZ12 = 2 ; Character Size
.equ TXEN1 = 3 ; Transmitter Enable
.equ RXEN1 = 4 ; Receiver Enable
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
 
; UCSR1C - USART Control and Status Register C
.equ UCPOL1 = 0 ; Clock Polarity
.equ UCSZ10 = 1 ; Character Size
.equ UCSZ11 = 2 ; Character Size
.equ USBS1 = 3 ; Stop Bit Select
.equ UPM10 = 4 ; Parity Mode Bit 0
.equ UPM11 = 5 ; Parity Mode Bit 1
.equ UMSEL1 = 6 ; USART Mode Select
 
 
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
 
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ SM2 = 2 ; Sleep Mode Select
.equ SM0 = 3 ; Sleep Mode Select
.equ SM1 = 4 ; Sleep Mode Select
.equ SE = 5 ; Sleep Enable
.equ SRW10 = 6 ; External SRAM Wait State Select
.equ SRE = 7 ; External SRAM Enable
 
; XMCRA - External Memory Control Register A
.equ SRW11 = 1 ; Wait state select bit upper page
.equ SRW00 = 2 ; Wait state select bit lower page
.equ SRW01 = 3 ; Wait state select bit lower page
.equ SRL0 = 4 ; Wait state page limit
.equ SRL1 = 5 ; Wait state page limit
.equ SRL2 = 6 ; Wait state page limit
 
; XMCRB - External Memory Control Register B
.equ XMM0 = 0 ; External Memory High Mask
.equ XMM1 = 1 ; External Memory High Mask
.equ XMM2 = 2 ; External Memory High Mask
.equ XMBK = 7 ; External Memory Bus Keeper Enable
 
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value
.equ CAL1 = 1 ; Oscillator Calibration Value
.equ CAL2 = 2 ; Oscillator Calibration Value
.equ CAL3 = 3 ; Oscillator Calibration Value
.equ CAL4 = 4 ; Oscillator Calibration Value
.equ CAL5 = 5 ; Oscillator Calibration Value
.equ CAL6 = 6 ; Oscillator Calibration Value
.equ CAL7 = 7 ; Oscillator Calibration Value
 
; XDIV - XTAL Divide Control Register
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
.equ XDIVEN = 7 ; XTAL Divide Enable
 
; MCUCSR - MCU Control And Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
.equ JTRF = 4 ; JTAG Reset Flag
.equ JTD = 7 ; JTAG Interface Disable
 
; RAMPZ - RAM Page Z Select Register
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
 
 
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMCR = SPMCSR ; For compatibility
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ ASRE = RWWSRE ; For compatibility
.equ RWWSB = 6 ; Read While Write Section Busy
.equ ASB = RWWSB ; For compatibility
.equ SPMIE = 7 ; SPM Interrupt Enable
 
 
; ***** JTAG *************************
; OCDR - On-Chip Debug Related Register in I/O Memory
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
.equ IDRD = OCDR7 ; For compatibility
 
; MCUCSR - MCU Control And Status Register
;.equ JTRF = 4 ; JTAG Reset Flag
;.equ JTD = 7 ; JTAG Interface Disable
 
 
; ***** MISC *************************
; SFIOR - Special Function IO Register
.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
.equ PSR1 = PSR321 ; For compatibility
.equ PSR2 = PSR321 ; For compatibility
.equ PSR3 = PSR321 ; For compatibility
.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
.equ PUD = 2 ; Pull Up Disable
;.equ ACME = 3 ; Analog Comparator Multiplexer Enable
.equ TSM = 7 ; Timer/Counter Synchronization Mode
 
 
; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
.equ ISC00 = 0 ; External Interrupt Sense Control Bit
.equ ISC01 = 1 ; External Interrupt Sense Control Bit
.equ ISC10 = 2 ; External Interrupt Sense Control Bit
.equ ISC11 = 3 ; External Interrupt Sense Control Bit
.equ ISC20 = 4 ; External Interrupt Sense Control Bit
.equ ISC21 = 5 ; External Interrupt Sense Control Bit
.equ ISC30 = 6 ; External Interrupt Sense Control Bit
.equ ISC31 = 7 ; External Interrupt Sense Control Bit
 
; EICRB - External Interrupt Control Register B
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
 
; EIMSK - External Interrupt Mask Register
.equ GICR = EIMSK ; For compatibility
.equ GIMSK = EIMSK ; For compatibility
.equ INT0 = 0 ; External Interrupt Request 0 Enable
.equ INT1 = 1 ; External Interrupt Request 1 Enable
.equ INT2 = 2 ; External Interrupt Request 2 Enable
.equ INT3 = 3 ; External Interrupt Request 3 Enable
.equ INT4 = 4 ; External Interrupt Request 4 Enable
.equ INT5 = 5 ; External Interrupt Request 5 Enable
.equ INT6 = 6 ; External Interrupt Request 6 Enable
.equ INT7 = 7 ; External Interrupt Request 7 Enable
 
; EIFR - External Interrupt Flag Register
.equ GIFR = EIFR ; For compatibility
.equ INTF0 = 0 ; External Interrupt Flag 0
.equ INTF1 = 1 ; External Interrupt Flag 1
.equ INTF2 = 2 ; External Interrupt Flag 2
.equ INTF3 = 3 ; External Interrupt Flag 3
.equ INTF4 = 4 ; External Interrupt Flag 4
.equ INTF5 = 5 ; External Interrupt Flag 5
.equ INTF6 = 6 ; External Interrupt Flag 6
.equ INTF7 = 7 ; External Interrupt Flag 7
 
 
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
 
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
 
 
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
 
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
 
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
 
 
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
 
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
 
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
 
 
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
 
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
 
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
 
 
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
 
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
 
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
 
 
; ***** PORTE ************************
; PORTE - Data Register, Port E
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
.equ PORTE3 = 3 ;
.equ PE3 = 3 ; For compatibility
.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
 
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
 
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
 
 
; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
 
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
 
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
 
 
; ***** PORTG ************************
; PORTG - Data Register, Port G
.equ PORTG0 = 0 ;
.equ PG0 = 0 ; For compatibility
.equ PORTG1 = 1 ;
.equ PG1 = 1 ; For compatibility
.equ PORTG2 = 2 ;
.equ PG2 = 2 ; For compatibility
.equ PORTG3 = 3 ;
.equ PG3 = 3 ; For compatibility
.equ PORTG4 = 4 ;
.equ PG4 = 4 ; For compatibility
 
; DDRG - Data Direction Register, Port G
.equ DDG0 = 0 ;
.equ DDG1 = 1 ;
.equ DDG2 = 2 ;
.equ DDG3 = 3 ;
.equ DDG4 = 4 ;
 
; PING - Input Pins, Port G
.equ PING0 = 0 ;
.equ PING1 = 1 ;
.equ PING2 = 2 ;
.equ PING3 = 3 ;
.equ PING4 = 4 ;
 
 
; ***** TIMER_COUNTER_0 **************
; TCCR0 - Timer/Counter Control Register
.equ CS00 = 0 ; Clock Select 0
.equ CS01 = 1 ; Clock Select 1
.equ CS02 = 2 ; Clock Select 2
.equ WGM01 = 3 ; Waveform Generation Mode 1
.equ CTC0 = WGM01 ; For compatibility
.equ COM00 = 4 ; Compare match Output Mode 0
.equ COM01 = 5 ; Compare Match Output Mode 1
.equ WGM00 = 6 ; Waveform Generation Mode 0
.equ PWM0 = WGM00 ; For compatibility
.equ FOC0 = 7 ; Force Output Compare
 
; TCNT0 - Timer/Counter Register
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
 
; OCR0 - Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
 
; ASSR - Asynchronus Status Register
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
.equ OCR0UB = 1 ; Output Compare register 0 Busy
.equ TCN0UB = 2 ; Timer/Counter0 Update Busy
.equ AS0 = 3 ; Asynchronus Timer/Counter 0
 
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0 = 1 ; Output Compare Flag 0
 
; SFIOR - Special Function IO Register
;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
 
 
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
 
; ETIMSK - Extended Timer/Counter Interrupt Mask Register
.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable
 
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 3 ; Output Compare Flag 1B
.equ OCF1A = 4 ; Output Compare Flag 1A
.equ ICF1 = 5 ; Input Capture Flag 1
 
; ETIFR - Extended Timer/Counter Interrupt Flag register
.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag
 
; SFIOR - Special Function IO Register
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
 
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode Bit 0
.equ PWM10 = WGM10 ; For compatibility
.equ WGM11 = 1 ; Waveform Generation Mode Bit 1
.equ PWM11 = WGM11 ; For compatibility
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
 
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select bit 0
.equ CS11 = 1 ; Clock Select 1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ WGM12 = 3 ; Waveform Generation Mode
.equ CTC10 = WGM12 ; For compatibility
.equ WGM13 = 4 ; Waveform Generation Mode
.equ CTC11 = WGM13 ; For compatibility
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
 
; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1C = 5 ; Force Output Compare for channel C
.equ FOC1B = 6 ; Force Output Compare for channel B
.equ FOC1A = 7 ; Force Output Compare for channel A
 
 
; ***** TIMER_COUNTER_2 **************
; TCCR2 - Timer/Counter Control Register
.equ CS20 = 0 ; Clock Select
.equ CS21 = 1 ; Clock Select
.equ CS22 = 2 ; Clock Select
.equ WGM21 = 3 ; Waveform Generation Mode
.equ CTC2 = WGM21 ; For compatibility
.equ COM20 = 4 ; Compare Match Output Mode
.equ COM21 = 5 ; Compare Match Output Mode
.equ WGM20 = 6 ; Wafeform Generation Mode
.equ PWM2 = WGM20 ; For compatibility
.equ FOC2 = 7 ; Force Output Compare
 
; TCNT2 - Timer/Counter Register
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
 
; OCR2 - Output Compare Register
.equ OCR2_0 = 0 ; Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Output Compare Register Bit 7
 
; TIMSK -
.equ TOIE2 = 6 ;
.equ OCIE2 = 7 ;
 
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
 
 
; ***** TIMER_COUNTER_3 **************
; ETIMSK - Extended Timer/Counter Interrupt Mask Register
.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable
.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable
.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable
.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable
.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
 
; ETIFR - Extended Timer/Counter Interrupt Flag register
.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag
.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag
.equ OCF3B = 3 ; Output Compare Flag 1B
.equ OCF3A = 4 ; Output Compare Flag 1A
.equ ICF3 = 5 ; Input Capture Flag 1
 
; SFIOR - Special Function IO Register
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
;.equ PSR1 = PSR321 ; For compatibility
;.equ PSR2 = PSR321 ; For compatibility
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
 
; TCCR3A - Timer/Counter3 Control Register A
.equ WGM30 = 0 ; Waveform Generation Mode Bit 0
.equ PWM30 = WGM30 ; For compatibility
.equ WGM31 = 1 ; Waveform Generation Mode Bit 1
.equ PWM31 = WGM31 ; For compatibility
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0
.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1
 
; TCCR3B - Timer/Counter3 Control Register B
.equ CS30 = 0 ; Clock Select 3 bit 0
.equ CS31 = 1 ; Clock Select 3 bit 1
.equ CS32 = 2 ; Clock Select3 bit 2
.equ WGM32 = 3 ; Waveform Generation Mode
.equ CTC30 = WGM32 ; For compatibility
.equ WGM33 = 4 ; Waveform Generation Mode
.equ CTC31 = WGM33 ; For compatibility
.equ ICES3 = 6 ; Input Capture 3 Edge Select
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler
 
; TCCR3C - Timer/Counter3 Control Register C
.equ FOC3C = 5 ; Force Output Compare for channel C
.equ FOC3B = 6 ; Force Output Compare for channel B
.equ FOC3A = 7 ; Force Output Compare for channel A
 
 
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
 
 
 
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lock bit
.equ LB2 = 1 ; Lock bit
.equ BLB01 = 2 ; Boot Lock bit
.equ BLB02 = 3 ; Boot Lock bit
.equ BLB11 = 4 ; Boot lock bit
.equ BLB12 = 5 ; Boot lock bit
 
 
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ BODEN = 6 ; Brown out detector enable
.equ BODLEVEL = 7 ; Brown out detector trigger level
 
; HIGH fuse bits
.equ BOOTRST = 0 ; Select Reset Vector
.equ BOOTSZ0 = 1 ; Select Boot Size
.equ BOOTSZ1 = 2 ; Select Boot Size
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ CKOPT = 4 ; Oscillator Options
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ JTAGEN = 6 ; Enable JTAG
.equ OCDEN = 7 ; Enable OCD
 
; EXTENDED fuse bits
.equ WDTON = 0 ; Watchdog timer always on
.equ M103C = 1 ; ATmega103 compatibility mode
 
 
 
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
 
 
 
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0xffff ; Note: Word address
.equ IOEND = 0x00ff
.equ SRAM_START = 0x0100
.equ SRAM_SIZE = 4096
.equ RAMEND = 0x10ff
.equ XRAMEND = 0xffff
.equ E2END = 0x0fff
.equ EEPROMEND = 0x0fff
.equ EEADRBITS = 12
#pragma AVRPART MEMORY PROG_FLASH 131072
#pragma AVRPART MEMORY EEPROM 4096
#pragma AVRPART MEMORY INT_SRAM SIZE 4096
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
 
 
 
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0xf000
.equ NRWW_STOP_ADDR = 0xffff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0xefff
.equ PAGESIZE = 128
.equ FIRSTBOOTSTART = 0xfe00
.equ SECONDBOOTSTART = 0xfc00
.equ THIRDBOOTSTART = 0xf800
.equ FOURTHBOOTSTART = 0xf000
.equ SMALLBOOTSTART = FIRSTBOOTSTART
.equ LARGEBOOTSTART = FOURTHBOOTSTART
 
 
 
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0002 ; External Interrupt Request 0
.equ INT1addr = 0x0004 ; External Interrupt Request 1
.equ INT2addr = 0x0006 ; External Interrupt Request 2
.equ INT3addr = 0x0008 ; External Interrupt Request 3
.equ INT4addr = 0x000a ; External Interrupt Request 4
.equ INT5addr = 0x000c ; External Interrupt Request 5
.equ INT6addr = 0x000e ; External Interrupt Request 6
.equ INT7addr = 0x0010 ; External Interrupt Request 7
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
.equ URXC0addr = 0x0024 ; USART0, Rx Complete
.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty
.equ UTXC0addr = 0x0028 ; USART0, Tx Complete
.equ ADCCaddr = 0x002a ; ADC Conversion Complete
.equ ERDYaddr = 0x002c ; EEPROM Ready
.equ ACIaddr = 0x002e ; Analog Comparator
.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C
.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event
.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A
.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B
.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C
.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow
.equ URXC1addr = 0x003c ; USART1, Rx Complete
.equ UDRE1addr = 0x003e ; USART1, Data Register Empty
.equ UTXC1addr = 0x0040 ; USART1, Tx Complete
.equ TWIaddr = 0x0042 ; 2-wire Serial Interface
.equ SPMRaddr = 0x0044 ; Store Program Memory Read
 
.equ INT_VECTORS_SIZE = 70 ; size in words
 
#endif /* _M128DEF_INC_ */
 
; ***** END OF FILE ******************************************************
/contrib/toolchain/avra/includes/m161def.inc
0,0 → 1,736
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2005-01-11 10:30 ******* Source: ATmega161.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m161def.inc"
;* Title : Register/Bit Definitions for the ATmega161
;* Date : 2005-01-11
;* Version : 2.14
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega161
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
 
#ifndef _M161DEF_INC_
#define _M161DEF_INC_
 
 
#pragma partinc 0
 
; ***** SPECIFY DEVICE ***************************************************
.device ATmega161
#pragma AVRPART ADMIN PART_NAME ATmega161
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x94
.equ SIGNATURE_002 = 0x01
 
#pragma AVRPART CORE CORE_VERSION V2E
 
 
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPH = 0x3e
.equ SPL = 0x3d
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ SPMCR = 0x37
.equ EMCUCR = 0x36
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ OCR0 = 0x31
.equ SFIOR = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1H = 0x2d
.equ TCNT1L = 0x2c
.equ OCR1AH = 0x2b
.equ OCR1AL = 0x2a
.equ OCR1BH = 0x29