/programs/system/drivers/ati2d/accel_2d.h |
---|
64,9 → 64,15 |
void *local; |
}local_pixmap_t; |
#define PX_MEM_SYSTEM 0 |
#define PX_MEM_LOCAL 1 |
#define PX_MEM_GART 2 |
#define PX_LOCK 1 |
#define PX_MEM_MASK 3 |
#define PX_LOCK 1 |
typedef struct |
{ |
local_pixmap_t *dstpix; |
/programs/system/drivers/ati2d/accel_2d.inc |
---|
567,43 → 567,140 |
}; |
#define ADDRREG(addr) ((volatile u32_t *)(rhd.MMIOBase + (addr))) |
static int blit_host(u32_t dstpitch, int dstx, int dsty, |
u32_t src, int srcx, int srcy, |
int w, int h, int srcpitch) |
{ |
u32_t ifl; |
color_t *src_addr; |
ifl = safe_cli(); |
#if R300_PIO |
R5xxFIFOWait(5); |
OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
// RADEON_GMC_DST_CLIPPING | |
RADEON_GMC_BRUSH_NONE | |
RADEON_GMC_DST_32BPP | |
RADEON_GMC_SRC_DATATYPE_COLOR | |
RADEON_DP_SRC_SOURCE_HOST_DATA | |
// RADEON_GMC_BYTE_MSB_TO_LSB | |
R5XX_GMC_CLR_CMP_CNTL_DIS | |
R5XX_GMC_WR_MSK_DIS | |
R5XX_ROP3_S |
); |
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | |
R5XX_DST_Y_TOP_TO_BOTTOM); |
OUTREG(R5XX_DST_PITCH_OFFSET, dstpitch); |
// OUTREG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff)); |
// OUTREG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); |
OUTREG(RADEON_DST_Y_X, (dsty << 16) | (dstx & 0xffff)); |
OUTREG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); |
src_addr = &((color_t*)src)[srcpitch*srcy/4+srcx]; |
while ( h-- ) |
{ |
color_t *tmp_src = src_addr; |
src_addr += srcpitch/4; |
int left = w; |
while( left ) |
{ |
volatile u32_t *d; |
if( left > 8 ) |
{ |
int i; |
R5xxFIFOWait(8); |
d = ADDRREG(RADEON_HOST_DATA0); |
/* Unrolling doesn't improve performance */ |
for ( i = 0; i < 8; i++) |
*d++ = *tmp_src++; |
left -= 8; |
} |
else |
{ |
R5xxFIFOWait(left); |
if( h ) |
d = ADDRREG(RADEON_HOST_DATA7) - (left - 1); |
else |
d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1); |
for ( ; left; --left) |
*d++ = *tmp_src++; |
left = 0; |
}; |
}; |
}; |
#endif |
safe_sti(ifl); |
return ERR_OK; |
} |
int Blit(io_blit_t *blit) |
{ |
clip_t src_clip, dst_clip; |
clip_t src_clip, dst_clip; |
local_pixmap_t *srcpixmap; |
local_pixmap_t *dstpixmap; |
local_pixmap_t *srcpixmap; |
local_pixmap_t *dstpixmap; |
//dbgprintf("Pixblit src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
//dbgprintf("Pixblit src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
//dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap); |
//dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap); |
//dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height); |
//dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height); |
//dbgprintf("srcpitch: %x dstpitch: %x\n", |
// srcpixmap->pitch_offset,dstpixmap->pitch_offset); |
//dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height); |
//dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height); |
//dbgprintf("srcpitch: %x dstpitch: %x\n", |
// srcpixmap->pitch_offset,dstpixmap->pitch_offset); |
src_clip.xmin = 0; |
src_clip.ymin = 0; |
src_clip.xmax = srcpixmap->width-1; |
src_clip.ymax = srcpixmap->height-1; |
src_clip.xmin = 0; |
src_clip.ymin = 0; |
src_clip.xmax = srcpixmap->width-1; |
src_clip.ymax = srcpixmap->height-1; |
dst_clip.xmin = 0; |
dst_clip.ymin = 0; |
dst_clip.xmax = dstpixmap->width-1; |
dst_clip.ymax = dstpixmap->height-1; |
dst_clip.xmin = 0; |
dst_clip.ymin = 0; |
dst_clip.xmax = dstpixmap->width-1; |
dst_clip.ymax = dstpixmap->height-1; |
if( !blit_clip(&dst_clip, &blit->dst_x, &blit->dst_y, |
&src_clip, &blit->src_x, &blit->src_y, |
&blit->w, &blit->h) ) |
{ |
if( !blit_clip(&dst_clip, &blit->dst_x, &blit->dst_y, |
&src_clip, &blit->src_x, &blit->src_y, |
&blit->w, &blit->h) ) |
{ |
u32_t *ring, write; |
u32_t ifl; |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
return blit_host(dstpixmap->pitch_offset, |
blit->dst_x, blit->dst_y, |
srcpixmap->mapped, |
blit->src_x, blit->src_y, |
blit->w, blit->h, |
srcpixmap->pitch); |
ifl = safe_cli(); |
#if R300_PIO |
632,31 → 729,31 |
OUTREG(R5XX_DST_HEIGHT_WIDTH,(blit->h<<16)|blit->w); |
#else |
BEGIN_RING(7); |
BEGIN_RING(7); |
OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5)); |
OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5)); |
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
RADEON_GMC_BRUSH_NONE | |
RADEON_GMC_DST_32BPP | |
RADEON_GMC_SRC_DATATYPE_COLOR | |
RADEON_DP_SRC_SOURCE_MEMORY | |
R5XX_GMC_CLR_CMP_CNTL_DIS | |
R5XX_GMC_WR_MSK_DIS | |
R5XX_ROP3_S |
); |
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
RADEON_GMC_BRUSH_NONE | |
RADEON_GMC_DST_32BPP | |
RADEON_GMC_SRC_DATATYPE_COLOR | |
RADEON_DP_SRC_SOURCE_MEMORY | |
R5XX_GMC_CLR_CMP_CNTL_DIS | |
R5XX_GMC_WR_MSK_DIS | |
R5XX_ROP3_S |
); |
OUT_RING(srcpixmap->pitch_offset); |
OUT_RING(dstpixmap->pitch_offset); |
OUT_RING(srcpixmap->pitch_offset); |
OUT_RING(dstpixmap->pitch_offset); |
OUT_RING((blit->src_x<<16)|blit->src_y); |
OUT_RING((blit->dst_x<<16)|blit->dst_y); |
OUT_RING((blit->w<<16)|blit->h); |
COMMIT_RING(); |
OUT_RING((blit->src_x<<16)|blit->src_y); |
OUT_RING((blit->dst_x<<16)|blit->dst_y); |
OUT_RING((blit->w<<16)|blit->h); |
COMMIT_RING(); |
#endif |
safe_sti(ifl); |
safe_sti(ifl); |
}; |
return ERR_OK; |
}; |
/programs/system/drivers/ati2d/ati2d.c |
---|
1,8 → 1,13 |
#define R300_PIO 0 /* now we have cp */ |
#define R300_PIO 1 |
#define API_VERSION 0x01000100 |
#define SRV_GETVERSION 0 |
#include "types.h" |
#include <stdio.h> |
72,8 → 77,11 |
R5xx2DInit(); |
#if !R300_PIO |
Init3DEngine(&rhd); |
#endif |
retval = RegService("HDRAW", srv_2d); |
dbgprintf("reg service %s as: %x\n", "HDRAW", retval); |
82,11 → 90,6 |
}; |
#define API_VERSION 0x01000100 |
#define SRV_GETVERSION 0 |
int __stdcall srv_2d(ioctl_t *io) |
{ |
u32_t *inp; |
/programs/system/drivers/ati2d/ati_mem.c |
---|
39,11 → 39,12 |
* already mapped into each client's address space. |
*/ |
struct mem_block { |
struct mem_block *next; |
struct mem_block *prev; |
u32_t start; |
size_t size; |
struct mem_block |
{ |
struct mem_block *next; |
struct mem_block *prev; |
u32_t start; |
size_t size; |
}; |
/* Initialize. How to check for an uninitialized heap? |
50,38 → 51,38 |
*/ |
static int init_heap(struct mem_block **heap, int start, int size) |
{ |
struct mem_block *blocks = malloc(sizeof(*blocks)); |
struct mem_block *blocks = malloc(sizeof(*blocks)); |
if (!blocks) |
return -1; //-ENOMEM; |
if (!blocks) |
return -1; //-ENOMEM; |
*heap = malloc(sizeof(**heap)); |
if (!*heap) |
{ |
free(blocks); |
return -1; //-ENOMEM; |
*heap = malloc(sizeof(**heap)); |
if (!*heap) |
{ |
free(blocks); |
return -1; //-ENOMEM; |
} |
blocks->start = start; |
blocks->size = size; |
blocks->next = blocks->prev = *heap; |
blocks->start = start; |
blocks->size = size; |
blocks->next = blocks->prev = *heap; |
__clear(*heap,sizeof(**heap)); |
__clear(*heap,sizeof(**heap)); |
(*heap)->next = (*heap)->prev = blocks; |
(*heap)->start |= USED_BLOCK; |
(*heap)->start |= USED_BLOCK; |
return 0; |
} |
static struct mem_block **get_heap(RHDPtr rhdPtr, int region) |
{ |
switch (region) |
{ |
case RHD_MEM_GART: |
return &rhdPtr->gart_heap; |
case RHD_MEM_FB: |
return &rhdPtr->fb_heap; |
default: |
return NULL; |
switch (region) |
{ |
case RHD_MEM_GART: |
return &rhdPtr->gart_heap; |
case RHD_MEM_FB: |
return &rhdPtr->fb_heap; |
default: |
return NULL; |
} |
} |
91,17 → 92,17 |
/* Maybe cut off the end of an existing block */ |
if (size < p->size) |
{ |
struct mem_block *newblock = malloc(sizeof(*newblock)); |
if (!newblock) |
goto out; |
newblock->start = p->start + size; |
newblock->size = p->size - size; |
newblock->next = p->next; |
newblock->prev = p; |
p->next->prev = newblock; |
p->next = newblock; |
p->size = size; |
p->start|=USED_BLOCK; |
struct mem_block *newblock = malloc(sizeof(*newblock)); |
if (!newblock) |
goto out; |
newblock->start = p->start + size; |
newblock->size = p->size - size; |
newblock->next = p->next; |
newblock->prev = p; |
p->next->prev = newblock; |
p->next = newblock; |
p->size = size; |
p->start|=USED_BLOCK; |
} |
out: |
112,11 → 113,10 |
{ |
struct mem_block *p; |
list_for_each(p, heap) |
{ |
if ( !(p->start & USED_BLOCK) && size <= p->size) |
return split_block(p, size); |
list_for_each(p, heap) |
{ |
if ( !(p->start & USED_BLOCK) && size <= p->size) |
return split_block(p, size); |
} |
return NULL; |
140,32 → 140,32 |
* 'heap' to stop it being subsumed. |
*/ |
p->start &= ~USED_BLOCK; |
p->start &= ~USED_BLOCK; |
if ( !(p->next->start & USED_BLOCK)) |
{ |
if ( !(p->next->start & USED_BLOCK)) |
{ |
struct mem_block *q = p->next; |
p->size += q->size; |
p->next = q->next; |
p->next->prev = p; |
free(q); |
free(q); |
} |
if ( !(p->prev->start & USED_BLOCK)) |
{ |
if ( !(p->prev->start & USED_BLOCK)) |
{ |
struct mem_block *q = p->prev; |
q->size += p->size; |
q->next = p->next; |
q->next->prev = q; |
free(p); |
free(p); |
} |
} |
int rhdInitHeap(RHDPtr rhdPtr) |
{ |
int base = rhdPtr->FbFreeStart; |
int base = rhdPtr->FbFreeStart; |
return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize); |
return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize); |
}; |
void *rhd_mem_alloc(RHDPtr rhdPtr,int region, int size) |
172,22 → 172,22 |
{ |
struct mem_block *block, **heap; |
heap = get_heap(rhdPtr, region); |
if (!heap || !*heap) |
return NULL; |
heap = get_heap(rhdPtr, region); |
if (!heap || !*heap) |
return NULL; |
/* Make things easier on ourselves: all allocations at least |
* 4k aligned. |
*/ |
size = (size+4095) & ~4095; |
size = (size+4095) & ~4095; |
block = alloc_block(*heap, size); |
block = alloc_block(*heap, size); |
if (!block) |
return NULL; |
return NULL; |
return (void*)(block->start & ~USED_BLOCK); |
return (void*)(block->start & ~USED_BLOCK); |
} |
int rhd_mem_free(RHDPtr rhdPtr, int region, void *offset) |
194,16 → 194,16 |
{ |
struct mem_block *block, **heap; |
heap = get_heap(rhdPtr, region); |
if (!heap || !*heap) |
return -1; |
heap = get_heap(rhdPtr, region); |
if (!heap || !*heap) |
return -1; |
block = find_block(*heap, (int)offset); |
block = find_block(*heap, (int)offset); |
if (!block) |
return -1; |
return -1; |
if ( !(block->start & USED_BLOCK)) |
return -1; |
if ( !(block->start & USED_BLOCK)) |
return -1; |
free_block(block); |
return 0; |
212,13 → 212,13 |
void dump_mem() |
{ |
struct mem_block *p; |
struct mem_block **heap; |
struct mem_block **heap; |
heap = &rhd.fb_heap; |
heap = &rhd.fb_heap; |
list_for_each(p, *heap) |
{ |
dbgprintf("block: %x next: %x prev: %x start: %x size:%x\n", |
list_for_each(p, *heap) |
{ |
dbgprintf("block: %x next: %x prev: %x start: %x size:%x\n", |
p,p->next,p->prev,p->start,p->size); |
} |
} |
/programs/system/drivers/ati2d/init.c |
---|
19,25 → 19,25 |
if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
data = INREG(RS690_MC_DATA); |
OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
data = INREG(RS690_MC_DATA); |
} else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
data = INREG(RS600_MC_DATA); |
OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
data = INREG(RS600_MC_DATA); |
} else if (IS_AVIVO_VARIANT) { |
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
(void)INREG(AVIVO_MC_INDEX); |
data = INREG(AVIVO_MC_DATA); |
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
(void)INREG(AVIVO_MC_INDEX); |
data = INREG(AVIVO_MC_DATA); |
OUTREG(AVIVO_MC_INDEX, 0); |
(void)INREG(AVIVO_MC_INDEX); |
OUTREG(AVIVO_MC_INDEX, 0); |
(void)INREG(AVIVO_MC_INDEX); |
} else { |
OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
(void)INREG(R300_MC_IND_INDEX); |
data = INREG(R300_MC_IND_DATA); |
OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
(void)INREG(R300_MC_IND_INDEX); |
data = INREG(R300_MC_IND_DATA); |
OUTREG(R300_MC_IND_INDEX, 0); |
(void)INREG(R300_MC_IND_INDEX); |
OUTREG(R300_MC_IND_INDEX, 0); |
(void)INREG(R300_MC_IND_INDEX); |
} |
return data; |
46,65 → 46,65 |
/* Write MC information */ |
void OUTMC(RHDPtr info, int addr, u32_t data) |
{ |
if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN)); |
OUTREG(RS690_MC_DATA, data); |
OUTREG(RS690_MC_DATA, data); |
OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
} |
else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
} |
else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN)); |
OUTREG(RS600_MC_DATA, data); |
OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); |
} |
else if (IS_AVIVO_VARIANT) { |
} |
else if (IS_AVIVO_VARIANT) { |
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); |
(void)INREG(AVIVO_MC_INDEX); |
OUTREG(AVIVO_MC_DATA, data); |
OUTREG(AVIVO_MC_INDEX, 0); |
(void)INREG(AVIVO_MC_INDEX); |
} |
else { |
} |
else { |
OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN)); |
(void)INREG(R300_MC_IND_INDEX); |
OUTREG(R300_MC_IND_DATA, data); |
OUTREG(R300_MC_IND_INDEX, 0); |
(void)INREG(R300_MC_IND_INDEX); |
} |
} |
} |
static Bool avivo_get_mc_idle(RHDPtr info) |
{ |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
/* no idea where this is on r600 yet */ |
return TRUE; |
} |
else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
} |
else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) |
return TRUE; |
return TRUE; |
else |
return FALSE; |
} |
else if (info->ChipFamily == CHIP_FAMILY_RS600) |
{ |
return FALSE; |
} |
else if (info->ChipFamily == CHIP_FAMILY_RS600) |
{ |
if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) |
return TRUE; |
return TRUE; |
else |
return FALSE; |
} |
else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
return FALSE; |
} |
else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) |
return TRUE; |
return TRUE; |
else |
return FALSE; |
return FALSE; |
} |
else { |
if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
return TRUE; |
else |
return FALSE; |
if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
return TRUE; |
else |
return FALSE; |
} |
} |
448,115 → 448,115 |
#endif |
static void RADEONInitMemoryMap(RHDPtr info) |
{ |
u32_t mem_size; |
u32_t aper_size; |
u32_t mem_size; |
u32_t aper_size; |
radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
&info->mc_agp_location, &info->mc_agp_location_hi); |
radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
&info->mc_agp_location, &info->mc_agp_location_hi); |
dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
/* We shouldn't use info->videoRam here which might have been clipped |
* but the real video RAM instead |
*/ |
if (info->ChipFamily >= CHIP_FAMILY_R600){ |
/* We shouldn't use info->videoRam here which might have been clipped |
* but the real video RAM instead |
*/ |
if (info->ChipFamily >= CHIP_FAMILY_R600){ |
mem_size = INREG(R600_CONFIG_MEMSIZE); |
aper_size = INREG(R600_CONFIG_APER_SIZE); |
} |
else { |
} |
else { |
mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
} |
} |
if (mem_size == 0) |
if (mem_size == 0) |
mem_size = 0x800000; |
/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
Novell bug 204882 + along with lots of ubuntu ones */ |
if (aper_size > mem_size) |
/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
Novell bug 204882 + along with lots of ubuntu ones */ |
if (aper_size > mem_size) |
mem_size = aper_size; |
if ( (info->ChipFamily != CHIP_FAMILY_RS600) && |
(info->ChipFamily != CHIP_FAMILY_RS690) && |
(info->ChipFamily != CHIP_FAMILY_RS740)) { |
if ( (info->ChipFamily != CHIP_FAMILY_RS600) && |
(info->ChipFamily != CHIP_FAMILY_RS690) && |
(info->ChipFamily != CHIP_FAMILY_RS740)) |
{ |
if (info->IsIGP) |
info->mc_fb_location = INREG(RADEON_NB_TOM); |
info->mc_fb_location = INREG(RADEON_NB_TOM); |
else |
{ |
u32_t aper0_base; |
u32_t aper0_base; |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
aper0_base = INREG(R600_CONFIG_F0_BASE); |
} |
else { |
aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
} |
dbgprintf("aper0 base %x\n", aper0_base ); |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
aper0_base = INREG(R600_CONFIG_F0_BASE); |
} |
else { |
aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
} |
dbgprintf("aper0 base %x\n", aper0_base ); |
/* Recent chips have an "issue" with the memory controller, the |
* location must be aligned to the size. We just align it down, |
* too bad if we walk over the top of system memory, we don't |
* use DMA without a remapped anyway. |
* Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
*/ |
if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
info->ChipFamily == CHIP_FAMILY_R300 || |
info->ChipFamily == CHIP_FAMILY_R350 || |
info->ChipFamily == CHIP_FAMILY_RV350 || |
info->ChipFamily == CHIP_FAMILY_RV380 || |
info->ChipFamily == CHIP_FAMILY_R420 || |
info->ChipFamily == CHIP_FAMILY_RV410) |
aper0_base &= ~(mem_size - 1); |
/* Recent chips have an "issue" with the memory controller, the |
* location must be aligned to the size. We just align it down, |
* too bad if we walk over the top of system memory, we don't |
* use DMA without a remapped anyway. |
* Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
*/ |
if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
info->ChipFamily == CHIP_FAMILY_R300 || |
info->ChipFamily == CHIP_FAMILY_R350 || |
info->ChipFamily == CHIP_FAMILY_RV350 || |
info->ChipFamily == CHIP_FAMILY_RV380 || |
info->ChipFamily == CHIP_FAMILY_R420 || |
info->ChipFamily == CHIP_FAMILY_RV410) |
aper0_base &= ~(mem_size - 1); |
if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
info->mc_fb_location = (aper0_base >> 24) | |
(((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
} |
else { |
info->mc_fb_location = (aper0_base >> 16) | |
((aper0_base + mem_size - 1) & 0xffff0000U); |
dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
} |
if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
info->mc_fb_location = (aper0_base >> 24) | |
(((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
} |
else { |
info->mc_fb_location = (aper0_base >> 16) | |
((aper0_base + mem_size - 1) & 0xffff0000U); |
dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
} |
} |
} |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
} |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
} |
else { |
} |
else { |
info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
} |
/* Just disable the damn AGP apertures for now, it may be |
* re-enabled later by the DRM |
*/ |
} |
/* Just disable the damn AGP apertures for now, it may be |
* re-enabled later by the DRM |
*/ |
// if (IS_AVIVO_VARIANT) { |
// if (info->ChipFamily >= CHIP_FAMILY_R600) { |
// OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
// } |
// else { |
// OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
// } |
// info->mc_agp_location = 0x003f0000; |
// } |
// else |
// info->mc_agp_location = 0xffffffc0; |
// if (IS_AVIVO_VARIANT) { |
// if (info->ChipFamily >= CHIP_FAMILY_R600) { |
// OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
// } |
// else { |
// OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
// } |
// info->mc_agp_location = 0x003f0000; |
// } |
// else |
// info->mc_agp_location = 0xffffffc0; |
dbgprintf("RADEONInitMemoryMap() : \n"); |
dbgprintf(" mem_size : 0x%08x\n", (u32_t)mem_size); |
dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation); |
dbgprintf("RADEONInitMemoryMap() : \n"); |
dbgprintf(" mem_size : 0x%08x\n", (u32_t)mem_size); |
dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation); |
#if !R300_PIO |
RADEONUpdateMemMapRegisters(info); |
RADEONUpdateMemMapRegisters(info); |
#endif |
813,31 → 813,31 |
static Bool RADEONPreInitChipType(RHDPtr rhdPtr) |
{ |
u32_t cmd_stat; |
u32_t cmd_stat; |
rhdPtr->ChipErrata = 0; |
rhdPtr->ChipErrata = 0; |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) |
== RADEON_CFG_ATI_REV_A11)) |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) |
== RADEON_CFG_ATI_REV_A11)) |
rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
rhdPtr->cardType = CARD_PCI; |
rhdPtr->cardType = CARD_PCI; |
cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); |
cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); |
if (cmd_stat & RADEON_CAP_LIST) |
{ |
if (cmd_stat & RADEON_CAP_LIST) |
{ |
u32_t cap_ptr, cap_id; |
cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
845,42 → 845,42 |
while(cap_ptr != RADEON_CAP_ID_NULL) |
{ |
cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
rhdPtr->cardType = CARD_AGP; |
break; |
} |
if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
rhdPtr->cardType = CARD_PCIE; |
break; |
} |
cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
rhdPtr->cardType = CARD_AGP; |
break; |
} |
if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
rhdPtr->cardType = CARD_PCIE; |
break; |
} |
cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
} |
} |
} |
dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
(rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP"); |
dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
(rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP"); |
/* treat PCIE IGP cards as PCI */ |
if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP) |
rhdPtr->cardType = CARD_PCI; |
if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP) |
rhdPtr->cardType = CARD_PCI; |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS600) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS690) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS740)) |
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS600) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS690) || |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS740)) |
rhdPtr->has_tcl = FALSE; |
else { |
else { |
rhdPtr->has_tcl = TRUE; |
} |
} |
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
return TRUE; |
return TRUE; |
} |
#if 0 |
958,29 → 958,29 |
RHDPtr info; |
/* We need access to IO space already */ |
if ( !rhdMapMMIO(&rhd) ) { |
if ( !rhdMapMMIO(&rhd) ) { |
dbgprintf("Failed to map MMIO.\n"); |
return FALSE; |
}; |
}; |
if( !RADEONPreInitChipType(&rhd)) |
return FALSE; |
if( !RADEONPreInitChipType(&rhd)) |
return FALSE; |
if (!RADEONPreInitVRAM(&rhd)) |
return FALSE; |
if (!RADEONPreInitVRAM(&rhd)) |
return FALSE; |
RADEONInitMemoryMap(&rhd); |
RADEONInitMemoryMap(&rhd); |
if (!rhd.videoRam) |
{ |
dbgprintf("No Video RAM detected.\n"); |
goto error1; |
} |
dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
if (!rhd.videoRam) |
{ |
dbgprintf("No Video RAM detected.\n"); |
goto error1; |
} |
dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
// rhd.FbFreeStart = 0; |
rhd.FbFreeSize = rhd.videoRam << 10; |
rhd.FbFreeSize = rhd.videoRam << 10; |
// if( !rhdMapFB(&rhd)) |
// return FALSE; |
988,19 → 988,131 |
// rhd.FbScanoutStart = 0; |
// rhd.FbScanoutSize = 8*1024*1024; |
rhd.FbFreeStart = 10*1024*1024; |
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize; |
rhd.FbFreeStart = 10*1024*1024; |
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize; |
rhdInitHeap(&rhd); |
rhdInitHeap(&rhd); |
info = &rhd; |
info = &rhd; |
return TRUE; |
return TRUE; |
error1: |
error1: |
return FALSE; |
return FALSE; |
}; |
static void RADEONPllErrataAfterIndex() |
{ |
if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
return; |
/* This workaround is necessary on rv200 and RS200 or PLL |
* reads may return garbage (among others...) |
*/ |
(void)INREG(RADEON_CLOCK_CNTL_DATA); |
(void)INREG(RADEON_CRTC_GEN_CNTL); |
} |
static void RADEONPllErrataAfterData() |
{ |
/* This function is required to workaround a hardware bug in some (all?) |
* revisions of the R300. This workaround should be called after every |
* CLOCK_CNTL_INDEX register access. If not, register reads afterward |
* may not be correct. |
*/ |
if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
{ |
u32_t save, tmp; |
save = INREG(RADEON_CLOCK_CNTL_INDEX); |
tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
} |
} |
/* Read PLL register */ |
static u32_t RADEONINPLL(int addr) |
{ |
u32_t data; |
OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
RADEONPllErrataAfterIndex(); |
data = INREG(RADEON_CLOCK_CNTL_DATA); |
RADEONPllErrataAfterData(); |
return data; |
}; |
/* Write PLL information */ |
static void RADEONOUTPLL(int addr, u32_t data) |
{ |
OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
RADEON_PLL_WR_EN)); |
RADEONPllErrataAfterIndex(); |
OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
RADEONPllErrataAfterData(); |
} |
static void init_pipes(RHDPtr info) |
{ |
u32_t gb_tile_config = 0; |
if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
(info->ChipFamily == CHIP_FAMILY_R420) || |
(info->ChipFamily == CHIP_FAMILY_RS600) || |
(info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740) || |
(info->ChipFamily == CHIP_FAMILY_RS400) || |
(info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
{ |
u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
if (IS_R500_3D) |
OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
} |
else |
{ |
if ((info->ChipFamily == CHIP_FAMILY_R300) || |
(info->ChipFamily == CHIP_FAMILY_R350)) |
{ |
/* R3xx chips */ |
info->num_gb_pipes = 2; |
} |
else { |
/* RV3xx chips */ |
info->num_gb_pipes = 1; |
} |
} |
if (IS_R300_3D || IS_R500_3D) |
{ |
dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
switch(info->num_gb_pipes) { |
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
default: |
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
} |
OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); |
OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | |
R300_DC_AUTOFLUSH_ENABLE | |
R300_DC_DC_DISABLE_IGNORE_PE)); |
} |
else |
OUTREG(RADEON_RB3D_CNTL, 0); |
}; |
/programs/system/drivers/ati2d/init_3d.inc |
---|
635,7 → 635,6 |
FINISH_ACCEL(); |
} |
safe_sti(ifl); |
} |
/programs/system/drivers/ati2d/init_cp.c |
---|
20,66 → 20,10 |
#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ |
#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ |
#define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */ |
void RADEONPllErrataAfterIndex() |
{ |
if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
return; |
/* This workaround is necessary on rv200 and RS200 or PLL |
* reads may return garbage (among others...) |
*/ |
(void)INREG(RADEON_CLOCK_CNTL_DATA); |
(void)INREG(RADEON_CRTC_GEN_CNTL); |
} |
void RADEONPllErrataAfterData() |
{ |
/* This function is required to workaround a hardware bug in some (all?) |
* revisions of the R300. This workaround should be called after every |
* CLOCK_CNTL_INDEX register access. If not, register reads afterward |
* may not be correct. |
*/ |
if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
{ |
u32_t save, tmp; |
save = INREG(RADEON_CLOCK_CNTL_INDEX); |
tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
} |
} |
/* Read PLL register */ |
u32_t RADEONINPLL(int addr) |
{ |
u32_t data; |
OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
RADEONPllErrataAfterIndex(); |
data = INREG(RADEON_CLOCK_CNTL_DATA); |
RADEONPllErrataAfterData(); |
return data; |
}; |
/* Write PLL information */ |
void RADEONOUTPLL(int addr, u32_t data) |
{ |
OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
RADEON_PLL_WR_EN)); |
RADEONPllErrataAfterIndex(); |
OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
RADEONPllErrataAfterData(); |
} |
void RADEONEngineFlush(RHDPtr info) |
{ |
int i; |
148,62 → 92,7 |
} |
static void init_pipes(RHDPtr info) |
{ |
u32_t gb_tile_config = 0; |
if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
(info->ChipFamily == CHIP_FAMILY_R420) || |
(info->ChipFamily == CHIP_FAMILY_RS600) || |
(info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740) || |
(info->ChipFamily == CHIP_FAMILY_RS400) || |
(info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
{ |
u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
if (IS_R500_3D) |
OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
} |
else |
{ |
if ((info->ChipFamily == CHIP_FAMILY_R300) || |
(info->ChipFamily == CHIP_FAMILY_R350)) |
{ |
/* R3xx chips */ |
info->num_gb_pipes = 2; |
} |
else { |
/* RV3xx chips */ |
info->num_gb_pipes = 1; |
} |
} |
if (IS_R300_3D || IS_R500_3D) |
{ |
dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
switch(info->num_gb_pipes) { |
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
default: |
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
} |
OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); |
OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | |
R300_DC_AUTOFLUSH_ENABLE | |
R300_DC_DC_DISABLE_IGNORE_PE)); |
} |
else |
OUTREG(RADEON_RB3D_CNTL, 0); |
}; |
/* ================================================================ |
* CP control, initialization |
*/ |
357,10 → 246,10 |
void radeon_engine_reset(RHDPtr info) |
{ |
u32_t clock_cntl_index; |
u32_t mclk_cntl; |
u32_t rbbm_soft_reset; |
u32_t host_path_cntl; |
u32_t clock_cntl_index; |
u32_t mclk_cntl; |
u32_t rbbm_soft_reset; |
u32_t host_path_cntl; |
if (info->ChipFamily <= CHIP_FAMILY_RV410) |
{ |
501,6 → 390,7 |
radeon_cp_start(&rhd); |
return TRUE; |
}; |
/programs/system/drivers/ati2d/makefile |
---|
22,8 → 22,7 |
blend.inc \ |
r500.inc \ |
pixmap.inc \ |
accel_2d.inc \ |
accel_3d.inc |
accel_2d.inc |
ATI_SRC:= ati2d.c |
/programs/system/drivers/ati2d/pci.c |
---|
34,83 → 34,81 |
RHDPtr FindPciDevice() |
{ |
const RADEONCardInfo *dev; |
u32_t bus, last_bus; |
const RADEONCardInfo *dev; |
u32_t bus, last_bus; |
if( (last_bus = PciApi(1))==-1) |
return 0; |
if( (last_bus = PciApi(1))==-1) |
return 0; |
for(bus=0;bus<=last_bus;bus++) |
{ |
u32_t devfn; |
for(devfn=0;devfn<256;devfn++) |
for(bus=0;bus<=last_bus;bus++) |
{ |
u32_t id; |
id = PciRead32(bus,devfn, 0); |
u32_t devfn; |
if( (u16_t)id != VENDOR_ATI) |
continue; |
for(devfn=0;devfn<256;devfn++) |
{ |
u32_t id; |
id = PciRead32(bus,devfn, 0); |
rhd.PciDeviceID = (id>>16); |
if( (u16_t)id != VENDOR_ATI) |
continue; |
if( (dev = RadeonDevMatch(rhd.PciDeviceID, RADEONCards))!=NULL) |
{ |
u32_t reg2C; |
int i; |
rhd.PciDeviceID = (id>>16); |
rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID); |
if (!rhd.chipset) |
{ |
dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
return FALSE; |
} |
dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",rhd.chipset,rhd.PciDeviceID); |
if( (dev = RadeonDevMatch(rhd.PciDeviceID, RADEONCards))!=NULL) |
{ |
u32_t reg2C; |
int i; |
rhd.bus = bus; |
rhd.devfn = devfn; |
rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID); |
if (!rhd.chipset){ |
dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
return FALSE; |
} |
dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n", |
rhd.chipset,rhd.PciDeviceID); |
rhd.ChipFamily = dev->chip_family; |
rhd.IsMobility = dev->mobility; |
rhd.IsIGP = dev->igp; |
rhd.HasCRTC2 = !dev->nocrtc2; |
rhd.bus = bus; |
rhd.devfn = devfn; |
rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
reg2C = PciRead32(bus,devfn, 0x2C); |
rhd.ChipFamily = dev->chip_family; |
rhd.IsMobility = dev->mobility; |
rhd.IsIGP = dev->igp; |
rhd.HasCRTC2 = !dev->nocrtc2; |
rhd.subvendor_id = reg2C & 0xFFFF;; |
rhd.subdevice_id = reg2C >> 16; |
reg2C = PciRead32(bus,devfn, 0x2C); |
if (rhd.ChipFamily >= CHIP_FAMILY_R600) |
dbgprintf("R600 unsupported yet.\nExit\n"); |
rhd.subvendor_id = reg2C & 0xFFFF;; |
rhd.subdevice_id = reg2C >> 16; |
if (rhd.ChipFamily >= CHIP_FAMILY_R600) |
dbgprintf("R600 unsupported yet.\nExit\n"); |
for (i = 0; i < 6; i++) |
{ |
u32_t base; |
Bool validSize; |
base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); |
if(base) |
{ |
if (base & PCI_MAP_IO) |
{ |
rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
for (i = 0; i < 6; i++) |
{ |
u32_t base; |
Bool validSize; |
base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); |
if(base) |
{ |
if (base & PCI_MAP_IO){ |
rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
} |
else{ |
rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
} |
} |
rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
} |
return &rhd; |
} |
else |
{ |
rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
} |
} |
rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
} |
return &rhd; |
} |
}; |
}; |
return NULL; |
return NULL; |
} |
/programs/system/drivers/ati2d/pixmap.inc |
---|
50,7 → 50,7 |
pixmap->width = io->width; |
pixmap->height = io->height; |
pixmap->format = PICT_a8r8g8b8; |
pixmap->flags = io->flags; |
pixmap->flags = PX_MEM_LOCAL; //io->flags; |
pixmap->pitch = pitch; |
pixmap->mapped = mapped; |
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10); |
/programs/system/drivers/ati2d/r500.inc |
---|
39,8 → 39,8 |
R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
for (i = 0; i < R5XX_LOOP_COUNT; i++) |
if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
return TRUE; |
if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
return TRUE; |
dbgprintf("%s: Timeout 0x%08x.\n", __func__, |
(unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
54,24 → 54,23 |
/* wait for fifo to clear */ |
for (i = 0; i < R5XX_LOOP_COUNT; i++) |
if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
break; |
if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
break; |
if (i == R5XX_LOOP_COUNT) { |
dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
return FALSE; |
dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
return FALSE; |
} |
/* wait for engine to go idle */ |
for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
R5xx2DFlush(); |
return TRUE; |
} |
if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
R5xx2DFlush(); |
return TRUE; |
} |
} |
dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
return FALSE; |
} |
174,6 → 173,7 |
scr_pixmap.width = rhd.displayWidth; |
scr_pixmap.height = rhd.displayHeight; |
scr_pixmap.format = PICT_a8r8g8b8; |
scr_pixmap.flags = PX_MEM_LOCAL; |
scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch; |
scr_pixmap.local = (void*)rhd.fbLocation; |
scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
188,9 → 188,10 |
OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); |
#if R300_PIO |
#else |
#if !R300_PIO |
init_cp(&rhd); |
#endif |
R5xx2DSetup(); |