| 167,30 → 167,84 |
|---|
| |
| extern RHD_t rhd; |
| |
| typedef struct |
| { |
| int xmin; |
| int ymin; |
| int xmax; |
| int ymax; |
| }clip_t, *PTRclip; |
| |
| |
| typedef struct |
| { |
| u32_t width; |
| u32_t height; |
| u32_t format; |
| u32_t flags; |
| u32_t pitch_offset; |
| u32_t pitch; |
| u32_t offset; |
| void* raw; |
| void* usermap; |
| }pixmap_t; |
| #define R5XX_DP_BRUSH_BKGD_CLR 0x1478 |
| #define R5XX_DP_BRUSH_FRGD_CLR 0x147c |
| #define R5XX_BRUSH_DATA0 0x1480 |
| #define R5XX_BRUSH_DATA1 0x1484 |
| |
| #define PX_LOCK 1 |
| # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
| # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
| # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
| # define RADEON_GMC_BRUSH_NONE (15 << 4) |
| # define RADEON_GMC_DST_16BPP (4 << 8) |
| # define RADEON_GMC_DST_24BPP (5 << 8) |
| # define RADEON_GMC_DST_32BPP (6 << 8) |
| # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
| # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
| # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
| # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
| # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
| # define RADEON_ROP3_S 0x00cc0000 |
| # define RADEON_ROP3_P 0x00f00000 |
| |
| #define RADEON_CP_PACKET0 0x00000000 |
| #define RADEON_CP_PACKET1 0x40000000 |
| #define RADEON_CP_PACKET2 0x80000000 |
| #define RADEON_CP_PACKET3 0xC0000000 |
| |
| # define RADEON_CNTL_PAINT 0x00009100 |
| # define RADEON_CNTL_BITBLT 0x00009200 |
| # define RADEON_CNTL_TRANBLT 0x00009C00 |
| |
| # define RADEON_CNTL_PAINT_POLYLINE 0x00009500 |
| # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
| |
| #define CP_PACKET0(reg, n) \ |
| (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
| |
| #define CP_PACKET1(reg0, reg1) \ |
| (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
| |
| #define CP_PACKET2() \ |
| (RADEON_CP_PACKET2) |
| |
| #define CP_PACKET3( pkt, n ) \ |
| (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
| |
| #define BEGIN_RING( n ) do { \ |
| ring = rhd.ring_base; \ |
| write = rhd.ring_wp; \ |
| } while (0) |
| |
| #define ADVANCE_RING() |
| |
| #define OUT_RING( x ) do { \ |
| ring[write++] = (x); \ |
| } while (0) |
| |
| #define OUT_RING_REG(reg, val) \ |
| do { \ |
| OUT_RING(CP_PACKET0(reg, 0)); \ |
| OUT_RING(val); \ |
| } while (0) |
| |
| #define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
| |
| #define COMMIT_RING() do { \ |
| rhd.ring_wp = write & 0x1FFF; \ |
| /* Flush writes to ring */ \ |
| DRM_MEMORYBARRIER(); \ |
| /*GET_RING_HEAD( dev_priv ); */ \ |
| OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
| /* read from PCI bus to ensure correct posting */ \ |
| INREG( RADEON_CP_RB_RPTR ); \ |
| } while (0) |
| |
| |
| |
| typedef struct { |
| int token; /* id of the token */ |
| const char * name; /* token name */ |