| 95,11 → 95,11 |
|---|
| CAPS_ALTMOVCR8 equ 74 ; |
| |
| ; CPU MSR names |
| MSR_SYSENTER_CS equ 0x174 |
| MSR_SYSENTER_ESP equ 0x175 |
| MSR_SYSENTER_EIP equ 0x176 |
| MSR_AMD_EFER equ 0xC0000080 ; Extended Feature Enable Register |
| MSR_AMD_STAR equ 0xC0000081 ; SYSCALL/SYSRET Target Address Register |
| MSR_SYSENTER_CS equ 0x174 |
| MSR_SYSENTER_ESP equ 0x175 |
| MSR_SYSENTER_EIP equ 0x176 |
| MSR_AMD_EFER equ 0xC0000080 ; Extended Feature Enable Register |
| MSR_AMD_STAR equ 0xC0000081 ; SYSCALL/SYSRET Target Address Register |
| |
| CR0_PE equ 0x00000001 ;protected mode |
| CR0_MP equ 0x00000002 ;monitor fpu |
| 468,9 → 468,10 |
|---|
| .id dd ? ;event uid |
| .state dd ? ;internal flags |
| .code dd ? |
| rd 5 |
| rd 6 |
| .size = $ - .magic |
| .codesize = $ - .code |
| } |
| EVENT_SIZE equ 52 |
| |
| virtual at 0 |
| EVENT EVENT |
| 687,4 → 688,3 |
|---|
| virtual at 0 |
| CSYM COFF_SYM |
| end virtual |
| |