| 172,18 → 172,7 |
|---|
| else |
| rbo->placements[i].lpfn = 0; |
| } |
| |
| /* |
| * Use two-ended allocation depending on the buffer size to |
| * improve fragmentation quality. |
| * 512kb was measured as the most optimal number. |
| */ |
| if (rbo->tbo.mem.size > 512 * 1024) { |
| for (i = 0; i < c; i++) { |
| rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; |
| } |
| } |
| } |
| |
| int radeon_bo_create(struct radeon_device *rdev, |
| unsigned long size, int byte_align, bool kernel, |
| 232,11 → 221,30 |
|---|
| if (!(rdev->flags & RADEON_IS_PCIE)) |
| bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
| |
| /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx |
| * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 |
| */ |
| if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) |
| bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
| |
| #ifdef CONFIG_X86_32 |
| /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit |
| * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 |
| */ |
| bo->flags &= ~RADEON_GEM_GTT_WC; |
| bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
| #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) |
| /* Don't try to enable write-combining when it can't work, or things |
| * may be slow |
| * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 |
| */ |
| |
| #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ |
| thanks to write-combining |
| |
| if (bo->flags & RADEON_GEM_GTT_WC) |
| DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " |
| "better performance thanks to write-combining\n"); |
| bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); |
| #endif |
| |
| radeon_ttm_placement_from_domain(bo, domain); |