42,6 → 42,12 |
void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
|
void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
|
|
/* |
* r100,rv100,rs100,rv200,rs200 |
*/ |
58,17 → 64,20 |
int r100_suspend(struct radeon_device *rdev); |
int r100_resume(struct radeon_device *rdev); |
void r100_vga_set_state(struct radeon_device *rdev, bool state); |
bool r100_gpu_is_lockup(struct radeon_device *rdev); |
bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
int r100_asic_reset(struct radeon_device *rdev); |
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
void r100_cp_commit(struct radeon_device *rdev); |
void r100_ring_start(struct radeon_device *rdev); |
void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
int r100_irq_set(struct radeon_device *rdev); |
int r100_irq_process(struct radeon_device *rdev); |
void r100_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
void r100_semaphore_ring_emit(struct radeon_device *rdev, |
struct radeon_ring *cp, |
struct radeon_semaphore *semaphore, |
bool emit_wait); |
int r100_cs_parse(struct radeon_cs_parser *p); |
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
75,8 → 84,8 |
int r100_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence); |
unsigned num_gpu_pages, |
struct radeon_fence **fence); |
int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
uint32_t tiling_flags, uint32_t pitch, |
uint32_t offset, uint32_t obj_size); |
83,7 → 92,7 |
void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
void r100_bandwidth_update(struct radeon_device *rdev); |
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int r100_ring_test(struct radeon_device *rdev); |
int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
void r100_hpd_init(struct radeon_device *rdev); |
void r100_hpd_fini(struct radeon_device *rdev); |
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
100,13 → 109,7 |
void r100_pci_gart_disable(struct radeon_device *rdev); |
int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
int r100_gui_wait_for_idle(struct radeon_device *rdev); |
void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, |
struct radeon_cp *cp); |
bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, |
struct r100_gpu_lockup *lockup, |
struct radeon_cp *cp); |
void r100_ib_fini(struct radeon_device *rdev); |
int r100_ib_init(struct radeon_device *rdev); |
int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
void r100_irq_disable(struct radeon_device *rdev); |
void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
136,6 → 139,8 |
extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); |
extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* r200,rv250,rs300,rv280 |
143,8 → 148,8 |
extern int r200_copy_dma(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence); |
unsigned num_gpu_pages, |
struct radeon_fence **fence); |
void r200_set_safe_registers(struct radeon_device *rdev); |
|
/* |
154,9 → 159,8 |
extern void r300_fini(struct radeon_device *rdev); |
extern int r300_suspend(struct radeon_device *rdev); |
extern int r300_resume(struct radeon_device *rdev); |
extern bool r300_gpu_is_lockup(struct radeon_device *rdev); |
extern int r300_asic_reset(struct radeon_device *rdev); |
extern void r300_ring_start(struct radeon_device *rdev); |
extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
extern void r300_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
extern int r300_cs_parse(struct radeon_cs_parser *p); |
173,6 → 177,7 |
extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* r420,r423,rv410 |
203,6 → 208,7 |
void rs400_gart_adjust_size(struct radeon_device *rdev); |
void rs400_gart_disable(struct radeon_device *rdev); |
void rs400_gart_fini(struct radeon_device *rdev); |
extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* rs600. |
233,8 → 239,9 |
extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); |
void rs600_set_safe_registers(struct radeon_device *rdev); |
extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
|
|
/* |
* rs690,rs740 |
*/ |
248,23 → 255,21 |
void rs690_line_buffer_adjust(struct radeon_device *rdev, |
struct drm_display_mode *mode1, |
struct drm_display_mode *mode2); |
extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* rv515 |
*/ |
struct rv515_mc_save { |
u32 d1vga_control; |
u32 d2vga_control; |
u32 vga_render_control; |
u32 vga_hdp_control; |
u32 d1crtc_control; |
u32 d2crtc_control; |
}; |
|
int rv515_init(struct radeon_device *rdev); |
void rv515_fini(struct radeon_device *rdev); |
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
void rv515_ring_start(struct radeon_device *rdev); |
void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
void rv515_bandwidth_update(struct radeon_device *rdev); |
int rv515_resume(struct radeon_device *rdev); |
int rv515_suspend(struct radeon_device *rdev); |
275,13 → 280,14 |
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
void rv515_clock_startup(struct radeon_device *rdev); |
void rv515_debugfs(struct radeon_device *rdev); |
int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
|
|
/* |
* r520,rv530,rv560,rv570,r580 |
*/ |
int r520_init(struct radeon_device *rdev); |
int r520_resume(struct radeon_device *rdev); |
int r520_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
293,7 → 299,6 |
void r600_vga_set_state(struct radeon_device *rdev, bool state); |
int r600_wb_init(struct radeon_device *rdev); |
void r600_wb_fini(struct radeon_device *rdev); |
void r600_cp_commit(struct radeon_device *rdev); |
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
300,18 → 305,22 |
int r600_cs_parse(struct radeon_cs_parser *p); |
void r600_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
bool r600_gpu_is_lockup(struct radeon_device *rdev); |
void r600_semaphore_ring_emit(struct radeon_device *rdev, |
struct radeon_ring *cp, |
struct radeon_semaphore *semaphore, |
bool emit_wait); |
bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
int r600_asic_reset(struct radeon_device *rdev); |
int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
uint32_t tiling_flags, uint32_t pitch, |
uint32_t offset, uint32_t obj_size); |
void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
int r600_ib_test(struct radeon_device *rdev); |
int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int r600_ring_test(struct radeon_device *rdev); |
int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
int r600_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, uint64_t dst_offset, |
unsigned num_pages, struct radeon_fence *fence); |
unsigned num_gpu_pages, struct radeon_fence **fence); |
void r600_hpd_init(struct radeon_device *rdev); |
void r600_hpd_fini(struct radeon_device *rdev); |
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
328,7 → 337,7 |
bool r600_card_posted(struct radeon_device *rdev); |
void r600_cp_stop(struct radeon_device *rdev); |
int r600_cp_start(struct radeon_device *rdev); |
void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
int r600_cp_resume(struct radeon_device *rdev); |
void r600_cp_fini(struct radeon_device *rdev); |
int r600_count_pipe_bits(uint32_t val); |
349,26 → 358,23 |
void r600_rlc_stop(struct radeon_device *rdev); |
/* r600 audio */ |
int r600_audio_init(struct radeon_device *rdev); |
int r600_audio_tmds_index(struct drm_encoder *encoder); |
void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
int r600_audio_channels(struct radeon_device *rdev); |
int r600_audio_bits_per_sample(struct radeon_device *rdev); |
int r600_audio_rate(struct radeon_device *rdev); |
uint8_t r600_audio_status_bits(struct radeon_device *rdev); |
uint8_t r600_audio_category_code(struct radeon_device *rdev); |
void r600_audio_schedule_polling(struct radeon_device *rdev); |
void r600_audio_enable_polling(struct drm_encoder *encoder); |
void r600_audio_disable_polling(struct drm_encoder *encoder); |
struct r600_audio r600_audio_status(struct radeon_device *rdev); |
void r600_audio_fini(struct radeon_device *rdev); |
void r600_hdmi_init(struct drm_encoder *encoder); |
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
/* r600 blit */ |
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
struct radeon_fence **fence, struct radeon_sa_bo **vb, |
struct radeon_semaphore **sem); |
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
void r600_kms_blit_copy(struct radeon_device *rdev, |
u64 src_gpu_addr, u64 dst_gpu_addr, |
int size_bytes); |
unsigned num_gpu_pages, |
struct radeon_sa_bo *vb); |
int r600_mc_wait_for_idle(struct radeon_device *rdev); |
uint64_t r600_get_gpu_clock(struct radeon_device *rdev); |
|
/* |
* rv770,rv730,rv710,rv740 |
387,23 → 393,20 |
* evergreen |
*/ |
struct evergreen_mc_save { |
u32 vga_control[6]; |
u32 vga_render_control; |
u32 vga_hdp_control; |
u32 crtc_control[6]; |
bool crtc_enabled[RADEON_MAX_CRTCS]; |
}; |
|
void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
int evergreen_init(struct radeon_device *rdev); |
void evergreen_fini(struct radeon_device *rdev); |
int evergreen_suspend(struct radeon_device *rdev); |
int evergreen_resume(struct radeon_device *rdev); |
bool evergreen_gpu_is_lockup(struct radeon_device *rdev); |
bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
int evergreen_asic_reset(struct radeon_device *rdev); |
void evergreen_bandwidth_update(struct radeon_device *rdev); |
void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int evergreen_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, uint64_t dst_offset, |
unsigned num_pages, struct radeon_fence *fence); |
void evergreen_hpd_init(struct radeon_device *rdev); |
void evergreen_hpd_fini(struct radeon_device *rdev); |
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
416,28 → 419,62 |
extern void evergreen_pm_misc(struct radeon_device *rdev); |
extern void evergreen_pm_prepare(struct radeon_device *rdev); |
extern void evergreen_pm_finish(struct radeon_device *rdev); |
extern void sumo_pm_init_profile(struct radeon_device *rdev); |
extern void btc_pm_init_profile(struct radeon_device *rdev); |
extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); |
extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
int evergreen_blit_init(struct radeon_device *rdev); |
void evergreen_blit_fini(struct radeon_device *rdev); |
/* evergreen blit */ |
int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
void evergreen_kms_blit_copy(struct radeon_device *rdev, |
u64 src_gpu_addr, u64 dst_gpu_addr, |
int size_bytes); |
int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
|
/* |
* cayman |
*/ |
void cayman_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
int cayman_init(struct radeon_device *rdev); |
void cayman_fini(struct radeon_device *rdev); |
int cayman_suspend(struct radeon_device *rdev); |
int cayman_resume(struct radeon_device *rdev); |
bool cayman_gpu_is_lockup(struct radeon_device *rdev); |
int cayman_asic_reset(struct radeon_device *rdev); |
void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int cayman_vm_init(struct radeon_device *rdev); |
void cayman_vm_fini(struct radeon_device *rdev); |
void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
uint64_t addr, unsigned count, |
uint32_t incr, uint32_t flags); |
int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
|
/* DCE6 - SI */ |
void dce6_bandwidth_update(struct radeon_device *rdev); |
|
/* |
* si |
*/ |
void si_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
void si_pcie_gart_tlb_flush(struct radeon_device *rdev); |
int si_init(struct radeon_device *rdev); |
void si_fini(struct radeon_device *rdev); |
int si_suspend(struct radeon_device *rdev); |
int si_resume(struct radeon_device *rdev); |
bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
int si_asic_reset(struct radeon_device *rdev); |
void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int si_irq_set(struct radeon_device *rdev); |
int si_irq_process(struct radeon_device *rdev); |
int si_vm_init(struct radeon_device *rdev); |
void si_vm_fini(struct radeon_device *rdev); |
void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
uint64_t addr, unsigned count, |
uint32_t incr, uint32_t flags); |
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
uint64_t si_get_gpu_clock(struct radeon_device *rdev); |
|
#endif |