| 24,10 → 24,12 |
|---|
| * Authors: Christian König |
| */ |
| #include <linux/hdmi.h> |
| #include <linux/gcd.h> |
| #include <drm/drmP.h> |
| #include <drm/radeon_drm.h> |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "radeon_audio.h" |
| #include "r600d.h" |
| #include "atom.h" |
| |
| 54,30 → 56,6 |
|---|
| AUDIO_STATUS_LEVEL = 0x80 |
| }; |
| |
| static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
| /* 32kHz 44.1kHz 48kHz */ |
| /* Clock N CTS N CTS N CTS */ |
| { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ |
| { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
| { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
| { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
| { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
| { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
| { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ |
| { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
| { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ |
| { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
| }; |
| |
| |
| /* |
| * check if the chipset is supported |
| */ |
| static int r600_audio_chipset_supported(struct radeon_device *rdev) |
| { |
| return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev); |
| } |
| |
| static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) |
| { |
| struct r600_audio_pin status; |
| 190,43 → 168,6 |
|---|
| WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
| } |
| |
| /* |
| * initialize the audio vars |
| */ |
| int r600_audio_init(struct radeon_device *rdev) |
| { |
| if (!radeon_audio || !r600_audio_chipset_supported(rdev)) |
| return 0; |
| |
| rdev->audio.enabled = true; |
| |
| rdev->audio.num_pins = 1; |
| rdev->audio.pin[0].channels = -1; |
| rdev->audio.pin[0].rate = -1; |
| rdev->audio.pin[0].bits_per_sample = -1; |
| rdev->audio.pin[0].status_bits = 0; |
| rdev->audio.pin[0].category_code = 0; |
| rdev->audio.pin[0].id = 0; |
| /* disable audio. it will be set up later */ |
| r600_audio_enable(rdev, &rdev->audio.pin[0], 0); |
| |
| return 0; |
| } |
| |
| /* |
| * release the audio timer |
| * TODO: How to do this correctly on SMP systems? |
| */ |
| void r600_audio_fini(struct radeon_device *rdev) |
| { |
| if (!rdev->audio.enabled) |
| return; |
| |
| r600_audio_enable(rdev, &rdev->audio.pin[0], 0); |
| |
| rdev->audio.enabled = false; |
| } |
| |
| struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) |
| { |
| /* only one pin on 6xx-NI */ |
| 233,96 → 174,40 |
|---|
| return &rdev->audio.pin[0]; |
| } |
| |
| /* |
| * calculate CTS and N values if they are not found in the table |
| */ |
| static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) |
| void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
| const struct radeon_hdmi_acr *acr) |
| { |
| int n, cts; |
| unsigned long div, mul; |
| |
| /* Safe, but overly large values */ |
| n = 128 * freq; |
| cts = clock * 1000; |
| |
| /* Smallest valid fraction */ |
| div = gcd(n, cts); |
| |
| n /= div; |
| cts /= div; |
| |
| /* |
| * The optimal N is 128*freq/1000. Calculate the closest larger |
| * value that doesn't truncate any bits. |
| */ |
| mul = ((128*freq/1000) + (n-1))/n; |
| |
| n *= mul; |
| cts *= mul; |
| |
| /* Check that we are in spec (not always possible) */ |
| if (n < (128*freq/1500)) |
| printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); |
| if (n > (128*freq/300)) |
| printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); |
| |
| *N = n; |
| *CTS = cts; |
| |
| DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", |
| *N, *CTS, freq); |
| } |
| |
| struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
| { |
| struct radeon_hdmi_acr res; |
| u8 i; |
| |
| /* Precalculated values for common clocks */ |
| for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { |
| if (r600_hdmi_predefined_acr[i].clock == clock) |
| return r600_hdmi_predefined_acr[i]; |
| } |
| |
| /* And odd clocks get manually calculated */ |
| r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); |
| r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); |
| r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); |
| |
| return res; |
| } |
| |
| /* |
| * update the N and CTS parameters for a given pixel clock rate |
| */ |
| void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| uint32_t offset = dig->afmt->offset; |
| |
| /* DCE 3.0 uses register that's normally for CRC_CONTROL */ |
| uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : |
| HDMI0_ACR_PACKET_CONTROL; |
| WREG32_P(acr_ctl + offset, |
| HDMI0_ACR_SOURCE | /* select SW CTS value */ |
| HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ |
| ~(HDMI0_ACR_SOURCE | |
| HDMI0_ACR_AUTO_SEND)); |
| |
| WREG32_P(HDMI0_ACR_32_0 + offset, |
| HDMI0_ACR_CTS_32(acr.cts_32khz), |
| HDMI0_ACR_CTS_32(acr->cts_32khz), |
| ~HDMI0_ACR_CTS_32_MASK); |
| WREG32_P(HDMI0_ACR_32_1 + offset, |
| HDMI0_ACR_N_32(acr.n_32khz), |
| HDMI0_ACR_N_32(acr->n_32khz), |
| ~HDMI0_ACR_N_32_MASK); |
| |
| WREG32_P(HDMI0_ACR_44_0 + offset, |
| HDMI0_ACR_CTS_44(acr.cts_44_1khz), |
| HDMI0_ACR_CTS_44(acr->cts_44_1khz), |
| ~HDMI0_ACR_CTS_44_MASK); |
| WREG32_P(HDMI0_ACR_44_1 + offset, |
| HDMI0_ACR_N_44(acr.n_44_1khz), |
| HDMI0_ACR_N_44(acr->n_44_1khz), |
| ~HDMI0_ACR_N_44_MASK); |
| |
| WREG32_P(HDMI0_ACR_48_0 + offset, |
| HDMI0_ACR_CTS_48(acr.cts_48khz), |
| HDMI0_ACR_CTS_48(acr->cts_48khz), |
| ~HDMI0_ACR_CTS_48_MASK); |
| WREG32_P(HDMI0_ACR_48_1 + offset, |
| HDMI0_ACR_N_48(acr.n_48khz), |
| HDMI0_ACR_N_48(acr->n_48khz), |
| ~HDMI0_ACR_N_48_MASK); |
| } |
| |
| 329,16 → 214,10 |
|---|
| /* |
| * build a HDMI Video Info Frame |
| */ |
| void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, |
| size_t size) |
| void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, |
| unsigned char *buffer, size_t size) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| uint32_t offset = dig->afmt->offset; |
| uint8_t *frame = buffer + 3; |
| uint8_t *header = buffer; |
| |
| WREG32(HDMI0_AVI_INFO0 + offset, |
| frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 347,7 → 226,15 |
|---|
| WREG32(HDMI0_AVI_INFO2 + offset, |
| frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
| WREG32(HDMI0_AVI_INFO3 + offset, |
| frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
| frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
| |
| WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, |
| HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */ |
| |
| WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
| HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
| HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */ |
| |
| } |
| |
| /* |
| 424,105 → 311,48 |
|---|
| value, ~HDMI0_AUDIO_TEST_EN); |
| } |
| |
| void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
| void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
| struct radeon_crtc *crtc, unsigned int clock) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| u32 base_rate = 24000; |
| u32 max_ratio = clock / base_rate; |
| u32 dto_phase; |
| u32 dto_modulo = clock; |
| u32 wallclock_ratio; |
| u32 dto_cntl; |
| struct radeon_encoder *radeon_encoder; |
| struct radeon_encoder_atom_dig *dig; |
| |
| if (!dig || !dig->afmt) |
| if (!crtc) |
| return; |
| |
| if (max_ratio >= 8) { |
| dto_phase = 192 * 1000; |
| wallclock_ratio = 3; |
| } else if (max_ratio >= 4) { |
| dto_phase = 96 * 1000; |
| wallclock_ratio = 2; |
| } else if (max_ratio >= 2) { |
| dto_phase = 48 * 1000; |
| wallclock_ratio = 1; |
| } else { |
| dto_phase = 24 * 1000; |
| wallclock_ratio = 0; |
| } |
| radeon_encoder = to_radeon_encoder(crtc->encoder); |
| dig = radeon_encoder->enc_priv; |
| |
| /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
| * doesn't matter which one you use. Just use the first one. |
| */ |
| /* XXX two dtos; generally use dto0 for hdmi */ |
| /* Express [24MHz / target pixel clock] as an exact rational |
| * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| */ |
| if (ASIC_IS_DCE32(rdev)) { |
| if (!dig) |
| return; |
| |
| if (dig->dig_encoder == 0) { |
| dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
| dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
| WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
| WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
| WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
| WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
| } else { |
| dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
| dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
| WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); |
| WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); |
| WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); |
| WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
| } |
| } else { |
| /* according to the reg specs, this should DCE3.2 only, but in |
| * practice it seems to cover DCE2.0/3.0/3.1 as well. |
| */ |
| if (dig->dig_encoder == 0) { |
| WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
| WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); |
| WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
| WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
| } else { |
| WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); |
| WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); |
| WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); |
| WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
| } |
| } |
| } |
| |
| /* |
| * update the info frames with the data from the current display mode |
| */ |
| void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
| struct hdmi_avi_infoframe frame; |
| uint32_t offset; |
| uint32_t acr_ctl; |
| ssize_t err; |
| |
| if (!dig || !dig->afmt) |
| return; |
| WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, |
| HDMI0_NULL_SEND | /* send null packets when required */ |
| HDMI0_GC_SEND | /* send general control packets */ |
| HDMI0_GC_CONT); /* send general control packets every frame */ |
| } |
| |
| /* Silent, r600_hdmi_enable will raise WARN for us */ |
| if (!dig->afmt->enabled) |
| return; |
| offset = dig->afmt->offset; |
| void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| |
| /* disable audio prior to setting up hw */ |
| dig->afmt->pin = r600_audio_get_pin(rdev); |
| r600_audio_enable(rdev, dig->afmt->pin, 0xf); |
| |
| r600_audio_set_dto(encoder, mode->clock); |
| |
| WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
| 533,51 → 363,14 |
|---|
| HDMI0_AUDIO_PACKETS_PER_LINE_MASK | |
| HDMI0_60958_CS_UPDATE)); |
| |
| /* DCE 3.0 uses register that's normally for CRC_CONTROL */ |
| acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : |
| HDMI0_ACR_PACKET_CONTROL; |
| WREG32_P(acr_ctl + offset, |
| HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ |
| HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ |
| ~(HDMI0_ACR_SOURCE | |
| HDMI0_ACR_AUTO_SEND)); |
| |
| WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, |
| HDMI0_NULL_SEND | /* send null packets when required */ |
| HDMI0_GC_SEND | /* send general control packets */ |
| HDMI0_GC_CONT); /* send general control packets every frame */ |
| |
| WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
| HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
| HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
| HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
| |
| WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, |
| HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
| HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ |
| ~(HDMI0_AVI_INFO_LINE_MASK | |
| HDMI0_AUDIO_INFO_LINE_MASK)); |
| ~HDMI0_AUDIO_INFO_LINE_MASK); |
| |
| WREG32_AND(HDMI0_GC + offset, |
| ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */ |
| |
| err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| if (err < 0) { |
| DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
| return; |
| } |
| |
| err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| if (err < 0) { |
| DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
| return; |
| } |
| |
| r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
| |
| /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */ |
| |
| WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, |
| ~(HDMI0_GENERIC0_SEND | |
| HDMI0_GENERIC0_CONT | |
| 587,8 → 380,6 |
|---|
| HDMI0_GENERIC0_LINE_MASK | |
| HDMI0_GENERIC1_LINE_MASK)); |
| |
| r600_hdmi_update_ACR(encoder, mode->clock); |
| |
| WREG32_P(HDMI0_60958_0 + offset, |
| HDMI0_60958_CS_CHANNEL_NUMBER_L(1), |
| ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | |
| 597,15 → 388,17 |
|---|
| WREG32_P(HDMI0_60958_1 + offset, |
| HDMI0_60958_CS_CHANNEL_NUMBER_R(2), |
| ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); |
| } |
| |
| /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
| WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
| WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
| WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
| WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
| void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| |
| /* enable audio after to setting up hw */ |
| r600_audio_enable(rdev, dig->afmt->pin, 0xf); |
| if (mute) |
| WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); |
| else |
| WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); |
| } |
| |
| /** |
| 684,17 → 477,6 |
|---|
| if (!dig || !dig->afmt) |
| return; |
| |
| /* Silent, r600_hdmi_enable will raise WARN for us */ |
| if (enable && dig->afmt->enabled) |
| return; |
| if (!enable && !dig->afmt->enabled) |
| return; |
| |
| if (!enable && dig->afmt->pin) { |
| r600_audio_enable(rdev, dig->afmt->pin, 0); |
| dig->afmt->pin = NULL; |
| } |
| |
| /* Older chipsets require setting HDMI and routing manually */ |
| if (!ASIC_IS_DCE3(rdev)) { |
| if (enable) |