| 25,9 → 25,8 |
|---|
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #include "drmP.h" |
| #include "drm.h" |
| #include "radeon_drm.h" |
| #include <drm/drmP.h> |
| #include <drm/radeon_drm.h> |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| 87,9 → 86,10 |
|---|
| int r200_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence) |
| unsigned num_gpu_pages, |
| struct radeon_fence **fence) |
| { |
| struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| uint32_t size; |
| uint32_t cur_size; |
| int i, num_loops; |
| 96,16 → 96,16 |
|---|
| int r = 0; |
| |
| /* radeon pitch is /64 */ |
| size = num_pages << PAGE_SHIFT; |
| size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; |
| num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
| r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
| r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64); |
| if (r) { |
| DRM_ERROR("radeon: moving bo (%d).\n", r); |
| return r; |
| } |
| /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
| radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(rdev, (1 << 16)); |
| radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(ring, (1 << 16)); |
| for (i = 0; i < num_loops; i++) { |
| cur_size = size; |
| if (cur_size > 0x1FFFFF) { |
| 112,19 → 112,19 |
|---|
| cur_size = 0x1FFFFF; |
| } |
| size -= cur_size; |
| radeon_ring_write(rdev, PACKET0(0x720, 2)); |
| radeon_ring_write(rdev, src_offset); |
| radeon_ring_write(rdev, dst_offset); |
| radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
| radeon_ring_write(ring, PACKET0(0x720, 2)); |
| radeon_ring_write(ring, src_offset); |
| radeon_ring_write(ring, dst_offset); |
| radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); |
| src_offset += cur_size; |
| dst_offset += cur_size; |
| } |
| radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
| radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); |
| if (fence) { |
| r = radeon_fence_emit(rdev, fence); |
| r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
| } |
| radeon_ring_unlock_commit(rdev); |
| radeon_ring_unlock_commit(rdev, ring); |
| return r; |
| } |
| #if 0 |
| 156,7 → 156,7 |
|---|
| u32 tile_flags = 0; |
| u32 idx_value; |
| |
| ib = p->ib->ptr; |
| ib = p->ib.ptr; |
| track = (struct r100_cs_track *)p->track; |
| idx_value = radeon_get_ib_value(p, idx); |
| switch (reg) { |
| 217,6 → 217,16 |
|---|
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| tile_flags |= R200_TXO_MACRO_TILE; |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= R200_TXO_MICRO_TILE; |
| |
| tmp = idx_value & ~(0x7 << 2); |
| tmp |= tile_flags; |
| ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
| } else |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].robj = reloc->robj; |
| track->tex_dirty = true; |
| 279,6 → 289,7 |
|---|
| return r; |
| } |
| |
| if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| tile_flags |= RADEON_COLOR_TILE_ENABLE; |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 287,6 → 298,8 |
|---|
| tmp = idx_value & ~(0x7 << 16); |
| tmp |= tile_flags; |
| ib[idx] = tmp; |
| } else |
| ib[idx] = idx_value; |
| |
| track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
| track->cb_dirty = true; |