3862,11 → 3862,13 |
ni_update_current_ps(rdev, new_ps); |
} |
|
#if 0 |
void ni_dpm_reset_asic(struct radeon_device *rdev) |
{ |
ni_restrict_performance_levels_before_switch(rdev); |
rv770_set_boot_state(rdev); |
} |
#endif |
|
union power_info { |
struct _ATOM_POWERPLAY_INFO info; |
4317,6 → 4319,42 |
} |
} |
|
u32 ni_dpm_get_current_sclk(struct radeon_device *rdev) |
{ |
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
struct radeon_ps *rps = &eg_pi->current_rps; |
struct ni_ps *ps = ni_get_ps(rps); |
struct rv7xx_pl *pl; |
u32 current_index = |
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
CURRENT_STATE_INDEX_SHIFT; |
|
if (current_index >= ps->performance_level_count) { |
return 0; |
} else { |
pl = &ps->performance_levels[current_index]; |
return pl->sclk; |
} |
} |
|
u32 ni_dpm_get_current_mclk(struct radeon_device *rdev) |
{ |
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
struct radeon_ps *rps = &eg_pi->current_rps; |
struct ni_ps *ps = ni_get_ps(rps); |
struct rv7xx_pl *pl; |
u32 current_index = |
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
CURRENT_STATE_INDEX_SHIFT; |
|
if (current_index >= ps->performance_level_count) { |
return 0; |
} else { |
pl = &ps->performance_levels[current_index]; |
return pl->mclk; |
} |
} |
|
u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) |
{ |
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |