1739,6 → 1739,7 |
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct drm_crtc *test_crtc; |
struct radeon_crtc *test_radeon_crtc; |
|
1748,6 → 1749,10 |
test_radeon_crtc = to_radeon_crtc(test_crtc); |
if (test_radeon_crtc->encoder && |
ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
/* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
test_radeon_crtc->pll_id == ATOM_PPLL2) |
continue; |
/* for DP use the same PLL for all */ |
if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
return test_radeon_crtc->pll_id; |
1769,6 → 1774,7 |
{ |
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
struct drm_device *dev = crtc->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct drm_crtc *test_crtc; |
struct radeon_crtc *test_radeon_crtc; |
u32 adjusted_clock, test_adjusted_clock; |
1784,6 → 1790,10 |
test_radeon_crtc = to_radeon_crtc(test_crtc); |
if (test_radeon_crtc->encoder && |
!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
/* PPLL2 is exclusive to UNIPHYA on DCE61 */ |
if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && |
test_radeon_crtc->pll_id == ATOM_PPLL2) |
continue; |
/* check if we are already driving this connector with another crtc */ |
if (test_radeon_crtc->connector == radeon_crtc->connector) { |
/* if we are, return that pll */ |