| 51,15 → 51,14 |
|---|
| u32 adpa_reg; |
| }; |
| |
| static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
| { |
| return container_of(intel_attached_encoder(connector), |
| struct intel_crt, base); |
| return container_of(encoder, struct intel_crt, base); |
| } |
| |
| static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
| static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| { |
| return container_of(encoder, struct intel_crt, base); |
| return intel_encoder_to_crt(intel_attached_encoder(connector)); |
| } |
| |
| static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
| 83,6 → 82,28 |
|---|
| return true; |
| } |
| |
| static void intel_crt_get_config(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config) |
| { |
| struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| u32 tmp, flags = 0; |
| |
| tmp = I915_READ(crt->adpa_reg); |
| |
| if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
| flags |= DRM_MODE_FLAG_PHSYNC; |
| else |
| flags |= DRM_MODE_FLAG_NHSYNC; |
| |
| if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
| flags |= DRM_MODE_FLAG_PVSYNC; |
| else |
| flags |= DRM_MODE_FLAG_NVSYNC; |
| |
| pipe_config->adjusted_mode.flags |= flags; |
| } |
| |
| /* Note: The caller is required to filter out dpms modes not supported by the |
| * platform. */ |
| static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
| 126,7 → 147,7 |
|---|
| intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
| } |
| |
| |
| /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
| static void intel_crt_dpms(struct drm_connector *connector, int mode) |
| { |
| struct drm_device *dev = connector->dev; |
| 157,6 → 178,8 |
|---|
| else |
| encoder->connectors_active = true; |
| |
| /* We call connector dpms manually below in case pipe dpms doesn't |
| * change due to cloning. */ |
| if (mode < old_dpms) { |
| /* From off to on, enable the pipe first. */ |
| intel_crtc_update_dpms(crtc); |
| 206,20 → 229,21 |
|---|
| if (HAS_PCH_SPLIT(dev)) |
| pipe_config->has_pch_encoder = true; |
| |
| /* LPT FDI RX only supports 8bpc. */ |
| if (HAS_PCH_LPT(dev)) |
| pipe_config->pipe_bpp = 24; |
| |
| return true; |
| } |
| |
| static void intel_crt_mode_set(struct drm_encoder *encoder, |
| struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode) |
| static void intel_crt_mode_set(struct intel_encoder *encoder) |
| { |
| |
| struct drm_device *dev = encoder->dev; |
| struct drm_crtc *crtc = encoder->crtc; |
| struct intel_crt *crt = |
| intel_encoder_to_crt(to_intel_encoder(encoder)); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| struct drm_device *dev = encoder->base.dev; |
| struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
| u32 adpa; |
| |
| if (HAS_PCH_SPLIT(dev)) |
| 236,14 → 260,14 |
|---|
| if (HAS_PCH_LPT(dev)) |
| ; /* Those bits don't exist here */ |
| else if (HAS_PCH_CPT(dev)) |
| adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| else if (intel_crtc->pipe == 0) |
| adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
| else if (crtc->pipe == 0) |
| adpa |= ADPA_PIPE_A_SELECT; |
| else |
| adpa |= ADPA_PIPE_B_SELECT; |
| |
| if (!HAS_PCH_SPLIT(dev)) |
| I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); |
| I915_WRITE(BCLRPAT(crtc->pipe), 0); |
| |
| I915_WRITE(crt->adpa_reg, adpa); |
| } |
| 430,7 → 454,7 |
|---|
| |
| BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
| |
| i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
| i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
| edid = intel_crt_get_edid(connector, i2c); |
| |
| if (edid) { |
| 584,6 → 608,10 |
|---|
| enum drm_connector_status status; |
| struct intel_load_detect_pipe tmp; |
| |
| DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
| connector->base.id, drm_get_connector_name(connector), |
| force); |
| |
| if (I915_HAS_HOTPLUG(dev)) { |
| /* We can not rely on the HPD pin always being correctly wired |
| * up, for example many KVM do not pass it through, and so |
| 636,7 → 664,7 |
|---|
| int ret; |
| struct i2c_adapter *i2c; |
| |
| i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
| i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
| ret = intel_crt_ddc_get_modes(connector, i2c); |
| if (ret || !IS_G4X(dev)) |
| return ret; |
| 659,7 → 687,7 |
|---|
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_crt *crt = intel_attached_crt(connector); |
| |
| if (HAS_PCH_SPLIT(dev)) { |
| if (INTEL_INFO(dev)->gen >= 5) { |
| u32 adpa; |
| |
| adpa = I915_READ(crt->adpa_reg); |
| 678,10 → 706,6 |
|---|
| * Routines for controlling stuff on the analog port |
| */ |
| |
| static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
| .mode_set = intel_crt_mode_set, |
| }; |
| |
| static const struct drm_connector_funcs intel_crt_connector_funcs = { |
| .reset = intel_crt_reset, |
| .dpms = intel_crt_dpms, |
| 749,8 → 773,10 |
|---|
| crt->adpa_reg = ADPA; |
| |
| crt->base.compute_config = intel_crt_compute_config; |
| crt->base.mode_set = intel_crt_mode_set; |
| crt->base.disable = intel_disable_crt; |
| crt->base.enable = intel_enable_crt; |
| crt->base.get_config = intel_crt_get_config; |
| if (I915_HAS_HOTPLUG(dev)) |
| crt->base.hpd_pin = HPD_CRT; |
| if (HAS_DDI(dev)) |
| 759,7 → 785,6 |
|---|
| crt->base.get_hw_state = intel_crt_get_hw_state; |
| intel_connector->get_hw_state = intel_connector_get_hw_state; |
| |
| drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
| drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| |
| drm_sysfs_connector_add(connector); |