1657,11 → 1657,11 |
for_each_pipe(dev_priv, pipe) { |
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
intel_pipe_handle_vblank(dev, pipe)) |
/*intel_check_page_flip(dev, pipe)*/; |
intel_check_page_flip(dev, pipe); |
|
if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
// intel_prepare_page_flip(dev, pipe); |
// intel_finish_page_flip(dev, pipe); |
intel_prepare_page_flip(dev, pipe); |
intel_finish_page_flip(dev, pipe); |
} |
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
2028,7 → 2028,7 |
for_each_pipe(dev_priv, pipe) { |
if (de_iir & DE_PIPE_VBLANK(pipe) && |
intel_pipe_handle_vblank(dev, pipe)) |
/*intel_check_page_flip(dev, pipe)*/; |
intel_check_page_flip(dev, pipe); |
|
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
2038,8 → 2038,8 |
|
/* plane/pipes map 1:1 on ilk+ */ |
if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { |
// intel_prepare_page_flip(dev, pipe); |
// intel_finish_page_flip_plane(dev, pipe); |
intel_prepare_page_flip(dev, pipe); |
intel_finish_page_flip_plane(dev, pipe); |
} |
} |
|
2081,12 → 2081,12 |
for_each_pipe(dev_priv, pipe) { |
if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
intel_pipe_handle_vblank(dev, pipe)) |
/*intel_check_page_flip(dev, pipe)*/; |
intel_check_page_flip(dev, pipe); |
|
/* plane/pipes map 1:1 on ilk+ */ |
if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
// intel_prepare_page_flip(dev, pipe); |
// intel_finish_page_flip_plane(dev, pipe); |
intel_prepare_page_flip(dev, pipe); |
intel_finish_page_flip_plane(dev, pipe); |
} |
} |
|
2290,7 → 2290,7 |
|
if (pipe_iir & GEN8_PIPE_VBLANK && |
intel_pipe_handle_vblank(dev, pipe)) |
/* intel_check_page_flip(dev, pipe)*/; |
intel_check_page_flip(dev, pipe); |
|
if (INTEL_INFO(dev_priv)->gen >= 9) |
flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; |
2297,6 → 2297,10 |
else |
flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; |
|
if (flip_done) { |
intel_prepare_page_flip(dev, pipe); |
intel_finish_page_flip_plane(dev, pipe); |
} |
|
if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
hsw_pipe_crc_irq_handler(dev, pipe); |
2335,10 → 2339,14 |
spt_irq_handler(dev, pch_iir); |
else |
cpt_irq_handler(dev, pch_iir); |
} else |
DRM_ERROR("The master control interrupt lied (SDE)!\n"); |
|
} else { |
/* |
* Like on previous PCH there seems to be something |
* fishy going on with forwarding PCH interrupts. |
*/ |
DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); |
} |
} |
|
I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
POSTING_READ_FW(GEN8_MASTER_IRQ); |
2363,6 → 2371,8 |
for_each_ring(ring, dev_priv, i) |
wake_up_all(&ring->irq_queue); |
|
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ |
wake_up_all(&dev_priv->pending_flip_queue); |
|
/* |
* Signal tasks blocked in i915_gem_wait_for_error that the pending |
3775,12 → 3785,12 |
if (I915_READ16(ISR) & flip_pending) |
goto check_page_flip; |
|
// intel_prepare_page_flip(dev, plane); |
// intel_finish_page_flip(dev, pipe); |
intel_prepare_page_flip(dev, plane); |
intel_finish_page_flip(dev, pipe); |
return true; |
|
check_page_flip: |
// intel_check_page_flip(dev, pipe); |
intel_check_page_flip(dev, pipe); |
return false; |
} |
|
3959,9 → 3969,12 |
if (I915_READ(ISR) & flip_pending) |
goto check_page_flip; |
|
intel_prepare_page_flip(dev, plane); |
intel_finish_page_flip(dev, pipe); |
return true; |
|
check_page_flip: |
intel_check_page_flip(dev, pipe); |
return false; |
} |
|
4449,7 → 4462,7 |
void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
{ |
// drm_irq_uninstall(dev_priv->dev); |
// intel_hpd_cancel_work(dev_priv); |
intel_hpd_cancel_work(dev_priv); |
dev_priv->pm.irqs_enabled = false; |
} |
|