| 343,6 → 343,8 |
|---|
| int lane); |
| |
| #define DP_RECEIVER_CAP_SIZE 0xf |
| #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
| |
| void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| |
| 349,6 → 351,33 |
|---|
| u8 drm_dp_link_rate_to_bw_code(int link_rate); |
| int drm_dp_bw_code_to_link_rate(u8 link_bw); |
| |
| struct edp_sdp_header { |
| u8 HB0; /* Secondary Data Packet ID */ |
| u8 HB1; /* Secondary Data Packet Type */ |
| u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
| u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
| } __packed; |
| |
| #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
| #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
| |
| struct edp_vsc_psr { |
| struct edp_sdp_header sdp_header; |
| u8 DB0; /* Stereo Interface */ |
| u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
| u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
| u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
| u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
| u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
| u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
| u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
| u8 DB8_31[24]; /* Reserved */ |
| } __packed; |
| |
| #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
| #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
| #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
| |
| static inline int |
| drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |