/drivers/ddk/linux/dmapool.c |
---|
24,7 → 24,9 |
#include <ddk.h> |
#include <linux/errno.h> |
#include <linux/mutex.h> |
#include <pci.h> |
#include <syscall.h> |
/drivers/devman/Makefile |
---|
1,4 → 1,7 |
CC = gcc |
FASM = e:/fasm/fasm.exe |
28,6 → 31,7 |
scan.c \ |
pci_irq.c \ |
pci_root.c \ |
pci/access.c \ |
pci/pci.c \ |
pci/probe.c \ |
pci_bind.c |
/drivers/devman/acpi_bus.h |
---|
33,12 → 33,6 |
acpi_op_notify notify; |
}; |
struct resource_list { |
struct resource_list *next; |
struct resource *res; |
// struct pci_dev *dev; |
}; |
enum acpi_bus_device_type { |
ACPI_BUS_TYPE_DEVICE = 0, |
ACPI_BUS_TYPE_POWER, |
/drivers/devman/acpica/libacpica.a |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Deleted: svn:mime-type |
-application/octet-stream |
\ No newline at end of property |
/drivers/devman/acpica/Makefile |
---|
1,5 → 1,4 |
CC = gcc |
DRV_DIR = $(CURDIR)/../.. |
/drivers/devman/acpica/include/platform/ackolibri.h |
---|
116,9 → 116,14 |
#include "acgcc.h" |
#include <linux\types.h> |
#include <linux\mutex.h> |
#include <linux/string.h> |
#include <linux/kernel.h> |
#include <linux/module.h> |
#include <asm/atomic.h> |
#include <linux/errno.h> |
#include <ddk.h> |
#include <linux/pci.h> |
#include <syscall.h> |
#define ACPI_MACHINE_WIDTH 32 |
/drivers/devman/pci/access.c |
---|
0,0 → 1,89 |
#include <ddk.h> |
#include <linux/errno.h> |
#include <mutex.h> |
#include <pci.h> |
#include <syscall.h> |
int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) |
{ |
*val = PciRead8(dev->busnr, dev->devfn, where); |
return 0; |
} |
int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) |
{ |
if ( where & 1) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
*val = PciRead16(dev->busnr, dev->devfn, where); |
return 0; |
} |
int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val) |
{ |
if ( where & 3) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
*val = PciRead32(dev->busnr, dev->devfn, where); |
return 0; |
} |
int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) |
{ |
PciWrite8(dev->busnr, dev->devfn, where, val); |
return 0; |
}; |
int pci_write_config_word(struct pci_dev *dev, int where, u16 val) |
{ |
if ( where & 1) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
PciWrite16(dev->busnr, dev->devfn, where, val); |
return 0; |
} |
int pci_write_config_dword(struct pci_dev *dev, int where, |
u32 val) |
{ |
if ( where & 3) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
PciWrite32(dev->busnr, dev->devfn, where, val); |
return 0; |
} |
int pci_bus_read_config_byte (struct pci_bus *bus, u32 devfn, |
int pos, u8 *value) |
{ |
// raw_spin_lock_irqsave(&pci_lock, flags); |
*value = PciRead8(bus->number, devfn, pos); |
// raw_spin_unlock_irqrestore(&pci_lock, flags); |
return 0; |
} |
int pci_bus_read_config_word (struct pci_bus *bus, u32 devfn, |
int pos, u16 *value) |
{ |
if ( pos & 1) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
// raw_spin_lock_irqsave(&pci_lock, flags); |
*value = PciRead16(bus->number, devfn, pos); |
// raw_spin_unlock_irqrestore(&pci_lock, flags); |
return 0; |
} |
int pci_bus_read_config_dword (struct pci_bus *bus, u32 devfn, |
int pos, u16 *value) |
{ |
if ( pos & 3) |
return PCIBIOS_BAD_REGISTER_NUMBER; |
// raw_spin_lock_irqsave(&pci_lock, flags); |
*value = PciRead32(bus->number, devfn, pos); |
// raw_spin_unlock_irqrestore(&pci_lock, flags); |
return 0; |
} |
/drivers/devman/pci/pci.c |
---|
5,7 → 5,6 |
#include <pci.h> |
#include <syscall.h> |
LIST_HEAD(pci_root_buses); |
#define IO_SPACE_LIMIT 0xffff |
#define PCIBIOS_SUCCESSFUL 0x00 |
108,59 → 107,6 |
} |
static struct pci_bus * pci_alloc_bus(void) |
{ |
struct pci_bus *b; |
b = kzalloc(sizeof(*b), GFP_KERNEL); |
if (b) { |
INIT_LIST_HEAD(&b->node); |
INIT_LIST_HEAD(&b->children); |
INIT_LIST_HEAD(&b->devices); |
INIT_LIST_HEAD(&b->slots); |
INIT_LIST_HEAD(&b->resources); |
} |
return b; |
} |
struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata) |
{ |
int error; |
struct pci_bus *b, *b2; |
b = pci_alloc_bus(); |
if (!b) |
return NULL; |
b->sysdata = sysdata; |
b->ops = ops; |
b2 = pci_find_bus(pci_domain_nr(b), bus); |
if (b2) { |
/* If we already got to this bus through a different bridge, ignore it */ |
dbgprintf("bus already known\n"); |
goto err_out; |
} |
// down_write(&pci_bus_sem); |
list_add_tail(&b->node, &pci_root_buses); |
// up_write(&pci_bus_sem); |
b->number = b->secondary = bus; |
b->resource[0] = &ioport_resource; |
b->resource[1] = &iomem_resource; |
return b; |
err_out: |
kfree(b); |
return NULL; |
} |
static struct pci_bus *pci_do_find_bus(struct pci_bus *bus, unsigned char busnr) |
{ |
struct pci_bus* child; |
316,3 → 262,60 |
return 0; |
} |
#if 0 |
u32 pci_probe = 0; |
#define PCI_NOASSIGN_ROMS 0x80000 |
#define PCI_NOASSIGN_BARS 0x200000 |
static void pcibios_fixup_device_resources(struct pci_dev *dev) |
{ |
struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE]; |
struct resource *bar_r; |
int bar; |
if (pci_probe & PCI_NOASSIGN_BARS) { |
/* |
* If the BIOS did not assign the BAR, zero out the |
* resource so the kernel doesn't attmept to assign |
* it later on in pci_assign_unassigned_resources |
*/ |
for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) { |
bar_r = &dev->resource[bar]; |
if (bar_r->start == 0 && bar_r->end != 0) { |
bar_r->flags = 0; |
bar_r->end = 0; |
} |
} |
} |
if (pci_probe & PCI_NOASSIGN_ROMS) { |
if (rom_r->parent) |
return; |
if (rom_r->start) { |
/* we deal with BIOS assigned ROM later */ |
return; |
} |
rom_r->start = rom_r->end = rom_r->flags = 0; |
} |
} |
/* |
* Called after each bus is probed, but before its children |
* are examined. |
*/ |
void pcibios_fixup_bus(struct pci_bus *b) |
{ |
struct pci_dev *dev; |
/* root bus? */ |
// if (!b->parent) |
// x86_pci_root_bus_res_quirks(b); |
pci_read_bridge_bases(b); |
list_for_each_entry(dev, &b->devices, bus_list) |
pcibios_fixup_device_resources(dev); |
} |
#endif |
/drivers/devman/pci/probe.c |
---|
5,10 → 5,709 |
#include <pci.h> |
#include <syscall.h> |
LIST_HEAD(pci_root_buses); |
#define IO_SPACE_LIMIT 0xffff |
#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
#define CARDBUS_RESERVE_BUSNR 3 |
static int pcibios_assign_all_busses(void) |
{ |
return 0; |
}; |
/** |
* pci_ari_enabled - query ARI forwarding status |
* @bus: the PCI bus |
* |
* Returns 1 if ARI forwarding is enabled, or 0 if not enabled; |
*/ |
static inline int pci_ari_enabled(struct pci_bus *bus) |
{ |
return bus->self && bus->self->ari_enabled; |
} |
/* |
* Translate the low bits of the PCI base |
* to the resource type |
*/ |
static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
{ |
if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
return IORESOURCE_IO; |
if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
return IORESOURCE_MEM; |
} |
static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
{ |
u64 size = mask & maxbase; /* Find the significant bits */ |
if (!size) |
return 0; |
/* Get the lowest of them to find the decode size, and |
from that the extent. */ |
size = (size & ~(size-1)) - 1; |
/* base == maxbase can be valid only if the BAR has |
already been programmed with all 1s. */ |
if (base == maxbase && ((base | size) & mask) != mask) |
return 0; |
return size; |
} |
static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
{ |
if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
return pci_bar_io; |
} |
res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
return pci_bar_mem64; |
return pci_bar_mem32; |
} |
/** |
* pci_read_base - read a PCI BAR |
* @dev: the PCI device |
* @type: type of the BAR |
* @res: resource buffer to be filled in |
* @pos: BAR position in the config space |
* |
* Returns 1 if the BAR is 64-bit, or 0 if 32-bit. |
*/ |
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
struct resource *res, unsigned int pos) |
{ |
u32 l, sz, mask; |
u16 orig_cmd; |
mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
if (!dev->mmio_always_on) { |
pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); |
pci_write_config_word(dev, PCI_COMMAND, |
orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
} |
res->name = pci_name(dev); |
pci_read_config_dword(dev, pos, &l); |
pci_write_config_dword(dev, pos, l | mask); |
pci_read_config_dword(dev, pos, &sz); |
pci_write_config_dword(dev, pos, l); |
if (!dev->mmio_always_on) |
pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
/* |
* All bits set in sz means the device isn't working properly. |
* If the BAR isn't implemented, all bits must be 0. If it's a |
* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit |
* 1 must be clear. |
*/ |
if (!sz || sz == 0xffffffff) |
goto fail; |
/* |
* I don't know how l can have all bits set. Copied from old code. |
* Maybe it fixes a bug on some ancient platform. |
*/ |
if (l == 0xffffffff) |
l = 0; |
if (type == pci_bar_unknown) { |
type = decode_bar(res, l); |
res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
if (type == pci_bar_io) { |
l &= PCI_BASE_ADDRESS_IO_MASK; |
mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
} else { |
l &= PCI_BASE_ADDRESS_MEM_MASK; |
mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
} |
} else { |
res->flags |= (l & IORESOURCE_ROM_ENABLE); |
l &= PCI_ROM_ADDRESS_MASK; |
mask = (u32)PCI_ROM_ADDRESS_MASK; |
} |
if (type == pci_bar_mem64) { |
u64 l64 = l; |
u64 sz64 = sz; |
u64 mask64 = mask | (u64)~0 << 32; |
pci_read_config_dword(dev, pos + 4, &l); |
pci_write_config_dword(dev, pos + 4, ~0); |
pci_read_config_dword(dev, pos + 4, &sz); |
pci_write_config_dword(dev, pos + 4, l); |
l64 |= ((u64)l << 32); |
sz64 |= ((u64)sz << 32); |
sz64 = pci_size(l64, sz64, mask64); |
if (!sz64) |
goto fail; |
if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
dbgprintf("%s reg %x: can't handle 64-bit BAR\n", |
__FUNCTION__, pos); |
goto fail; |
} |
res->flags |= IORESOURCE_MEM_64; |
if ((sizeof(resource_size_t) < 8) && l) { |
/* Address above 32-bit boundary; disable the BAR */ |
pci_write_config_dword(dev, pos, 0); |
pci_write_config_dword(dev, pos + 4, 0); |
res->start = 0; |
res->end = sz64; |
} else { |
res->start = l64; |
res->end = l64 + sz64; |
dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res); |
} |
} else { |
sz = pci_size(l, sz, mask); |
if (!sz) |
goto fail; |
res->start = l; |
res->end = l + sz; |
dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res); |
} |
out: |
return (type == pci_bar_mem64) ? 1 : 0; |
fail: |
res->flags = 0; |
goto out; |
} |
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
{ |
unsigned int pos, reg; |
for (pos = 0; pos < howmany; pos++) { |
struct resource *res = &dev->resource[pos]; |
reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
} |
if (rom) { |
struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
dev->rom_base_reg = rom; |
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
IORESOURCE_READONLY | IORESOURCE_CACHEABLE | |
IORESOURCE_SIZEALIGN; |
__pci_read_base(dev, pci_bar_mem32, res, rom); |
} |
} |
#if 0 |
void pci_read_bridge_bases(struct pci_bus *child) |
{ |
struct pci_dev *dev = child->self; |
struct resource *res; |
int i; |
if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ |
return; |
dbgprintf("PCI bridge to [bus %02x-%02x]%s\n", |
child->secondary, child->subordinate, |
dev->transparent ? " (subtractive decode)" : ""); |
pci_bus_remove_resources(child); |
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
pci_read_bridge_io(child); |
pci_read_bridge_mmio(child); |
pci_read_bridge_mmio_pref(child); |
if (dev->transparent) { |
pci_bus_for_each_resource(child->parent, res, i) { |
if (res) { |
pci_bus_add_resource(child, res, |
PCI_SUBTRACTIVE_DECODE); |
dbgprintf(" bridge window %pR (subtractive decode)\n", res); |
} |
} |
} |
} |
#endif |
static struct pci_bus * pci_alloc_bus(void) |
{ |
struct pci_bus *b; |
b = kzalloc(sizeof(*b), GFP_KERNEL); |
if (b) { |
INIT_LIST_HEAD(&b->node); |
INIT_LIST_HEAD(&b->children); |
INIT_LIST_HEAD(&b->devices); |
INIT_LIST_HEAD(&b->slots); |
INIT_LIST_HEAD(&b->resources); |
// b->max_bus_speed = PCI_SPEED_UNKNOWN; |
// b->cur_bus_speed = PCI_SPEED_UNKNOWN; |
} |
return b; |
} |
#if 0 |
static unsigned char pcix_bus_speed[] = { |
PCI_SPEED_UNKNOWN, /* 0 */ |
PCI_SPEED_66MHz_PCIX, /* 1 */ |
PCI_SPEED_100MHz_PCIX, /* 2 */ |
PCI_SPEED_133MHz_PCIX, /* 3 */ |
PCI_SPEED_UNKNOWN, /* 4 */ |
PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ |
PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ |
PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ |
PCI_SPEED_UNKNOWN, /* 8 */ |
PCI_SPEED_66MHz_PCIX_266, /* 9 */ |
PCI_SPEED_100MHz_PCIX_266, /* A */ |
PCI_SPEED_133MHz_PCIX_266, /* B */ |
PCI_SPEED_UNKNOWN, /* C */ |
PCI_SPEED_66MHz_PCIX_533, /* D */ |
PCI_SPEED_100MHz_PCIX_533, /* E */ |
PCI_SPEED_133MHz_PCIX_533 /* F */ |
}; |
static unsigned char pcie_link_speed[] = { |
PCI_SPEED_UNKNOWN, /* 0 */ |
PCIE_SPEED_2_5GT, /* 1 */ |
PCIE_SPEED_5_0GT, /* 2 */ |
PCIE_SPEED_8_0GT, /* 3 */ |
PCI_SPEED_UNKNOWN, /* 4 */ |
PCI_SPEED_UNKNOWN, /* 5 */ |
PCI_SPEED_UNKNOWN, /* 6 */ |
PCI_SPEED_UNKNOWN, /* 7 */ |
PCI_SPEED_UNKNOWN, /* 8 */ |
PCI_SPEED_UNKNOWN, /* 9 */ |
PCI_SPEED_UNKNOWN, /* A */ |
PCI_SPEED_UNKNOWN, /* B */ |
PCI_SPEED_UNKNOWN, /* C */ |
PCI_SPEED_UNKNOWN, /* D */ |
PCI_SPEED_UNKNOWN, /* E */ |
PCI_SPEED_UNKNOWN /* F */ |
}; |
static void pci_set_bus_speed(struct pci_bus *bus) |
{ |
struct pci_dev *bridge = bus->self; |
int pos; |
pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
if (!pos) |
pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); |
if (pos) { |
u32 agpstat, agpcmd; |
pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); |
bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); |
pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); |
bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); |
} |
pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
if (pos) { |
u16 status; |
enum pci_bus_speed max; |
pci_read_config_word(bridge, pos + 2, &status); |
if (status & 0x8000) { |
max = PCI_SPEED_133MHz_PCIX_533; |
} else if (status & 0x4000) { |
max = PCI_SPEED_133MHz_PCIX_266; |
} else if (status & 0x0002) { |
if (((status >> 12) & 0x3) == 2) { |
max = PCI_SPEED_133MHz_PCIX_ECC; |
} else { |
max = PCI_SPEED_133MHz_PCIX; |
} |
} else { |
max = PCI_SPEED_66MHz_PCIX; |
} |
bus->max_bus_speed = max; |
bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; |
return; |
} |
pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); |
if (pos) { |
u32 linkcap; |
u16 linksta; |
pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); |
bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; |
pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); |
pcie_update_link_speed(bus, linksta); |
} |
} |
#endif |
static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
struct pci_dev *bridge, int busnr) |
{ |
struct pci_bus *child; |
int i; |
/* |
* Allocate a new bus, and inherit stuff from the parent.. |
*/ |
child = pci_alloc_bus(); |
if (!child) |
return NULL; |
child->parent = parent; |
child->ops = parent->ops; |
child->sysdata = parent->sysdata; |
child->bus_flags = parent->bus_flags; |
/* initialize some portions of the bus device, but don't register it |
* now as the parent is not properly set up yet. This device will get |
* registered later in pci_bus_add_devices() |
*/ |
// child->dev.class = &pcibus_class; |
// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
/* |
* Set up the primary, secondary and subordinate |
* bus numbers. |
*/ |
child->number = child->secondary = busnr; |
child->primary = parent->secondary; |
child->subordinate = 0xff; |
if (!bridge) |
return child; |
child->self = bridge; |
// child->bridge = get_device(&bridge->dev); |
// pci_set_bus_speed(child); |
/* Set up default resource pointers and names.. */ |
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
child->resource[i]->name = child->name; |
} |
bridge->subordinate = child; |
return child; |
} |
struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
{ |
struct pci_bus *child; |
child = pci_alloc_child_bus(parent, dev, busnr); |
if (child) { |
// down_write(&pci_bus_sem); |
list_add_tail(&child->node, &parent->children); |
// up_write(&pci_bus_sem); |
} |
return child; |
} |
static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
{ |
struct pci_bus *parent = child->parent; |
/* Attempts to fix that up are really dangerous unless |
we're going to re-assign all bus numbers. */ |
if (!pcibios_assign_all_busses()) |
return; |
while (parent->parent && parent->subordinate < max) { |
parent->subordinate = max; |
pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); |
parent = parent->parent; |
} |
} |
/* |
* If it's a bridge, configure it and scan the bus behind it. |
* For CardBus bridges, we don't scan behind as the devices will |
* be handled by the bridge driver itself. |
* |
* We need to process bridges in two passes -- first we scan those |
* already configured by the BIOS and after we are done with all of |
* them, we proceed to assigning numbers to the remaining buses in |
* order to avoid overlaps between old and new bus numbers. |
*/ |
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
{ |
struct pci_bus *child; |
int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
u32 buses, i, j = 0; |
u16 bctl; |
u8 primary, secondary, subordinate; |
int broken = 0; |
pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
primary = buses & 0xFF; |
secondary = (buses >> 8) & 0xFF; |
subordinate = (buses >> 16) & 0xFF; |
dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n", |
secondary, subordinate, pass); |
/* Check if setup is sensible at all */ |
if (!pass && |
(primary != bus->number || secondary <= bus->number)) { |
dbgprintf("bus configuration invalid, reconfiguring\n"); |
broken = 1; |
} |
/* Disable MasterAbortMode during probing to avoid reporting |
of bus errors (in some architectures) */ |
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, |
bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
!is_cardbus && !broken) { |
unsigned int cmax; |
/* |
* Bus already configured by firmware, process it in the first |
* pass and just note the configuration. |
*/ |
if (pass) |
goto out; |
/* |
* If we already got to this bus through a different bridge, |
* don't re-add it. This can happen with the i450NX chipset. |
* |
* However, we continue to descend down the hierarchy and |
* scan remaining child buses. |
*/ |
child = pci_find_bus(pci_domain_nr(bus), secondary); |
if (!child) { |
child = pci_add_new_bus(bus, dev, secondary); |
if (!child) |
goto out; |
child->primary = primary; |
child->subordinate = subordinate; |
child->bridge_ctl = bctl; |
} |
cmax = pci_scan_child_bus(child); |
if (cmax > max) |
max = cmax; |
if (child->subordinate > max) |
max = child->subordinate; |
} else { |
/* |
* We need to assign a number to this bus which we always |
* do in the second pass. |
*/ |
if (!pass) { |
if (pcibios_assign_all_busses() || broken) |
/* Temporarily disable forwarding of the |
configuration cycles on all bridges in |
this bus segment to avoid possible |
conflicts in the second pass between two |
bridges programmed with overlapping |
bus ranges. */ |
pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
buses & ~0xffffff); |
goto out; |
} |
/* Clear errors */ |
pci_write_config_word(dev, PCI_STATUS, 0xffff); |
/* Prevent assigning a bus number that already exists. |
* This can happen when a bridge is hot-plugged */ |
if (pci_find_bus(pci_domain_nr(bus), max+1)) |
goto out; |
child = pci_add_new_bus(bus, dev, ++max); |
buses = (buses & 0xff000000) |
| ((unsigned int)(child->primary) << 0) |
| ((unsigned int)(child->secondary) << 8) |
| ((unsigned int)(child->subordinate) << 16); |
/* |
* yenta.c forces a secondary latency timer of 176. |
* Copy that behaviour here. |
*/ |
if (is_cardbus) { |
buses &= ~0xff000000; |
buses |= CARDBUS_LATENCY_TIMER << 24; |
} |
/* |
* We need to blast all three values with a single write. |
*/ |
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
if (!is_cardbus) { |
child->bridge_ctl = bctl; |
/* |
* Adjust subordinate busnr in parent buses. |
* We do this before scanning for children because |
* some devices may not be detected if the bios |
* was lazy. |
*/ |
pci_fixup_parent_subordinate_busnr(child, max); |
/* Now we can scan all subordinate buses... */ |
max = pci_scan_child_bus(child); |
/* |
* now fix it up again since we have found |
* the real value of max. |
*/ |
pci_fixup_parent_subordinate_busnr(child, max); |
} else { |
/* |
* For CardBus bridges, we leave 4 bus numbers |
* as cards with a PCI-to-PCI bridge can be |
* inserted later. |
*/ |
for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
struct pci_bus *parent = bus; |
if (pci_find_bus(pci_domain_nr(bus), |
max+i+1)) |
break; |
while (parent->parent) { |
if ((!pcibios_assign_all_busses()) && |
(parent->subordinate > max) && |
(parent->subordinate <= max+i)) { |
j = 1; |
} |
parent = parent->parent; |
} |
if (j) { |
/* |
* Often, there are two cardbus bridges |
* -- try to leave one valid bus number |
* for each one. |
*/ |
i /= 2; |
break; |
} |
} |
max += i; |
pci_fixup_parent_subordinate_busnr(child, max); |
} |
/* |
* Set the subordinate bus number to its real value. |
*/ |
child->subordinate = max; |
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
} |
vsprintf(child->name, |
(is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), |
pci_domain_nr(bus), child->number); |
/* Has only triggered on CardBus, fixup is in yenta_socket */ |
while (bus->parent) { |
if ((child->subordinate > bus->subordinate) || |
(child->number > bus->subordinate) || |
(child->number < bus->number) || |
(child->subordinate < bus->number)) { |
dbgprintf("[bus %02x-%02x] %s " |
"hidden behind%s bridge %s [bus %02x-%02x]\n", |
child->number, child->subordinate, |
(bus->number > child->subordinate && |
bus->subordinate < child->number) ? |
"wholly" : "partially", |
bus->self->transparent ? " transparent" : "", |
"FIX BRIDGE NAME", |
bus->number, bus->subordinate); |
} |
bus = bus->parent; |
} |
out: |
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
return max; |
} |
void set_pcie_port_type(struct pci_dev *pdev) |
{ |
int pos; |
u16 reg16; |
pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
if (!pos) |
return; |
pdev->is_pcie = 1; |
pdev->pcie_cap = pos; |
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; |
} |
void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
{ |
int pos; |
u16 reg16; |
u32 reg32; |
pos = pci_pcie_cap(pdev); |
if (!pos) |
return; |
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
if (!(reg16 & PCI_EXP_FLAGS_SLOT)) |
return; |
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); |
if (reg32 & PCI_EXP_SLTCAP_HPC) |
pdev->is_hotplug_bridge = 1; |
} |
/* |
* Read interrupt line and base address registers. |
* The architecture-dependent code can tweak these, of course. |
*/ |
static void pci_read_irq(struct pci_dev *dev) |
{ |
unsigned char irq; |
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
dev->pin = irq; |
if (irq) |
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
dev->irq = irq; |
} |
/** |
* pci_setup_device - fill in class and map information of a device |
* @dev: the device structure to fill |
* |
176,7 → 875,9 |
/* some broken boards return 0 or ~0 if a slot is empty: */ |
if (l == 0xffffffff || l == 0x00000000 || |
l == 0x0000ffff || l == 0xffff0000) |
l == 0x0000ffff || l == 0xffff0000 || |
(l & 0xffff0000) == 0xffff0000 || |
(l & 0x0000ffff) == 0x0000ffff ) |
return NULL; |
/* Configuration request Retry Status */ |
186,7 → 887,7 |
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
return NULL; |
/* Card hasn't responded in 60 seconds? Must be stuck. */ |
if (delay > 60 * 1000) { |
if (timeout > 60 * 1000) { |
printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
"responding\n", pci_domain_nr(bus), |
bus->number, PCI_SLOT(devfn), |
212,7 → 913,37 |
return dev; |
} |
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
{ |
// device_initialize(&dev->dev); |
// dev->dev.release = pci_release_dev; |
// pci_dev_get(dev); |
// dev->dev.dma_mask = &dev->dma_mask; |
// dev->dev.dma_parms = &dev->dma_parms; |
// dev->dev.coherent_dma_mask = 0xffffffffull; |
// pci_set_dma_max_seg_size(dev, 65536); |
// pci_set_dma_seg_boundary(dev, 0xffffffff); |
/* Fix up broken headers */ |
// pci_fixup_device(pci_fixup_header, dev); |
/* Clear the state_saved flag. */ |
dev->state_saved = false; |
/* Initialize various capabilities */ |
// pci_init_capabilities(dev); |
/* |
* Add the device to our list of discovered devices |
* and the bus list for fixup functions, etc. |
*/ |
// down_write(&pci_bus_sem); |
list_add_tail(&dev->bus_list, &bus->devices); |
// up_write(&pci_bus_sem); |
} |
struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn) |
{ |
struct pci_dev *dev; |
312,8 → 1043,8 |
} |
/* only one slot has pcie device */ |
if (bus->self && nr) |
pcie_aspm_init_link_state(bus->self); |
// if (bus->self && nr) |
// pcie_aspm_init_link_state(bus->self); |
return nr; |
} |
339,7 → 1070,7 |
*/ |
if (!bus->is_added) { |
dbgprintf("fixups for bus\n"); |
pcibios_fixup_bus(bus); |
// pcibios_fixup_bus(bus); |
if (pci_is_root_bus(bus)) |
bus->is_added = 1; |
} |
417,3 → 1148,38 |
} |
struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata) |
{ |
int error; |
struct pci_bus *b, *b2; |
b = pci_alloc_bus(); |
if (!b) |
return NULL; |
b->sysdata = sysdata; |
b->ops = ops; |
b2 = pci_find_bus(pci_domain_nr(b), bus); |
if (b2) { |
/* If we already got to this bus through a different bridge, ignore it */ |
dbgprintf("bus already known\n"); |
goto err_out; |
} |
// down_write(&pci_bus_sem); |
list_add_tail(&b->node, &pci_root_buses); |
// up_write(&pci_bus_sem); |
b->number = b->secondary = bus; |
b->resource[0] = &ioport_resource; |
b->resource[1] = &iomem_resource; |
return b; |
err_out: |
kfree(b); |
return NULL; |
} |
/drivers/include/ddk.h |
---|
1,9 → 1,12 |
#ifndef __DDK_H__ |
#define __DDK_H__ |
#include <kernel.h> |
#include <mutex.h> |
#define OS_BASE 0x80000000 |
#define PG_SW 0x003 |
/drivers/include/linux/asm/atomic_32.h |
---|
File deleted |
/drivers/include/linux/asm/atomic.h |
---|
1,5 → 1,318 |
#ifdef CONFIG_X86_32 |
# include "atomic_32.h" |
#else |
# include "atomic_64.h" |
#ifndef _ASM_X86_ATOMIC_H |
#define _ASM_X86_ATOMIC_H |
#include <linux/compiler.h> |
#include <linux/types.h> |
//#include <asm/processor.h> |
//#include <asm/alternative.h> |
#include <asm/cmpxchg.h> |
/* |
* Atomic operations that C can't guarantee us. Useful for |
* resource counting etc.. |
*/ |
#define ATOMIC_INIT(i) { (i) } |
/** |
* atomic_read - read atomic variable |
* @v: pointer of type atomic_t |
* |
* Atomically reads the value of @v. |
*/ |
static inline int atomic_read(const atomic_t *v) |
{ |
return (*(volatile int *)&(v)->counter); |
} |
/** |
* atomic_set - set atomic variable |
* @v: pointer of type atomic_t |
* @i: required value |
* |
* Atomically sets the value of @v to @i. |
*/ |
static inline void atomic_set(atomic_t *v, int i) |
{ |
v->counter = i; |
} |
/** |
* atomic_add - add integer to atomic variable |
* @i: integer value to add |
* @v: pointer of type atomic_t |
* |
* Atomically adds @i to @v. |
*/ |
static inline void atomic_add(int i, atomic_t *v) |
{ |
asm volatile(LOCK_PREFIX "addl %1,%0" |
: "+m" (v->counter) |
: "ir" (i)); |
} |
/** |
* atomic_sub - subtract integer from atomic variable |
* @i: integer value to subtract |
* @v: pointer of type atomic_t |
* |
* Atomically subtracts @i from @v. |
*/ |
static inline void atomic_sub(int i, atomic_t *v) |
{ |
asm volatile(LOCK_PREFIX "subl %1,%0" |
: "+m" (v->counter) |
: "ir" (i)); |
} |
/** |
* atomic_sub_and_test - subtract value from variable and test result |
* @i: integer value to subtract |
* @v: pointer of type atomic_t |
* |
* Atomically subtracts @i from @v and returns |
* true if the result is zero, or false for all |
* other cases. |
*/ |
static inline int atomic_sub_and_test(int i, atomic_t *v) |
{ |
unsigned char c; |
asm volatile(LOCK_PREFIX "subl %2,%0; sete %1" |
: "+m" (v->counter), "=qm" (c) |
: "ir" (i) : "memory"); |
return c; |
} |
/** |
* atomic_inc - increment atomic variable |
* @v: pointer of type atomic_t |
* |
* Atomically increments @v by 1. |
*/ |
static inline void atomic_inc(atomic_t *v) |
{ |
asm volatile(LOCK_PREFIX "incl %0" |
: "+m" (v->counter)); |
} |
/** |
* atomic_dec - decrement atomic variable |
* @v: pointer of type atomic_t |
* |
* Atomically decrements @v by 1. |
*/ |
static inline void atomic_dec(atomic_t *v) |
{ |
asm volatile(LOCK_PREFIX "decl %0" |
: "+m" (v->counter)); |
} |
/** |
* atomic_dec_and_test - decrement and test |
* @v: pointer of type atomic_t |
* |
* Atomically decrements @v by 1 and |
* returns true if the result is 0, or false for all other |
* cases. |
*/ |
static inline int atomic_dec_and_test(atomic_t *v) |
{ |
unsigned char c; |
asm volatile(LOCK_PREFIX "decl %0; sete %1" |
: "+m" (v->counter), "=qm" (c) |
: : "memory"); |
return c != 0; |
} |
/** |
* atomic_inc_and_test - increment and test |
* @v: pointer of type atomic_t |
* |
* Atomically increments @v by 1 |
* and returns true if the result is zero, or false for all |
* other cases. |
*/ |
static inline int atomic_inc_and_test(atomic_t *v) |
{ |
unsigned char c; |
asm volatile(LOCK_PREFIX "incl %0; sete %1" |
: "+m" (v->counter), "=qm" (c) |
: : "memory"); |
return c != 0; |
} |
/** |
* atomic_add_negative - add and test if negative |
* @i: integer value to add |
* @v: pointer of type atomic_t |
* |
* Atomically adds @i to @v and returns true |
* if the result is negative, or false when |
* result is greater than or equal to zero. |
*/ |
static inline int atomic_add_negative(int i, atomic_t *v) |
{ |
unsigned char c; |
asm volatile(LOCK_PREFIX "addl %2,%0; sets %1" |
: "+m" (v->counter), "=qm" (c) |
: "ir" (i) : "memory"); |
return c; |
} |
/** |
* atomic_add_return - add integer and return |
* @i: integer value to add |
* @v: pointer of type atomic_t |
* |
* Atomically adds @i to @v and returns @i + @v |
*/ |
static inline int atomic_add_return(int i, atomic_t *v) |
{ |
int __i; |
#ifdef CONFIG_M386 |
unsigned long flags; |
if (unlikely(boot_cpu_data.x86 <= 3)) |
goto no_xadd; |
#endif |
/* Modern 486+ processor */ |
__i = i; |
asm volatile(LOCK_PREFIX "xaddl %0, %1" |
: "+r" (i), "+m" (v->counter) |
: : "memory"); |
return i + __i; |
#ifdef CONFIG_M386 |
no_xadd: /* Legacy 386 processor */ |
raw_local_irq_save(flags); |
__i = atomic_read(v); |
atomic_set(v, i + __i); |
raw_local_irq_restore(flags); |
return i + __i; |
#endif |
} |
/** |
* atomic_sub_return - subtract integer and return |
* @v: pointer of type atomic_t |
* @i: integer value to subtract |
* |
* Atomically subtracts @i from @v and returns @v - @i |
*/ |
static inline int atomic_sub_return(int i, atomic_t *v) |
{ |
return atomic_add_return(-i, v); |
} |
#define atomic_inc_return(v) (atomic_add_return(1, v)) |
#define atomic_dec_return(v) (atomic_sub_return(1, v)) |
static inline int atomic_cmpxchg(atomic_t *v, int old, int new) |
{ |
return cmpxchg(&v->counter, old, new); |
} |
static inline int atomic_xchg(atomic_t *v, int new) |
{ |
return xchg(&v->counter, new); |
} |
/** |
* atomic_add_unless - add unless the number is already a given value |
* @v: pointer of type atomic_t |
* @a: the amount to add to v... |
* @u: ...unless v is equal to u. |
* |
* Atomically adds @a to @v, so long as @v was not already @u. |
* Returns non-zero if @v was not @u, and zero otherwise. |
*/ |
static inline int atomic_add_unless(atomic_t *v, int a, int u) |
{ |
int c, old; |
c = atomic_read(v); |
for (;;) { |
if (unlikely(c == (u))) |
break; |
old = atomic_cmpxchg((v), c, c + (a)); |
if (likely(old == c)) |
break; |
c = old; |
} |
return c != (u); |
} |
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) |
/* |
* atomic_dec_if_positive - decrement by 1 if old value positive |
* @v: pointer of type atomic_t |
* |
* The function returns the old value of *v minus 1, even if |
* the atomic variable, v, was not decremented. |
*/ |
static inline int atomic_dec_if_positive(atomic_t *v) |
{ |
int c, old, dec; |
c = atomic_read(v); |
for (;;) { |
dec = c - 1; |
if (unlikely(dec < 0)) |
break; |
old = atomic_cmpxchg((v), c, dec); |
if (likely(old == c)) |
break; |
c = old; |
} |
return dec; |
} |
/** |
* atomic_inc_short - increment of a short integer |
* @v: pointer to type int |
* |
* Atomically adds 1 to @v |
* Returns the new value of @u |
*/ |
static inline short int atomic_inc_short(short int *v) |
{ |
asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v)); |
return *v; |
} |
#ifdef CONFIG_X86_64 |
/** |
* atomic_or_long - OR of two long integers |
* @v1: pointer to type unsigned long |
* @v2: pointer to type unsigned long |
* |
* Atomically ORs @v1 and @v2 |
* Returns the result of the OR |
*/ |
static inline void atomic_or_long(unsigned long *v1, unsigned long v2) |
{ |
asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2)); |
} |
#endif |
/* These are x86-specific, used by some header files */ |
#define atomic_clear_mask(mask, addr) \ |
asm volatile(LOCK_PREFIX "andl %0,%1" \ |
: : "r" (~(mask)), "m" (*(addr)) : "memory") |
#define atomic_set_mask(mask, addr) \ |
asm volatile(LOCK_PREFIX "orl %0,%1" \ |
: : "r" ((unsigned)(mask)), "m" (*(addr)) \ |
: "memory") |
/* Atomic operations are already serializing on x86 */ |
#define smp_mb__before_atomic_dec() barrier() |
#define smp_mb__after_atomic_dec() barrier() |
#define smp_mb__before_atomic_inc() barrier() |
#define smp_mb__after_atomic_inc() barrier() |
//#include <asm-generic/atomic-long.h> |
#endif /* _ASM_X86_ATOMIC_H */ |
/drivers/include/linux/asm/cmpxchg_32.h |
---|
26,23 → 26,32 |
__typeof(*(ptr)) __x = (x); \ |
switch (size) { \ |
case 1: \ |
asm volatile("xchgb %b0,%1" \ |
: "=q" (__x) \ |
: "m" (*__xg(ptr)), "0" (__x) \ |
{ \ |
volatile u8 *__ptr = (volatile u8 *)(ptr); \ |
asm volatile("xchgb %0,%1" \ |
: "=q" (__x), "+m" (*__ptr) \ |
: "0" (__x) \ |
: "memory"); \ |
break; \ |
} \ |
case 2: \ |
asm volatile("xchgw %w0,%1" \ |
: "=r" (__x) \ |
: "m" (*__xg(ptr)), "0" (__x) \ |
{ \ |
volatile u16 *__ptr = (volatile u16 *)(ptr); \ |
asm volatile("xchgw %0,%1" \ |
: "=r" (__x), "+m" (*__ptr) \ |
: "0" (__x) \ |
: "memory"); \ |
break; \ |
} \ |
case 4: \ |
{ \ |
volatile u32 *__ptr = (volatile u32 *)(ptr); \ |
asm volatile("xchgl %0,%1" \ |
: "=r" (__x) \ |
: "m" (*__xg(ptr)), "0" (__x) \ |
: "=r" (__x), "+m" (*__ptr) \ |
: "0" (__x) \ |
: "memory"); \ |
break; \ |
} \ |
default: \ |
__xchg_wrong_size(); \ |
} \ |
53,60 → 62,33 |
__xchg((v), (ptr), sizeof(*ptr)) |
/* |
* The semantics of XCHGCMP8B are a bit strange, this is why |
* there is a loop and the loading of %%eax and %%edx has to |
* be inside. This inlines well in most cases, the cached |
* cost is around ~38 cycles. (in the future we might want |
* to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that |
* might have an implicit FPU-save as a cost, so it's not |
* clear which path to go.) |
* CMPXCHG8B only writes to the target if we had the previous |
* value in registers, otherwise it acts as a read and gives us the |
* "new previous" value. That is why there is a loop. Preloading |
* EDX:EAX is a performance optimization: in the common case it means |
* we need only one locked operation. |
* |
* cmpxchg8b must be used with the lock prefix here to allow |
* the instruction to be executed atomically, see page 3-102 |
* of the instruction set reference 24319102.pdf. We need |
* the reader side to see the coherent 64bit value. |
* A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very |
* least an FPU save and/or %cr0.ts manipulation. |
* |
* cmpxchg8b must be used with the lock prefix here to allow the |
* instruction to be executed atomically. We need to have the reader |
* side to see the coherent 64bit value. |
*/ |
static inline void __set_64bit(unsigned long long *ptr, |
unsigned int low, unsigned int high) |
static inline void set_64bit(volatile u64 *ptr, u64 value) |
{ |
u32 low = value; |
u32 high = value >> 32; |
u64 prev = *ptr; |
asm volatile("\n1:\t" |
"movl (%0), %%eax\n\t" |
"movl 4(%0), %%edx\n\t" |
LOCK_PREFIX "cmpxchg8b (%0)\n\t" |
LOCK_PREFIX "cmpxchg8b %0\n\t" |
"jnz 1b" |
: /* no outputs */ |
: "D"(ptr), |
"b"(low), |
"c"(high) |
: "ax", "dx", "memory"); |
: "=m" (*ptr), "+A" (prev) |
: "b" (low), "c" (high) |
: "memory"); |
} |
static inline void __set_64bit_constant(unsigned long long *ptr, |
unsigned long long value) |
{ |
__set_64bit(ptr, (unsigned int)value, (unsigned int)(value >> 32)); |
} |
#define ll_low(x) *(((unsigned int *)&(x)) + 0) |
#define ll_high(x) *(((unsigned int *)&(x)) + 1) |
static inline void __set_64bit_var(unsigned long long *ptr, |
unsigned long long value) |
{ |
__set_64bit(ptr, ll_low(value), ll_high(value)); |
} |
#define set_64bit(ptr, value) \ |
(__builtin_constant_p((value)) \ |
? __set_64bit_constant((ptr), (value)) \ |
: __set_64bit_var((ptr), (value))) |
#define _set_64bit(ptr, value) \ |
(__builtin_constant_p(value) \ |
? __set_64bit(ptr, (unsigned int)(value), \ |
(unsigned int)((value) >> 32)) \ |
: __set_64bit(ptr, ll_low((value)), ll_high((value)))) |
extern void __cmpxchg_wrong_size(void); |
/* |
121,23 → 103,32 |
__typeof__(*(ptr)) __new = (new); \ |
switch (size) { \ |
case 1: \ |
asm volatile(lock "cmpxchgb %b1,%2" \ |
: "=a"(__ret) \ |
: "q"(__new), "m"(*__xg(ptr)), "0"(__old) \ |
{ \ |
volatile u8 *__ptr = (volatile u8 *)(ptr); \ |
asm volatile(lock "cmpxchgb %2,%1" \ |
: "=a" (__ret), "+m" (*__ptr) \ |
: "q" (__new), "0" (__old) \ |
: "memory"); \ |
break; \ |
} \ |
case 2: \ |
asm volatile(lock "cmpxchgw %w1,%2" \ |
: "=a"(__ret) \ |
: "r"(__new), "m"(*__xg(ptr)), "0"(__old) \ |
{ \ |
volatile u16 *__ptr = (volatile u16 *)(ptr); \ |
asm volatile(lock "cmpxchgw %2,%1" \ |
: "=a" (__ret), "+m" (*__ptr) \ |
: "r" (__new), "0" (__old) \ |
: "memory"); \ |
break; \ |
} \ |
case 4: \ |
asm volatile(lock "cmpxchgl %1,%2" \ |
: "=a"(__ret) \ |
: "r"(__new), "m"(*__xg(ptr)), "0"(__old) \ |
{ \ |
volatile u32 *__ptr = (volatile u32 *)(ptr); \ |
asm volatile(lock "cmpxchgl %2,%1" \ |
: "=a" (__ret), "+m" (*__ptr) \ |
: "r" (__new), "0" (__old) \ |
: "memory"); \ |
break; \ |
} \ |
default: \ |
__cmpxchg_wrong_size(); \ |
} \ |
175,31 → 166,27 |
(unsigned long long)(n))) |
#endif |
static inline unsigned long long __cmpxchg64(volatile void *ptr, |
unsigned long long old, |
unsigned long long new) |
static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new) |
{ |
unsigned long long prev; |
asm volatile(LOCK_PREFIX "cmpxchg8b %3" |
: "=A"(prev) |
: "b"((unsigned long)new), |
"c"((unsigned long)(new >> 32)), |
"m"(*__xg(ptr)), |
u64 prev; |
asm volatile(LOCK_PREFIX "cmpxchg8b %1" |
: "=A" (prev), |
"+m" (*ptr) |
: "b" ((u32)new), |
"c" ((u32)(new >> 32)), |
"0"(old) |
: "memory"); |
return prev; |
} |
static inline unsigned long long __cmpxchg64_local(volatile void *ptr, |
unsigned long long old, |
unsigned long long new) |
static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new) |
{ |
unsigned long long prev; |
asm volatile("cmpxchg8b %3" |
: "=A"(prev) |
: "b"((unsigned long)new), |
"c"((unsigned long)(new >> 32)), |
"m"(*__xg(ptr)), |
u64 prev; |
asm volatile("cmpxchg8b %1" |
: "=A" (prev), |
"+m" (*ptr) |
: "b" ((u32)new), |
"c" ((u32)(new >> 32)), |
"0"(old) |
: "memory"); |
return prev; |
212,6 → 199,24 |
* a function for each of the sizes we support. |
*/ |
extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8); |
extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16); |
extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32); |
static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old, |
unsigned long new, int size) |
{ |
switch (size) { |
case 1: |
return cmpxchg_386_u8(ptr, old, new); |
case 2: |
return cmpxchg_386_u16(ptr, old, new); |
case 4: |
return cmpxchg_386_u32(ptr, old, new); |
} |
return old; |
} |
#define cmpxchg(ptr, o, n) \ |
({ \ |
__typeof__(*(ptr)) __ret; \ |
236,14 → 241,13 |
* to simulate the cmpxchg8b on the 80386 and 80486 CPU. |
*/ |
extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64); |
#define cmpxchg64(ptr, o, n) \ |
({ \ |
__typeof__(*(ptr)) __ret; \ |
__typeof__(*(ptr)) __old = (o); \ |
__typeof__(*(ptr)) __new = (n); \ |
alternative_io("call cmpxchg8b_emu", \ |
alternative_io(LOCK_PREFIX_HERE \ |
"call cmpxchg8b_emu", \ |
"lock; cmpxchg8b (%%esi)" , \ |
X86_FEATURE_CX8, \ |
"=A" (__ret), \ |
254,20 → 258,20 |
__ret; }) |
#define cmpxchg64_local(ptr, o, n) \ |
({ \ |
__typeof__(*(ptr)) __ret; \ |
if (likely(boot_cpu_data.x86 > 4)) \ |
__ret = (__typeof__(*(ptr)))__cmpxchg64_local((ptr), \ |
(unsigned long long)(o), \ |
(unsigned long long)(n)); \ |
else \ |
__ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr), \ |
(unsigned long long)(o), \ |
(unsigned long long)(n)); \ |
__ret; \ |
}) |
__typeof__(*(ptr)) __old = (o); \ |
__typeof__(*(ptr)) __new = (n); \ |
alternative_io("call cmpxchg8b_emu", \ |
"cmpxchg8b (%%esi)" , \ |
X86_FEATURE_CX8, \ |
"=A" (__ret), \ |
"S" ((ptr)), "0" (__old), \ |
"b" ((unsigned int)__new), \ |
"c" ((unsigned int)(__new>>32)) \ |
: "memory"); \ |
__ret; }) |
#endif |
/drivers/include/linux/i2c.h |
---|
33,7 → 33,15 |
#define I2C_NAME_SIZE 20 |
#define I2C_MODULE_PREFIX "i2c:" |
struct i2c_device_id { |
char name[I2C_NAME_SIZE]; |
u32 driver_data /* Data private to the driver */ |
__attribute__((aligned(sizeof(u32)))); |
}; |
struct i2c_msg; |
struct i2c_algorithm; |
struct i2c_adapter; |
203,7 → 211,7 |
}; |
#define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev) |
static inline void *i2c_get_adapdata(const struct i2c_adapter *dev) |
static inline void *i2c_get_adapdata(struct i2c_adapter *dev) |
{ |
return dev_get_drvdata(&dev->dev); |
} |
/drivers/include/linux/ioport.h |
---|
0,0 → 1,127 |
/* |
* ioport.h Definitions of routines for detecting, reserving and |
* allocating system resources. |
* |
* Authors: Linus Torvalds |
*/ |
#ifndef _LINUX_IOPORT_H |
#define _LINUX_IOPORT_H |
#ifndef __ASSEMBLY__ |
#include <linux/compiler.h> |
#include <linux/types.h> |
/* |
* Resources are tree-like, allowing |
* nesting etc.. |
*/ |
struct resource { |
resource_size_t start; |
resource_size_t end; |
const char *name; |
unsigned long flags; |
struct resource *parent, *sibling, *child; |
}; |
struct resource_list { |
struct resource_list *next; |
struct resource *res; |
struct pci_dev *dev; |
}; |
/* |
* IO resources have these defined flags. |
*/ |
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
#define IORESOURCE_TYPE_BITS 0x00001f00 /* Resource type */ |
#define IORESOURCE_IO 0x00000100 |
#define IORESOURCE_MEM 0x00000200 |
#define IORESOURCE_IRQ 0x00000400 |
#define IORESOURCE_DMA 0x00000800 |
#define IORESOURCE_BUS 0x00001000 |
#define IORESOURCE_PREFETCH 0x00002000 /* No side effects */ |
#define IORESOURCE_READONLY 0x00004000 |
#define IORESOURCE_CACHEABLE 0x00008000 |
#define IORESOURCE_RANGELENGTH 0x00010000 |
#define IORESOURCE_SHADOWABLE 0x00020000 |
#define IORESOURCE_SIZEALIGN 0x00040000 /* size indicates alignment */ |
#define IORESOURCE_STARTALIGN 0x00080000 /* start field is alignment */ |
#define IORESOURCE_MEM_64 0x00100000 |
#define IORESOURCE_WINDOW 0x00200000 /* forwarded by bridge */ |
#define IORESOURCE_MUXED 0x00400000 /* Resource is software muxed */ |
#define IORESOURCE_EXCLUSIVE 0x08000000 /* Userland may not map this resource */ |
#define IORESOURCE_DISABLED 0x10000000 |
#define IORESOURCE_UNSET 0x20000000 |
#define IORESOURCE_AUTO 0x40000000 |
#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
/* PnP IRQ specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
#define IORESOURCE_IRQ_LOWEDGE (1<<1) |
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
#define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
#define IORESOURCE_IRQ_SHAREABLE (1<<4) |
#define IORESOURCE_IRQ_OPTIONAL (1<<5) |
/* PnP DMA specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_DMA_TYPE_MASK (3<<0) |
#define IORESOURCE_DMA_8BIT (0<<0) |
#define IORESOURCE_DMA_8AND16BIT (1<<0) |
#define IORESOURCE_DMA_16BIT (2<<0) |
#define IORESOURCE_DMA_MASTER (1<<2) |
#define IORESOURCE_DMA_BYTE (1<<3) |
#define IORESOURCE_DMA_WORD (1<<4) |
#define IORESOURCE_DMA_SPEED_MASK (3<<6) |
#define IORESOURCE_DMA_COMPATIBLE (0<<6) |
#define IORESOURCE_DMA_TYPEA (1<<6) |
#define IORESOURCE_DMA_TYPEB (2<<6) |
#define IORESOURCE_DMA_TYPEF (3<<6) |
/* PnP memory I/O specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
#define IORESOURCE_MEM_TYPE_MASK (3<<3) |
#define IORESOURCE_MEM_8BIT (0<<3) |
#define IORESOURCE_MEM_16BIT (1<<3) |
#define IORESOURCE_MEM_8AND16BIT (2<<3) |
#define IORESOURCE_MEM_32BIT (3<<3) |
#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
#define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
/* PnP I/O specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_IO_16BIT_ADDR (1<<0) |
#define IORESOURCE_IO_FIXED (1<<1) |
/* PCI ROM control bits (IORESOURCE_BITS) */ |
#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
/* PC/ISA/whatever - the normal PC address spaces: IO and memory */ |
extern struct resource ioport_resource; |
extern struct resource iomem_resource; |
static inline resource_size_t resource_size(const struct resource *res) |
{ |
return res->end - res->start + 1; |
} |
static inline unsigned long resource_type(const struct resource *res) |
{ |
return res->flags & IORESOURCE_TYPE_BITS; |
} |
#endif /* __ASSEMBLY__ */ |
#endif /* _LINUX_IOPORT_H */ |
/drivers/include/linux/pci.h |
---|
1,12 → 1,13 |
#ifndef __PCI_H__ |
#define __PCI_H__ |
#include <types.h> |
#include <list.h> |
#include <ioport.h> |
#include <pci_regs.h> |
#include <linux/errno.h> |
#ifndef __PCI_H__ |
#define __PCI_H__ |
/* pci_slot represents a physical slot */ |
struct pci_slot { |
struct pci_bus *bus; /* The bus this slot is on */ |
238,16 → 239,6 |
return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
} |
struct resource |
{ |
resource_size_t start; |
resource_size_t end; |
const char *name; |
unsigned long flags; |
struct resource *parent, *sibling, *child; |
}; |
/* This defines the direction arg to the DMA mapping routines. */ |
#define PCI_DMA_BIDIRECTIONAL 0 |
#define PCI_DMA_TODEVICE 1 |
287,75 → 278,6 |
/* |
* IO resources have these defined flags. |
*/ |
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
#define IORESOURCE_IO 0x00000100 /* Resource type */ |
#define IORESOURCE_MEM 0x00000200 |
#define IORESOURCE_IRQ 0x00000400 |
#define IORESOURCE_DMA 0x00000800 |
#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ |
#define IORESOURCE_READONLY 0x00002000 |
#define IORESOURCE_CACHEABLE 0x00004000 |
#define IORESOURCE_RANGELENGTH 0x00008000 |
#define IORESOURCE_SHADOWABLE 0x00010000 |
#define IORESOURCE_BUS_HAS_VGA 0x00080000 |
#define IORESOURCE_DISABLED 0x10000000 |
#define IORESOURCE_UNSET 0x20000000 |
#define IORESOURCE_AUTO 0x40000000 |
#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
#define IORESOURCE_IRQ_LOWEDGE (1<<1) |
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
#define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
#define IORESOURCE_IRQ_SHAREABLE (1<<4) |
/* ISA PnP DMA specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_DMA_TYPE_MASK (3<<0) |
#define IORESOURCE_DMA_8BIT (0<<0) |
#define IORESOURCE_DMA_8AND16BIT (1<<0) |
#define IORESOURCE_DMA_16BIT (2<<0) |
#define IORESOURCE_DMA_MASTER (1<<2) |
#define IORESOURCE_DMA_BYTE (1<<3) |
#define IORESOURCE_DMA_WORD (1<<4) |
#define IORESOURCE_DMA_SPEED_MASK (3<<6) |
#define IORESOURCE_DMA_COMPATIBLE (0<<6) |
#define IORESOURCE_DMA_TYPEA (1<<6) |
#define IORESOURCE_DMA_TYPEB (2<<6) |
#define IORESOURCE_DMA_TYPEF (3<<6) |
/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
#define IORESOURCE_MEM_TYPE_MASK (3<<3) |
#define IORESOURCE_MEM_8BIT (0<<3) |
#define IORESOURCE_MEM_16BIT (1<<3) |
#define IORESOURCE_MEM_8AND16BIT (2<<3) |
#define IORESOURCE_MEM_32BIT (3<<3) |
#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
#define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
/* PCI ROM control bits (IORESOURCE_BITS) */ |
#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
/* |
* For PCI devices, the region numbers are assigned this way: |
* |
* 0-5 standard PCI regions |
388,6 → 310,14 |
#define PCI_UNKNOWN ((pci_power_t __force) 5) |
#define PCI_POWER_ERROR ((pci_power_t __force) -1) |
enum pci_bar_type { |
pci_bar_unknown, /* Standard PCI BAR probe */ |
pci_bar_io, /* An io port BAR */ |
pci_bar_mem32, /* A 32-bit memory BAR */ |
pci_bar_mem64, /* A 64-bit memory BAR */ |
}; |
/* |
* The pci_dev structure is used to describe PCI devices. |
*/ |
479,7 → 409,7 |
// u32 saved_config_space[16]; /* config space saved at suspend time */ |
// struct hlist_head saved_cap_space; |
// struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
// int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
// struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
// struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
}; |
622,6 → 552,7 |
extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
int enum_pci_devices(void); |
642,7 → 573,10 |
int cap); |
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
struct pci_bus * pci_find_next_bus(const struct pci_bus *from); |
unsigned int pci_scan_child_bus(struct pci_bus *bus); |
void pcibios_fixup_bus(struct pci_bus *b); |
static inline bool pci_is_root_bus(struct pci_bus *pbus) |
{ |
return !(pbus->parent); |
675,6 → 609,49 |
return !!pci_pcie_cap(dev); |
} |
int pci_read_config_dyte(struct pci_dev *dev, int where, u16 *val); |
int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); |
int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
static inline int pci_iov_init(struct pci_dev *dev) |
{ |
return -ENODEV; |
} |
static inline void pci_iov_release(struct pci_dev *dev) |
{ |
} |
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
enum pci_bar_type *type) |
{ |
return 0; |
} |
static inline void pci_restore_iov_state(struct pci_dev *dev) |
{ |
} |
static inline int pci_iov_bus_range(struct pci_bus *bus) |
{ |
return 0; |
} |
static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
{ |
return -ENODEV; |
} |
static inline void pci_disable_ats(struct pci_dev *dev) |
{ |
} |
static inline int pci_ats_queue_depth(struct pci_dev *dev) |
{ |
return -ENODEV; |
} |
static inline int pci_ats_enabled(struct pci_dev *dev) |
{ |
return 0; |
} |
#define pci_name(x) "radeon" |
#endif //__PCI__H__ |
/drivers/include/syscall.h |
---|
405,17 → 405,6 |
FreeKernelSpace(addr); |
} |
static inline void * |
pci_alloc_consistent(struct pci_dev *hwdev, size_t size, |
addr_t *dma_handle) |
{ |
size = (size + 0x7FFF) & ~0x7FFF; |
*dma_handle = AllocPages(size >> 12); |
return (void*)MapIoMem(*dma_handle, size, PG_SW+PG_NOCACHE); |
} |
static inline void __SysMsgBoardStr(char *text) |
{ |
__asm__ __volatile__( |
/drivers/video/drm/radeon/radeon_gart.c |
---|
30,6 → 30,18 |
#include "radeon.h" |
#include "radeon_reg.h" |
static inline void * |
pci_alloc_consistent(struct pci_dev *hwdev, size_t size, |
addr_t *dma_handle) |
{ |
size = (size + 0x7FFF) & ~0x7FFF; |
*dma_handle = AllocPages(size >> 12); |
return (void*)MapIoMem(*dma_handle, size, PG_SW+PG_NOCACHE); |
} |
/* |
* Common GART table functions. |
*/ |
271,3 → 283,5 |
rdev->gart.pages = NULL; |
rdev->gart.pages_addr = NULL; |
} |