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Regard whitespace Rev 4400 → Rev 4401

/contrib/sdk/sources/Mesa/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
62,11 → 62,17
return num;
}
 
static void regmask_set(regmask_t regmask, struct ir3_register *reg)
static void regmask_set(regmask_t regmask, struct ir3_register *reg,
unsigned wrmask)
{
unsigned idx = regmask_idx(reg);
unsigned i;
for (i = 0; i < 4; i++) {
if (wrmask & (1 << i)) {
unsigned idx = regmask_idx(reg) + i;
regmask[idx / 8] |= 1 << (idx % 8);
}
}
}
 
static unsigned regmask_get(regmask_t regmask, struct ir3_register *reg)
{
91,6 → 97,7
 
unsigned next_inloc;
unsigned num_internal_temps;
struct tgsi_src_register internal_temps[6];
 
/* track registers which need to synchronize w/ "complex alu" cat3
* instruction pipeline:
128,9 → 135,16
* up the vector operation
*/
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register *tmp_src;
};
 
 
static void vectorize(struct fd3_compile_context *ctx,
struct ir3_instruction *instr, struct tgsi_dst_register *dst,
int nsrcs, ...);
static void create_mov(struct fd3_compile_context *ctx,
struct tgsi_dst_register *dst, struct tgsi_src_register *src);
 
static unsigned
compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
const struct tgsi_token *tokens)
154,19 → 168,19
/* Immediates go after constants: */
ctx->base_reg[TGSI_FILE_CONSTANT] = 0;
ctx->base_reg[TGSI_FILE_IMMEDIATE] =
ctx->info.file_count[TGSI_FILE_CONSTANT];
ctx->info.file_max[TGSI_FILE_CONSTANT] + 1;
 
/* Temporaries after outputs after inputs: */
ctx->base_reg[TGSI_FILE_INPUT] = 0;
ctx->base_reg[TGSI_FILE_OUTPUT] =
ctx->info.file_count[TGSI_FILE_INPUT];
ctx->info.file_max[TGSI_FILE_INPUT] + 1;
ctx->base_reg[TGSI_FILE_TEMPORARY] =
ctx->info.file_count[TGSI_FILE_INPUT] +
ctx->info.file_count[TGSI_FILE_OUTPUT];
ctx->info.file_max[TGSI_FILE_INPUT] + 1 +
ctx->info.file_max[TGSI_FILE_OUTPUT] + 1;
 
so->first_immediate = ctx->base_reg[TGSI_FILE_IMMEDIATE];
ctx->immediate_idx = 4 * (ctx->info.file_count[TGSI_FILE_CONSTANT] +
ctx->info.file_count[TGSI_FILE_IMMEDIATE]);
ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_CONSTANT] + 1 +
ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
 
ret = tgsi_parse_init(&ctx->parser, tokens);
if (ret != TGSI_PARSE_OK)
178,6 → 192,21
}
 
static void
compile_error(struct fd3_compile_context *ctx, const char *format, ...)
{
va_list ap;
va_start(ap, format);
_debug_vprintf(format, ap);
va_end(ap);
tgsi_dump(ctx->tokens, 0);
assert(0);
}
 
#define compile_assert(ctx, cond) do { \
if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
} while (0)
 
static void
compile_free(struct fd3_compile_context *ctx)
{
tgsi_parse_free(&ctx->parser);
193,6 → 222,24
unsigned arg;
};
 
static unsigned
src_flags(struct fd3_compile_context *ctx, struct ir3_register *reg)
{
unsigned flags = 0;
 
if (regmask_get(ctx->needs_ss, reg)) {
flags |= IR3_INSTR_SS;
memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
}
 
if (regmask_get(ctx->needs_sy, reg)) {
flags |= IR3_INSTR_SY;
memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
}
 
return flags;
}
 
static struct ir3_register *
add_dst_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
const struct tgsi_dst_register *dst, unsigned chan)
205,9 → 252,8
num = dst->Index + ctx->base_reg[dst->File];
break;
default:
DBG("unsupported dst register file: %s",
compile_error(ctx, "unsupported dst register file: %s\n",
tgsi_file_name(dst->File));
assert(0);
break;
}
 
234,14 → 280,17
flags |= IR3_REG_CONST;
num = src->Index + ctx->base_reg[src->File];
break;
case TGSI_FILE_OUTPUT:
/* NOTE: we should only end up w/ OUTPUT file for things like
* clamp()'ing saturated dst instructions
*/
case TGSI_FILE_INPUT:
case TGSI_FILE_TEMPORARY:
num = src->Index + ctx->base_reg[src->File];
break;
default:
DBG("unsupported src register file: %s",
compile_error(ctx, "unsupported src register file: %s\n",
tgsi_file_name(src->File));
assert(0);
break;
}
 
254,16 → 303,8
 
reg = ir3_reg_create(instr, regid(num, chan), flags);
 
if (regmask_get(ctx->needs_ss, reg)) {
instr->flags |= IR3_INSTR_SS;
memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
}
instr->flags |= src_flags(ctx, reg);
 
if (regmask_get(ctx->needs_sy, reg)) {
instr->flags |= IR3_INSTR_SY;
memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
}
 
return reg;
}
 
285,11 → 326,11
/* Get internal-temp src/dst to use for a sequence of instructions
* generated by a single TGSI op.
*/
static void
static struct tgsi_src_register *
get_internal_temp(struct fd3_compile_context *ctx,
struct tgsi_dst_register *tmp_dst,
struct tgsi_src_register *tmp_src)
struct tgsi_dst_register *tmp_dst)
{
struct tgsi_src_register *tmp_src;
int n;
 
tmp_dst->File = TGSI_FILE_TEMPORARY;
299,25 → 340,80
 
/* assign next temporary: */
n = ctx->num_internal_temps++;
compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
tmp_src = &ctx->internal_temps[n];
 
tmp_dst->Index = ctx->info.file_count[TGSI_FILE_TEMPORARY] + n;
tmp_dst->Index = ctx->info.file_max[TGSI_FILE_TEMPORARY] + n + 1;
 
src_from_dst(tmp_src, tmp_dst);
 
return tmp_src;
}
 
/* same as get_internal_temp, but w/ src.xxxx (for instructions that
* replicate their results)
*/
static void
static struct tgsi_src_register *
get_internal_temp_repl(struct fd3_compile_context *ctx,
struct tgsi_dst_register *tmp_dst,
struct tgsi_src_register *tmp_src)
struct tgsi_dst_register *tmp_dst)
{
get_internal_temp(ctx, tmp_dst, tmp_src);
struct tgsi_src_register *tmp_src =
get_internal_temp(ctx, tmp_dst);
tmp_src->SwizzleX = tmp_src->SwizzleY =
tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
return tmp_src;
}
 
static inline bool
is_const(struct tgsi_src_register *src)
{
return (src->File == TGSI_FILE_CONSTANT) ||
(src->File == TGSI_FILE_IMMEDIATE);
}
 
static type_t
get_ftype(struct fd3_compile_context *ctx)
{
return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
}
 
static type_t
get_utype(struct fd3_compile_context *ctx)
{
return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
}
 
static unsigned
src_swiz(struct tgsi_src_register *src, int chan)
{
switch (chan) {
case 0: return src->SwizzleX;
case 1: return src->SwizzleY;
case 2: return src->SwizzleZ;
case 3: return src->SwizzleW;
}
assert(0);
return 0;
}
 
/* for instructions that cannot take a const register as src, if needed
* generate a move to temporary gpr:
*/
static struct tgsi_src_register *
get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
{
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register *tmp_src;
 
compile_assert(ctx, is_const(src));
 
tmp_src = get_internal_temp(ctx, &tmp_dst);
 
create_mov(ctx, &tmp_dst, src);
 
return tmp_src;
}
 
static void
get_immediate(struct fd3_compile_context *ctx,
struct tgsi_src_register *reg, uint32_t val)
365,30 → 461,11
reg->SwizzleW = swiz2tgsi[swiz];
}
 
static type_t
get_type(struct fd3_compile_context *ctx)
{
return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
}
 
static unsigned
src_swiz(struct tgsi_src_register *src, int chan)
{
switch (chan) {
case 0: return src->SwizzleX;
case 1: return src->SwizzleY;
case 2: return src->SwizzleZ;
case 3: return src->SwizzleW;
}
assert(0);
return 0;
}
 
static void
create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
struct tgsi_src_register *src)
{
type_t type_mov = get_type(ctx);
type_t type_mov = get_ftype(ctx);
unsigned i;
 
for (i = 0; i < 4; i++) {
404,9 → 481,37
ir3_instr_create(ctx->ir, 0, OPC_NOP);
}
}
}
 
static void
create_clamp(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
struct tgsi_src_register *minval, struct tgsi_src_register *maxval)
{
struct ir3_instruction *instr;
struct tgsi_src_register src;
 
src_from_dst(&src, dst);
 
instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
vectorize(ctx, instr, dst, 2, &src, 0, minval, 0);
 
instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
vectorize(ctx, instr, dst, 2, &src, 0, maxval, 0);
}
 
static void
create_clamp_imm(struct fd3_compile_context *ctx,
struct tgsi_dst_register *dst,
uint32_t minval, uint32_t maxval)
{
struct tgsi_src_register minconst, maxconst;
 
get_immediate(ctx, &minconst, minval);
get_immediate(ctx, &maxconst, maxval);
 
create_clamp(ctx, dst, &minconst, &maxconst);
}
 
static struct tgsi_dst_register *
get_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst)
{
415,7 → 520,7
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
struct tgsi_src_register *src = &inst->Src[i].Register;
if ((src->File == dst->File) && (src->Index == dst->Index)) {
get_internal_temp(ctx, &ctx->tmp_dst, &ctx->tmp_src);
ctx->tmp_src = get_internal_temp(ctx, &ctx->tmp_dst);
ctx->tmp_dst.WriteMask = dst->WriteMask;
dst = &ctx->tmp_dst;
break;
430,7 → 535,7
{
/* if necessary, add mov back into original dst: */
if (dst != &inst->Dst[0].Register) {
create_mov(ctx, &inst->Dst[0].Register, &ctx->tmp_src);
create_mov(ctx, &inst->Dst[0].Register, ctx->tmp_src);
}
}
 
478,6 → 583,7
cur->regs[j+1]->num =
regid(cur->regs[j+1]->num >> 2,
src_swiz(src, i));
cur->flags |= src_flags(ctx, cur->regs[j+1]);
}
va_end(ap);
}
496,6 → 602,15
* native instructions:
*/
 
static inline void
get_swiz(unsigned *swiz, struct tgsi_src_register *src)
{
swiz[0] = src->SwizzleX;
swiz[1] = src->SwizzleY;
swiz[2] = src->SwizzleZ;
swiz[3] = src->SwizzleW;
}
 
static void
trans_dotp(const struct instr_translater *t,
struct fd3_compile_context *ctx,
503,39 → 618,35
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register *tmp_src;
struct tgsi_dst_register *dst = &inst->Dst[0].Register;
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
unsigned swiz0[] = { src0->SwizzleX, src0->SwizzleY, src0->SwizzleZ, src0->SwizzleW };
unsigned swiz1[] = { src1->SwizzleX, src1->SwizzleY, src1->SwizzleZ, src1->SwizzleW };
unsigned swiz0[4];
unsigned swiz1[4];
opc_t opc_mad = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
unsigned n = t->arg; /* number of components */
unsigned i;
unsigned i, swapped = 0;
 
get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
 
/* Blob compiler never seems to use a const in src1 position for
* mad.*, although there does seem (according to disassembler
* hidden in libllvm-a3xx.so) to be a bit to indicate that src1
* is a const. Not sure if this is a hw bug, or simply that the
* disassembler lies.
/* in particular, can't handle const for src1 for cat3/mad:
*/
if ((src1->File == TGSI_FILE_IMMEDIATE) ||
(src1->File == TGSI_FILE_CONSTANT)) {
if (is_const(src1)) {
if (!is_const(src0)) {
struct tgsi_src_register *tmp;
tmp = src0;
src0 = src1;
src1 = tmp;
swapped = 1;
} else {
src0 = get_unconst(ctx, src0);
}
}
 
/* the mov to tmp unswizzles src1, so now we have tmp.xyzw:
*/
for (i = 0; i < 4; i++)
swiz1[i] = i;
get_swiz(swiz0, src0);
get_swiz(swiz1, src1);
 
/* the first mul.f will clobber tmp.x, but that is ok
* because after that point we no longer need tmp.x:
*/
create_mov(ctx, &tmp_dst, src1);
src1 = &tmp_src;
}
 
instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, src0, swiz0[0]);
548,31 → 659,29
add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, src0, swiz0[i]);
add_src_reg(ctx, instr, src1, swiz1[i]);
add_src_reg(ctx, instr, &tmp_src, 0);
add_src_reg(ctx, instr, tmp_src, 0);
}
 
/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
if (t->tgsi_opc == TGSI_OPCODE_DPH) {
ir3_instr_create(ctx->ir, 0, OPC_NOP);
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
 
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
add_dst_reg(ctx, instr, &tmp_dst, 0);
if (swapped)
add_src_reg(ctx, instr, src0, swiz0[i]);
else
add_src_reg(ctx, instr, src1, swiz1[i]);
add_src_reg(ctx, instr, &tmp_src, 0);
add_src_reg(ctx, instr, tmp_src, 0);
 
n++;
}
 
ir3_instr_create(ctx->ir, 0, OPC_NOP);
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 2;
 
/* pad out to multiple of 4 scalar instructions: */
for (i = 2 * n; i % 4; i++) {
ir3_instr_create(ctx->ir, 0, OPC_NOP);
create_mov(ctx, dst, tmp_src);
}
 
create_mov(ctx, dst, &tmp_src);
}
 
/* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
static void
trans_lrp(const struct instr_translater *t,
581,37 → 690,39
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst1, tmp_dst2;
struct tgsi_src_register tmp_src1, tmp_src2;
struct tgsi_src_register *tmp_src1, *tmp_src2;
struct tgsi_src_register tmp_const;
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
 
get_internal_temp(ctx, &tmp_dst1, &tmp_src1);
get_internal_temp(ctx, &tmp_dst2, &tmp_src2);
if (is_const(src0) && is_const(src1))
src0 = get_unconst(ctx, src0);
 
tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
 
get_immediate(ctx, &tmp_const, fui(1.0));
 
/* tmp1 = (a * b) */
instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
vectorize(ctx, instr, &tmp_dst1, 2,
&inst->Src[0].Register, 0,
&inst->Src[1].Register, 0);
vectorize(ctx, instr, &tmp_dst1, 2, src0, 0, src1, 0);
 
/* tmp2 = (1 - a) */
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
vectorize(ctx, instr, &tmp_dst2, 2,
&tmp_const, 0,
&inst->Src[0].Register, IR3_REG_NEGATE);
vectorize(ctx, instr, &tmp_dst2, 2, &tmp_const, 0,
src0, IR3_REG_NEGATE);
 
/* tmp2 = tmp2 * c */
instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
vectorize(ctx, instr, &tmp_dst2, 2,
&tmp_src2, 0,
tmp_src2, 0,
&inst->Src[2].Register, 0);
 
/* dst = tmp1 + tmp2 */
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
vectorize(ctx, instr, &inst->Dst[0].Register, 2,
&tmp_src1, 0,
&tmp_src2, 0);
tmp_src1, 0,
tmp_src2, 0);
}
 
/* FRC(x) = x - FLOOR(x) */
622,9 → 733,9
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register *tmp_src;
 
get_internal_temp(ctx, &tmp_dst, &tmp_src);
tmp_src = get_internal_temp(ctx, &tmp_dst);
 
/* tmp = FLOOR(x) */
instr = ir3_instr_create(ctx->ir, 2, OPC_FLOOR_F);
635,7 → 746,7
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
vectorize(ctx, instr, &inst->Dst[0].Register, 2,
&inst->Src[0].Register, 0,
&tmp_src, IR3_REG_NEGATE);
tmp_src, IR3_REG_NEGATE);
}
 
/* POW(a,b) = EXP2(b * LOG2(a)) */
647,12 → 758,12
struct ir3_instruction *instr;
struct ir3_register *r;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register *tmp_src;
struct tgsi_dst_register *dst = &inst->Dst[0].Register;
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
 
get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
 
/* log2 Rtmp, Rsrc0 */
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
659,12 → 770,12
instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
r = add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, src0, src0->SwizzleX);
regmask_set(ctx->needs_ss, r);
regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
 
/* mul.f Rtmp, Rtmp, Rsrc1 */
instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, &tmp_src, 0);
add_src_reg(ctx, instr, tmp_src, 0);
add_src_reg(ctx, instr, src1, src1->SwizzleX);
 
/* blob compiler seems to ensure there are at least 6 instructions
676,10 → 787,10
/* exp2 Rdst, Rtmp */
instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
r = add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, &tmp_src, 0);
regmask_set(ctx->needs_ss, r);
add_src_reg(ctx, instr, tmp_src, 0);
regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
 
create_mov(ctx, dst, &tmp_src);
create_mov(ctx, dst, tmp_src);
}
 
/* texture fetch/sample instructions: */
690,8 → 801,6
{
struct ir3_register *r;
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register *coord = &inst->Src[0].Register;
struct tgsi_src_register *samp = &inst->Src[1].Register;
unsigned tex = inst->Texture.Texture;
711,7 → 820,7
flags |= IR3_INSTR_P;
break;
default:
assert(0);
compile_assert(ctx, 0);
break;
}
 
726,10 → 835,13
*/
for (i = 1; (i < 4) && (order[i] >= 0); i++) {
if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i])) {
type_t type_mov = get_type(ctx);
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register *tmp_src;
 
type_t type_mov = get_ftype(ctx);
 
/* need to move things around: */
get_internal_temp(ctx, &tmp_dst, &tmp_src);
tmp_src = get_internal_temp(ctx, &tmp_dst);
 
for (j = 0; (j < 4) && (order[j] >= 0); j++) {
instr = ir3_instr_create(ctx->ir, 1, 0);
740,7 → 852,7
src_swiz(coord, order[j]));
}
 
coord = &tmp_src;
coord = tmp_src;
 
if (j < 4)
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 4 - j - 1;
750,7 → 862,7
}
 
instr = ir3_instr_create(ctx->ir, 5, t->opc);
instr->cat5.type = get_type(ctx);
instr->cat5.type = get_ftype(ctx);
instr->cat5.samp = samp->Index;
instr->cat5.tex = samp->Index;
instr->flags |= flags;
760,10 → 872,42
 
add_src_reg(ctx, instr, coord, coord->SwizzleX);
 
regmask_set(ctx->needs_sy, r);
regmask_set(ctx->needs_sy, r, r->wrmask);
}
 
/* CMP(a,b,c) = (a < 0) ? b : c */
/*
* SEQ(a,b) = (a == b) ? 1.0 : 0.0
* cmps.f.eq tmp0, b, a
* cov.u16f16 dst, tmp0
*
* SNE(a,b) = (a != b) ? 1.0 : 0.0
* cmps.f.eq tmp0, b, a
* add.s tmp0, tmp0, -1
* sel.f16 dst, {0.0}, tmp0, {1.0}
*
* SGE(a,b) = (a >= b) ? 1.0 : 0.0
* cmps.f.ge tmp0, a, b
* cov.u16f16 dst, tmp0
*
* SLE(a,b) = (a <= b) ? 1.0 : 0.0
* cmps.f.ge tmp0, b, a
* cov.u16f16 dst, tmp0
*
* SGT(a,b) = (a > b) ? 1.0 : 0.0
* cmps.f.ge tmp0, b, a
* add.s tmp0, tmp0, -1
* sel.f16 dst, {0.0}, tmp0, {1.0}
*
* SLT(a,b) = (a < b) ? 1.0 : 0.0
* cmps.f.ge tmp0, a, b
* add.s tmp0, tmp0, -1
* sel.f16 dst, {0.0}, tmp0, {1.0}
*
* CMP(a,b,c) = (a < 0.0) ? b : c
* cmps.f.ge tmp0, a, {0.0}
* add.s tmp0, tmp0, -1
* sel.f16 dst, c, tmp0, b
*/
static void
trans_cmp(const struct instr_translater *t,
struct fd3_compile_context *ctx,
771,36 → 915,95
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct tgsi_src_register constval;
/* final instruction uses original src1 and src2, so we need get_dst() */
struct tgsi_src_register *tmp_src;
struct tgsi_src_register constval0, constval1;
/* final instruction for CMP() uses orig src1 and src2: */
struct tgsi_dst_register *dst = get_dst(ctx, inst);
struct tgsi_src_register *a0, *a1;
unsigned condition;
 
get_internal_temp(ctx, &tmp_dst, &tmp_src);
tmp_src = get_internal_temp(ctx, &tmp_dst);
 
/* cmps.f.ge tmp, src0, 0.0 */
switch (t->tgsi_opc) {
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SNE:
a0 = &inst->Src[1].Register; /* b */
a1 = &inst->Src[0].Register; /* a */
condition = IR3_COND_EQ;
break;
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_SLT:
a0 = &inst->Src[0].Register; /* a */
a1 = &inst->Src[1].Register; /* b */
condition = IR3_COND_GE;
break;
case TGSI_OPCODE_SLE:
case TGSI_OPCODE_SGT:
a0 = &inst->Src[1].Register; /* b */
a1 = &inst->Src[0].Register; /* a */
condition = IR3_COND_GE;
break;
case TGSI_OPCODE_CMP:
get_immediate(ctx, &constval0, fui(0.0));
a0 = &inst->Src[0].Register; /* a */
a1 = &constval0; /* {0.0} */
condition = IR3_COND_GE;
break;
default:
compile_assert(ctx, 0);
return;
}
 
if (is_const(a0) && is_const(a1))
a0 = get_unconst(ctx, a0);
 
/* cmps.f.ge tmp, a0, a1 */
instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
instr->cat2.condition = IR3_COND_GE;
get_immediate(ctx, &constval, fui(0.0));
vectorize(ctx, instr, &tmp_dst, 2,
&inst->Src[0].Register, 0,
&constval, 0);
instr->cat2.condition = condition;
vectorize(ctx, instr, &tmp_dst, 2, a0, 0, a1, 0);
 
switch (t->tgsi_opc) {
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SGE:
case TGSI_OPCODE_SLE:
/* cov.u16f16 dst, tmp0 */
instr = ir3_instr_create(ctx->ir, 1, 0);
instr->cat1.src_type = get_utype(ctx);
instr->cat1.dst_type = get_ftype(ctx);
vectorize(ctx, instr, dst, 1, tmp_src, 0);
break;
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_SGT:
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_CMP:
/* add.s tmp, tmp, -1 */
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
instr->repeat = 3;
add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, &tmp_src, 0);
add_src_reg(ctx, instr, tmp_src, 0)->flags |= IR3_REG_R;
ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
 
if (t->tgsi_opc == TGSI_OPCODE_CMP) {
/* sel.{f32,f16} dst, src2, tmp, src1 */
instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
OPC_SEL_F16 : OPC_SEL_F32);
vectorize(ctx, instr, &inst->Dst[0].Register, 3,
instr = ir3_instr_create(ctx->ir, 3,
ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
vectorize(ctx, instr, dst, 3,
&inst->Src[2].Register, 0,
&tmp_src, 0,
tmp_src, 0,
&inst->Src[1].Register, 0);
} else {
get_immediate(ctx, &constval0, fui(0.0));
get_immediate(ctx, &constval1, fui(1.0));
/* sel.{f32,f16} dst, {0.0}, tmp0, {1.0} */
instr = ir3_instr_create(ctx->ir, 3,
ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
vectorize(ctx, instr, dst, 3,
&constval0, 0, tmp_src, 0, &constval1, 0);
}
 
break;
}
 
put_dst(ctx, inst, dst);
}
 
858,10 → 1061,13
 
get_immediate(ctx, &constval, fui(0.0));
 
if (is_const(src))
src = get_unconst(ctx, src);
 
instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
ir3_reg_create(instr, regid(REG_P0, 0), 0);
add_src_reg(ctx, instr, src, src->SwizzleX);
add_src_reg(ctx, instr, &constval, constval.SwizzleX);
add_src_reg(ctx, instr, src, src->SwizzleX);
instr->cat2.condition = IR3_COND_EQ;
 
instr = ir3_instr_create(ctx->ir, 0, OPC_BR);
939,16 → 1145,12
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
struct ir3_instruction *instr;
unsigned src0_flags = 0;
 
instr = ir3_instr_create(ctx->ir, 2, t->opc);
 
switch (t->tgsi_opc) {
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
instr->cat2.condition = t->arg;
break;
case TGSI_OPCODE_ABS:
src0_flags = IR3_REG_ABS;
break;
970,13 → 1172,15
case OPC_SETRM:
case OPC_CBITS_B:
/* these only have one src reg */
vectorize(ctx, instr, dst, 1,
&inst->Src[0].Register, src0_flags);
instr = ir3_instr_create(ctx->ir, 2, t->opc);
vectorize(ctx, instr, dst, 1, src0, src0_flags);
break;
default:
vectorize(ctx, instr, dst, 2,
&inst->Src[0].Register, src0_flags,
&inst->Src[1].Register, 0);
if (is_const(src0) && is_const(src1))
src0 = get_unconst(ctx, src0);
 
instr = ir3_instr_create(ctx->ir, 2, t->opc);
vectorize(ctx, instr, dst, 2, src0, src0_flags, src1, 0);
break;
}
 
983,6 → 1187,23
put_dst(ctx, inst, dst);
}
 
static bool is_mad(opc_t opc)
{
switch (opc) {
case OPC_MAD_U16:
case OPC_MADSH_U16:
case OPC_MAD_S16:
case OPC_MADSH_M16:
case OPC_MAD_U24:
case OPC_MAD_S24:
case OPC_MAD_F16:
case OPC_MAD_F32:
return true;
default:
return false;
}
}
 
static void
instr_cat3(const struct instr_translater *t,
struct fd3_compile_context *ctx,
989,29 → 1210,27
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct ir3_instruction *instr;
 
/* Blob compiler never seems to use a const in src1 position..
* although there does seem (according to disassembler hidden
* in libllvm-a3xx.so) to be a bit to indicate that src1 is a
* const. Not sure if this is a hw bug, or simply that the
* disassembler lies.
/* in particular, can't handle const for src1 for cat3..
* for mad, we can swap first two src's if needed:
*/
if ((src1->File == TGSI_FILE_CONSTANT) ||
(src1->File == TGSI_FILE_IMMEDIATE)) {
get_internal_temp(ctx, &tmp_dst, &tmp_src);
create_mov(ctx, &tmp_dst, src1);
src1 = &tmp_src;
if (is_const(src1)) {
if (is_mad(t->opc) && !is_const(src0)) {
struct tgsi_src_register *tmp;
tmp = src0;
src0 = src1;
src1 = tmp;
} else {
src0 = get_unconst(ctx, src0);
}
}
 
instr = ir3_instr_create(ctx->ir, 3,
ctx->so->half_precision ? t->hopc : t->opc);
vectorize(ctx, instr, dst, 3,
&inst->Src[0].Register, 0,
src1, 0,
vectorize(ctx, instr, dst, 3, src0, 0, src1, 0,
&inst->Src[2].Register, 0);
put_dst(ctx, inst, dst);
}
1022,15 → 1241,20
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
struct tgsi_src_register *src = &inst->Src[0].Register;
struct ir3_instruction *instr;
 
/* seems like blob compiler avoids const as src.. */
if (is_const(src))
src = get_unconst(ctx, src);
 
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
instr = ir3_instr_create(ctx->ir, 4, t->opc);
 
vectorize(ctx, instr, dst, 1,
&inst->Src[0].Register, 0);
vectorize(ctx, instr, dst, 1, src, 0);
 
regmask_set(ctx->needs_ss, instr->regs[0]);
regmask_set(ctx->needs_ss, instr->regs[0],
inst->Dst[0].Register.WriteMask);
 
put_dst(ctx, inst, dst);
}
1051,12 → 1275,11
INSTR(DPH, trans_dotp, .arg = 3), /* almost like DP3 */
INSTR(MIN, instr_cat2, .opc = OPC_MIN_F),
INSTR(MAX, instr_cat2, .opc = OPC_MAX_F),
INSTR(SLT, instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_LT),
INSTR(SGE, instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_GE),
INSTR(MAD, instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
INSTR(LRP, trans_lrp),
INSTR(FRC, trans_frac),
INSTR(FLR, instr_cat2, .opc = OPC_FLOOR_F),
INSTR(ARL, instr_cat2, .opc = OPC_FLOOR_F),
INSTR(EX2, instr_cat4, .opc = OPC_EXP2),
INSTR(LG2, instr_cat4, .opc = OPC_LOG2),
INSTR(POW, trans_pow),
1065,6 → 1288,12
INSTR(SIN, instr_cat4, .opc = OPC_COS),
INSTR(TEX, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX),
INSTR(TXP, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP),
INSTR(SGT, trans_cmp),
INSTR(SLT, trans_cmp),
INSTR(SGE, trans_cmp),
INSTR(SLE, trans_cmp),
INSTR(SNE, trans_cmp),
INSTR(SEQ, trans_cmp),
INSTR(CMP, trans_cmp),
INSTR(IF, trans_if),
INSTR(ELSE, trans_else),
1132,7 → 1361,7
unsigned name = decl->Semantic.Name;
unsigned i;
 
assert(decl->Declaration.Semantic); // TODO is this ever not true?
compile_assert(ctx, decl->Declaration.Semantic); // TODO is this ever not true?
 
DBG("decl out[%d] -> r%d", name, decl->Range.First + base); // XXX
 
1152,9 → 1381,8
so->outputs[so->outputs_count++].regid = regid(i + base, 0);
break;
default:
DBG("unknown VS semantic name: %s",
compile_error(ctx, "unknown VS semantic name: %s\n",
tgsi_semantic_names[name]);
assert(0);
}
} else {
switch (name) {
1162,9 → 1390,8
so->color_regid = regid(decl->Range.First + base, 0);
break;
default:
DBG("unknown VS semantic name: %s",
compile_error(ctx, "unknown VS semantic name: %s\n",
tgsi_semantic_names[name]);
assert(0);
}
}
}
1223,14 → 1450,23
t->fxn(t, ctx, inst);
ctx->num_internal_temps = 0;
} else {
debug_printf("unknown TGSI opc: %s\n",
compile_error(ctx, "unknown TGSI opc: %s\n",
tgsi_get_opcode_name(opc));
tgsi_dump(ctx->tokens, 0);
assert(0);
}
 
switch (inst->Instruction.Saturate) {
case TGSI_SAT_ZERO_ONE:
create_clamp_imm(ctx, &inst->Dst[0].Register,
fui(0.0), fui(1.0));
break;
case TGSI_SAT_MINUS_PLUS_ONE:
create_clamp_imm(ctx, &inst->Dst[0].Register,
fui(-1.0), fui(1.0));
break;
}
 
break;
}
default:
break;
}
1253,6 → 1489,8
 
so->ir = ir3_shader_create();
 
assert(so->ir);
 
so->color_regid = regid(63,0);
so->pos_regid = regid(63,0);
so->psize_regid = regid(63,0);