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| #ifndef GEN_RENDER_MEDIA_XML |
| #define GEN_RENDER_MEDIA_XML |
| |
| /* Autogenerated file, DO NOT EDIT manually! |
| |
| This file was generated by the rules-ng-ng headergen tool in this git repository: |
| https://github.com/olvaffe/envytools/ |
| git clone https://github.com/olvaffe/envytools.git |
| |
| Copyright (C) 2014-2015 by the following authors: |
| - Chia-I Wu <olvaffe@gmail.com> (olv) |
| |
| Permission is hereby granted, free of charge, to any person obtaining |
| a copy of this software and associated documentation files (the |
| "Software"), to deal in the Software without restriction, including |
| without limitation the rights to use, copy, modify, merge, publish, |
| distribute, sublicense, and/or sell copies of the Software, and to |
| permit persons to whom the Software is furnished to do so, subject to |
| the following conditions: |
| |
| The above copyright notice and this permission notice (including the |
| next paragraph) shall be included in all copies or substantial |
| portions of the Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| #define GEN6_INTERFACE_DESCRIPTOR_DATA__SIZE 8 |
| |
| #define GEN6_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0 |
| #define GEN6_IDRT_DW0_KERNEL_ADDR__SHIFT 6 |
| #define GEN6_IDRT_DW0_KERNEL_ADDR__SHR 6 |
| |
| #define GEN6_IDRT_DW1_SPF (0x1 << 18) |
| #define GEN6_IDRT_DW1_PRIORITY_HIGH (0x1 << 17) |
| #define GEN6_IDRT_DW1_FP_MODE_ALT (0x1 << 16) |
| #define GEN6_IDRT_DW1_ILLEGAL_CODE_EXCEPTION (0x1 << 13) |
| #define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION (0x1 << 11) |
| #define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION (0x1 << 7) |
| |
| #define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c |
| #define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2 |
| #define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK 0xffffffe0 |
| #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT 5 |
| #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR 5 |
| |
| #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK 0x0000001f |
| #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT 0 |
| |
| #define GEN6_IDRT_DW4_CURBE_READ_LEN__MASK 0xffff0000 |
| #define GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT 16 |
| #define GEN6_IDRT_DW4_CURBE_READ_OFFSET__MASK 0x0000ffff |
| #define GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT 0 |
| |
| #define GEN6_IDRT_DW5_BARRIER_ID__MASK 0x0000000f |
| #define GEN6_IDRT_DW5_BARRIER_ID__SHIFT 0 |
| |
| #define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__MASK 0xff000000 |
| #define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__SHIFT 24 |
| #define GEN7_IDRT_DW5_ROUNDING_MODE__MASK 0x00c00000 |
| #define GEN7_IDRT_DW5_ROUNDING_MODE__SHIFT 22 |
| #define GEN7_IDRT_DW5_ROUNDING_MODE_RTNE (0x0 << 22) |
| #define GEN7_IDRT_DW5_ROUNDING_MODE_RU (0x1 << 22) |
| #define GEN7_IDRT_DW5_ROUNDING_MODE_RD (0x2 << 22) |
| #define GEN7_IDRT_DW5_ROUNDING_MODE_RTZ (0x3 << 22) |
| #define GEN7_IDRT_DW5_BARRIER_ENABLE (0x1 << 21) |
| #define GEN7_IDRT_DW5_SLM_SIZE__MASK 0x001f0000 |
| #define GEN7_IDRT_DW5_SLM_SIZE__SHIFT 16 |
| #define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__MASK 0x0000ff00 |
| #define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__SHIFT 8 |
| #define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__MASK 0x000000ff |
| #define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT 0 |
| |
| #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff |
| #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 |
| |
| |
| |
| #define GEN8_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0 |
| #define GEN8_IDRT_DW0_KERNEL_ADDR__SHIFT 6 |
| #define GEN8_IDRT_DW0_KERNEL_ADDR__SHR 6 |
| |
| |
| #define GEN8_IDRT_DW2_THREAD_PREEMPTION_DISABLE (0x1 << 20) |
| #define GEN8_IDRT_DW2_DENORM__MASK 0x00080000 |
| #define GEN8_IDRT_DW2_DENORM__SHIFT 19 |
| #define GEN8_IDRT_DW2_DENORM_FTZ (0x0 << 19) |
| #define GEN8_IDRT_DW2_DENORM_RET (0x1 << 19) |
| #define GEN8_IDRT_DW2_SPF (0x1 << 18) |
| #define GEN8_IDRT_DW2_PRIORITY_HIGH (0x1 << 17) |
| #define GEN8_IDRT_DW2_FP_MODE_ALT (0x1 << 16) |
| #define GEN8_IDRT_DW2_ILLEGAL_CODE_EXCEPTION (0x1 << 13) |
| #define GEN8_IDRT_DW2_MASK_STACK_EXCEPTION (0x1 << 11) |
| #define GEN8_IDRT_DW2_SOFTWARE_EXCEPTION (0x1 << 7) |
| |
| #define GEN8_IDRT_DW3_SAMPLER_COUNT__MASK 0x0000001c |
| #define GEN8_IDRT_DW3_SAMPLER_COUNT__SHIFT 2 |
| #define GEN8_IDRT_DW3_SAMPLER_ADDR__MASK 0xffffffe0 |
| #define GEN8_IDRT_DW3_SAMPLER_ADDR__SHIFT 5 |
| #define GEN8_IDRT_DW3_SAMPLER_ADDR__SHR 5 |
| |
| #define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__MASK 0x0000001f |
| #define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__SHIFT 0 |
| |
| #define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK 0xffff0000 |
| #define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT 16 |
| |
| #define GEN8_IDRT_DW6_ROUNDING_MODE__MASK 0x00c00000 |
| #define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT 22 |
| #define GEN8_IDRT_DW6_ROUNDING_MODE_RTNE (0x0 << 22) |
| #define GEN8_IDRT_DW6_ROUNDING_MODE_RU (0x1 << 22) |
| #define GEN8_IDRT_DW6_ROUNDING_MODE_RD (0x2 << 22) |
| #define GEN8_IDRT_DW6_ROUNDING_MODE_RTZ (0x3 << 22) |
| #define GEN8_IDRT_DW6_BARRIER_ENABLE (0x1 << 21) |
| #define GEN8_IDRT_DW6_SLM_SIZE__MASK 0x001f0000 |
| #define GEN8_IDRT_DW6_SLM_SIZE__SHIFT 16 |
| #define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000000ff |
| #define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT 0 |
| |
| #define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff |
| #define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 |
| |
| #define GEN6_MEDIA_VFE_STATE__SIZE 9 |
| |
| |
| #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 |
| #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 |
| #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f |
| #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 |
| #define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 |
| #define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10 |
| #define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10 |
| |
| #define GEN6_VFE_DW2_MAX_THREADS__MASK 0xffff0000 |
| #define GEN6_VFE_DW2_MAX_THREADS__SHIFT 16 |
| #define GEN6_VFE_DW2_URB_ENTRY_COUNT__MASK 0x0000ff00 |
| #define GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT 8 |
| #define GEN6_VFE_DW2_RESET_GATEWAY_TIMER (0x1 << 7) |
| #define GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL (0x1 << 6) |
| #define GEN6_VFE_DW2_FAST_PREEMPT (0x1 << 5) |
| #define GEN7_VFE_DW2_GATEWAY_MMIO__MASK 0x00000018 |
| #define GEN7_VFE_DW2_GATEWAY_MMIO__SHIFT 3 |
| #define GEN7_VFE_DW2_GATEWAY_MMIO_NONE (0x0 << 3) |
| #define GEN7_VFE_DW2_GATEWAY_MMIO_ANY (0x2 << 3) |
| #define GEN7_VFE_DW2_GPGPU_MODE (0x1 << 2) |
| |
| #define GEN75_VFE_DW3_HALF_SLICE_DISABLE__MASK 0x00000003 |
| #define GEN75_VFE_DW3_HALF_SLICE_DISABLE__SHIFT 0 |
| #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_NONE 0x0 |
| #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_23 0x1 |
| #define GEN75_VFE_DW3_HALF_SLICE_DISABLE_123 0x3 |
| |
| #define GEN6_VFE_DW4_URB_ENTRY_SIZE__MASK 0xffff0000 |
| #define GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT 16 |
| #define GEN6_VFE_DW4_CURBE_SIZE__MASK 0x0000ffff |
| #define GEN6_VFE_DW4_CURBE_SIZE__SHIFT 0 |
| |
| #define GEN6_VFE_DW5_SCOREBOARD_ENABLE (0x1 << 31) |
| #define GEN6_VFE_DW5_SCOREBOARD_TYPE__MASK 0x40000000 |
| #define GEN6_VFE_DW5_SCOREBOARD_TYPE__SHIFT 30 |
| #define GEN6_VFE_DW5_SCOREBOARD_TYPE_STALLING (0x0 << 30) |
| #define GEN6_VFE_DW5_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30) |
| #define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK 0x000000ff |
| #define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT 0 |
| |
| |
| |
| |
| #define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 |
| #define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 |
| #define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f |
| #define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 |
| #define GEN8_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 |
| #define GEN8_VFE_DW1_SCRATCH_ADDR__SHIFT 10 |
| #define GEN8_VFE_DW1_SCRATCH_ADDR__SHR 10 |
| |
| |
| #define GEN8_VFE_DW3_MAX_THREADS__MASK 0xffff0000 |
| #define GEN8_VFE_DW3_MAX_THREADS__SHIFT 16 |
| #define GEN8_VFE_DW3_URB_ENTRY_COUNT__MASK 0x0000ff00 |
| #define GEN8_VFE_DW3_URB_ENTRY_COUNT__SHIFT 8 |
| #define GEN8_VFE_DW3_RESET_GATEWAY_TIMER (0x1 << 7) |
| #define GEN8_VFE_DW3_BYPASS_GATEWAY_CONTROL (0x1 << 6) |
| |
| #define GEN8_VFE_DW4_HALF_SLICE_DISABLE__MASK 0x00000003 |
| #define GEN8_VFE_DW4_HALF_SLICE_DISABLE__SHIFT 0 |
| #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_NONE 0x0 |
| #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_23 0x1 |
| #define GEN8_VFE_DW4_HALF_SLICE_DISABLE_123 0x3 |
| |
| #define GEN8_VFE_DW5_URB_ENTRY_SIZE__MASK 0xffff0000 |
| #define GEN8_VFE_DW5_URB_ENTRY_SIZE__SHIFT 16 |
| #define GEN8_VFE_DW5_CURBE_SIZE__MASK 0x0000ffff |
| #define GEN8_VFE_DW5_CURBE_SIZE__SHIFT 0 |
| |
| #define GEN8_VFE_DW6_SCOREBOARD_ENABLE (0x1 << 31) |
| #define GEN8_VFE_DW6_SCOREBOARD_TYPE__MASK 0x40000000 |
| #define GEN8_VFE_DW6_SCOREBOARD_TYPE__SHIFT 30 |
| #define GEN8_VFE_DW6_SCOREBOARD_TYPE_STALLING (0x0 << 30) |
| #define GEN8_VFE_DW6_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30) |
| #define GEN8_VFE_DW6_SCOREBOARD_MASK__MASK 0x000000ff |
| #define GEN8_VFE_DW6_SCOREBOARD_MASK__SHIFT 0 |
| |
| |
| #define GEN6_MEDIA_CURBE_LOAD__SIZE 4 |
| |
| |
| |
| #define GEN6_CURBE_LOAD_DW2_LEN__MASK 0x0001ffff |
| #define GEN6_CURBE_LOAD_DW2_LEN__SHIFT 0 |
| |
| #define GEN6_CURBE_LOAD_DW3_ADDR__MASK 0xffffffe0 |
| #define GEN6_CURBE_LOAD_DW3_ADDR__SHIFT 5 |
| #define GEN6_CURBE_LOAD_DW3_ADDR__SHR 5 |
| |
| #define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE 4 |
| |
| |
| |
| #define GEN6_IDRT_LOAD_DW2_LEN__MASK 0x0001ffff |
| #define GEN6_IDRT_LOAD_DW2_LEN__SHIFT 0 |
| |
| #define GEN6_IDRT_LOAD_DW3_ADDR__MASK 0xffffffe0 |
| #define GEN6_IDRT_LOAD_DW3_ADDR__SHIFT 5 |
| #define GEN6_IDRT_LOAD_DW3_ADDR__SHR 5 |
| |
| #define GEN6_MEDIA_STATE_FLUSH__SIZE 2 |
| |
| |
| #define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__MASK 0x00ff0000 |
| #define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__SHIFT 16 |
| #define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__MASK 0x0000ffff |
| #define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__SHIFT 0 |
| |
| #define GEN7_MEDIA_FLUSH_DW1_DISABLE_PREEMPTION (0x1 << 8) |
| #define GEN75_MEDIA_FLUSH_DW1_FLUSH_TO_GO (0x1 << 7) |
| #define GEN7_MEDIA_FLUSH_DW1_WATERMARK_REQUIRED (0x1 << 6) |
| #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK 0x0000003f |
| #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT 0 |
| |
| #define GEN7_GPGPU_WALKER__SIZE 15 |
| |
| #define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) |
| #define GEN7_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) |
| |
| #define GEN7_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f |
| #define GEN7_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 |
| |
| #define GEN7_GPGPU_DW2_SIMD_SIZE__MASK 0xc0000000 |
| #define GEN7_GPGPU_DW2_SIMD_SIZE__SHIFT 30 |
| #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8 (0x0 << 30) |
| #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16 (0x1 << 30) |
| #define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD32 (0x2 << 30) |
| #define GEN7_GPGPU_DW2_THREAD_MAX_Z__MASK 0x003f0000 |
| #define GEN7_GPGPU_DW2_THREAD_MAX_Z__SHIFT 16 |
| #define GEN7_GPGPU_DW2_THREAD_MAX_Y__MASK 0x00003f00 |
| #define GEN7_GPGPU_DW2_THREAD_MAX_Y__SHIFT 8 |
| #define GEN7_GPGPU_DW2_THREAD_MAX_X__MASK 0x0000003f |
| #define GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT 0 |
| |
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| |
| #define GEN8_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) |
| #define GEN8_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) |
| |
| #define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f |
| #define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 |
| |
| |
| #define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK 0xffffffe0 |
| #define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT 5 |
| #define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHR 5 |
| |
| #define GEN8_GPGPU_DW4_SIMD_SIZE__MASK 0xc0000000 |
| #define GEN8_GPGPU_DW4_SIMD_SIZE__SHIFT 30 |
| #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD8 (0x0 << 30) |
| #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD16 (0x1 << 30) |
| #define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD32 (0x2 << 30) |
| #define GEN8_GPGPU_DW4_THREAD_MAX_Z__MASK 0x003f0000 |
| #define GEN8_GPGPU_DW4_THREAD_MAX_Z__SHIFT 16 |
| #define GEN8_GPGPU_DW4_THREAD_MAX_Y__MASK 0x00003f00 |
| #define GEN8_GPGPU_DW4_THREAD_MAX_Y__SHIFT 8 |
| #define GEN8_GPGPU_DW4_THREAD_MAX_X__MASK 0x0000003f |
| #define GEN8_GPGPU_DW4_THREAD_MAX_X__SHIFT 0 |
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| #endif /* GEN_RENDER_MEDIA_XML */ |