/drivers/video/drm/include/types.h |
---|
133,6 → 133,7 |
void* memcpy(void *s1, const void *s2, size_t n); |
void* memset(void *s, int c, size_t n); |
size_t strlen(const char *s); |
char *strcpy(char *s1, const char *s2); |
char *strncpy (char *dst, const char *src, size_t len); |
void *malloc(size_t size); |
/drivers/video/drm/radeon/atombios_crtc.c |
---|
337,7 → 337,7 |
// return -EINVAL; |
//} |
fb_location = rdev->mc.vram_location; |
fb_location = 0; //rdev->mc.vram_location; |
dbgprintf("fb_location %x\n", fb_location); |
dbgprintf("bpp %x\n", crtc->fb->bits_per_pixel); |
708,3 → 708,5 |
#endif |
WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); |
} |
/drivers/video/drm/radeon/r100.c |
---|
46,7 → 46,6 |
void r100_gpu_wait_for_vsync2(struct radeon_device *rdev); |
int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
#if 0 |
/* |
* PCI GART |
*/ |
105,6 → 104,7 |
WREG32(RADEON_AIC_HI_ADDR, 0); |
} |
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
{ |
if (i < 0 || i > rdev->gart.num_gpu_pages) { |
132,10 → 132,10 |
uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl; |
/* FIXME: is this function correct for rs100,rs200,rs300 ? */ |
// if (r100_gui_wait_for_idle(rdev)) { |
// printk(KERN_WARNING "Failed to wait GUI idle while " |
// "programming pipes. Bad things might happen.\n"); |
// } |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
/* stop display and memory access */ |
ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL); |
168,10 → 168,10 |
uint32_t tmp; |
int r; |
r = r100_debugfs_mc_info_init(rdev); |
if (r) { |
DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); |
} |
// r = r100_debugfs_mc_info_init(rdev); |
// if (r) { |
// DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); |
// } |
/* Write VRAM size in case we are limiting it */ |
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
206,9 → 206,9 |
{ |
int r; |
if (r100_debugfs_rbbm_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
} |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
r100_gpu_init(rdev); |
/* Disable gart which also disable out of gart access */ |
245,11 → 245,10 |
void r100_mc_fini(struct radeon_device *rdev) |
{ |
r100_pci_gart_disable(rdev); |
radeon_gart_table_ram_free(rdev); |
radeon_gart_fini(rdev); |
// radeon_gart_table_ram_free(rdev); |
// radeon_gart_fini(rdev); |
} |
/* |
* Fence emission |
*/ |
268,8 → 267,7 |
radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
} |
#endif |
#if 0 |
/* |
* Writeback |
*/ |
317,7 → 315,6 |
} |
#if 0 |
int r100_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
391,6 → 388,7 |
return r; |
} |
#endif |
/* |
* CP |
412,14 → 410,10 |
radeon_ring_unlock_commit(rdev); |
} |
#endif |
static void r100_cp_load_microcode(struct radeon_device *rdev) |
{ |
int i; |
dbgprintf("%s\n",__FUNCTION__); |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
596,7 → 590,6 |
return 0; |
} |
#if 0 |
void r100_cp_fini(struct radeon_device *rdev) |
{ |
619,7 → 612,6 |
} |
} |
#endif |
int r100_cp_reset(struct radeon_device *rdev) |
{ |
1047,6 → 1039,7 |
return 0; |
} |
#endif |
/* |
* Global GPU functions |
1066,7 → 1059,6 |
} |
} |
#endif |
/* Wait for vertical sync on primary CRTC */ |
1212,8 → 1204,6 |
return -1; |
} |
#if 0 |
int r100_gpu_reset(struct radeon_device *rdev) |
{ |
uint32_t status; |
1306,8 → 1296,6 |
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
} |
#endif |
/* |
* Indirect registers accessor |
*/ |
/drivers/video/drm/radeon/r300.c |
---|
173,10 → 173,10 |
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
return rv370_pcie_gart_enable(rdev); |
} |
// return r100_pci_gart_enable(rdev); |
return r100_pci_gart_enable(rdev); |
} |
#if 0 |
/* |
* MC |
*/ |
184,9 → 184,9 |
{ |
int r; |
if (r100_debugfs_rbbm_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
} |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
r300_gpu_init(rdev); |
r100_pci_gart_disable(rdev); |
264,6 → 264,8 |
} |
#if 0 |
/* |
* Global GPU functions |
*/ |
311,6 → 313,8 |
return r; |
} |
#endif |
void r300_ring_start(struct radeon_device *rdev) |
{ |
unsigned gb_tile_config; |
714,6 → 718,7 |
} |
#if 0 |
/* |
* CS functions |
*/ |
968,6 → 973,8 |
} |
} |
#endif |
static const unsigned r300_reg_safe_bm[159] = { |
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
1011,6 → 1018,8 |
0x0003FC01, 0xFFFFFFF8, 0xFE800B19, |
}; |
#if 0 |
static int r300_packet0_check(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
unsigned idx, unsigned reg) |
1524,6 → 1533,8 |
return 0; |
} |
#endif |
int r300_init(struct radeon_device *rdev) |
{ |
rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
1532,4 → 1543,3 |
} |
#endif |
/drivers/video/drm/radeon/r520.c |
---|
239,82 → 239,7 |
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
} |
/* |
* Global GPU functions |
*/ |
void rs600_disable_vga(struct radeon_device *rdev) |
{ |
unsigned tmp; |
dbgprintf("%s\n",__FUNCTION__); |
WREG32(0x330, 0); |
WREG32(0x338, 0); |
tmp = RREG32(0x300); |
tmp &= ~(3 << 16); |
WREG32(0x300, tmp); |
WREG32(0x308, (1 << 8)); |
WREG32(0x310, rdev->mc.vram_location); |
WREG32(0x594, 0); |
} |
void r420_pipes_init(struct radeon_device *rdev) |
{ |
unsigned tmp; |
unsigned gb_pipe_select; |
unsigned num_pipes; |
dbgprintf("%s\n",__FUNCTION__); |
/* GA_ENHANCE workaround TCL deadlock issue */ |
WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); |
/* get max number of pipes */ |
gb_pipe_select = RREG32(0x402C); |
num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
rdev->num_gb_pipes = num_pipes; |
tmp = 0; |
switch (num_pipes) { |
default: |
/* force to 1 pipe */ |
num_pipes = 1; |
case 1: |
tmp = (0 << 1); |
break; |
case 2: |
tmp = (3 << 1); |
break; |
case 3: |
tmp = (6 << 1); |
break; |
case 4: |
tmp = (7 << 1); |
break; |
} |
WREG32(0x42C8, (1 << num_pipes) - 1); |
/* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
tmp |= (1 << 4) | (1 << 0); |
WREG32(0x4018, tmp); |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = RREG32(0x170C); |
WREG32(0x170C, tmp | (1 << 31)); |
WREG32(R300_RB2D_DSTCACHE_MODE, |
RREG32(R300_RB2D_DSTCACHE_MODE) | |
R300_DC_AUTOFLUSH_ENABLE | |
R300_DC_DC_DISABLE_IGNORE_PE); |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes); |
} |
int radeon_agp_init(struct radeon_device *rdev) |
{ |
434,38 → 359,8 |
} |
void rs600_mc_disable_clients(struct radeon_device *rdev) |
{ |
unsigned tmp; |
dbgprintf("%s\n",__FUNCTION__); |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = RREG32(AVIVO_D1VGA_CONTROL); |
WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
tmp = RREG32(AVIVO_D2VGA_CONTROL); |
WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
tmp = RREG32(AVIVO_D1CRTC_CONTROL); |
WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
/* make sure all previous write got through */ |
tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
mdelay(1); |
dbgprintf("done\n"); |
} |
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
/drivers/video/drm/radeon/r600.c |
---|
0,0 → 1,169 |
/* |
* Copyright 2008 Advanced Micro Devices, Inc. |
* Copyright 2008 Red Hat Inc. |
* Copyright 2009 Jerome Glisse. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
* Alex Deucher |
* Jerome Glisse |
*/ |
#include "drmP.h" |
#include "radeon_reg.h" |
#include "radeon.h" |
/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ |
void rs600_mc_disable_clients(struct radeon_device *rdev); |
/* This files gather functions specifics to: |
* r600,rv610,rv630,rv620,rv635,rv670 |
* |
* Some of these functions might be used by newer ASICs. |
*/ |
int r600_mc_wait_for_idle(struct radeon_device *rdev); |
void r600_gpu_init(struct radeon_device *rdev); |
/* |
* MC |
*/ |
int r600_mc_init(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
r600_gpu_init(rdev); |
/* setup the gart before changing location so we can ask to |
* discard unmapped mc request |
*/ |
/* FIXME: disable out of gart access */ |
tmp = rdev->mc.gtt_location / 4096; |
tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); |
tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; |
tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
rs600_mc_disable_clients(rdev); |
if (r600_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); |
tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); |
WREG32(R600_MC_VM_FB_LOCATION, tmp); |
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); |
WREG32(R600_MC_VM_AGP_TOP, tmp); |
tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); |
WREG32(R600_MC_VM_AGP_BOT, tmp); |
return 0; |
} |
void r600_mc_fini(struct radeon_device *rdev) |
{ |
/* FIXME: implement */ |
} |
/* |
* Global GPU functions |
*/ |
void r600_errata(struct radeon_device *rdev) |
{ |
rdev->pll_errata = 0; |
} |
int r600_mc_wait_for_idle(struct radeon_device *rdev) |
{ |
/* FIXME: implement */ |
return 0; |
} |
void r600_gpu_init(struct radeon_device *rdev) |
{ |
/* FIXME: implement */ |
} |
/* |
* VRAM info |
*/ |
void r600_vram_get_type(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
int chansize; |
rdev->mc.vram_width = 128; |
rdev->mc.vram_is_ddr = true; |
tmp = RREG32(R600_RAMCFG); |
if (tmp & R600_CHANSIZE_OVERRIDE) { |
chansize = 16; |
} else if (tmp & R600_CHANSIZE) { |
chansize = 64; |
} else { |
chansize = 32; |
} |
if (rdev->family == CHIP_R600) { |
rdev->mc.vram_width = 8 * chansize; |
} else if (rdev->family == CHIP_RV670) { |
rdev->mc.vram_width = 4 * chansize; |
} else if ((rdev->family == CHIP_RV610) || |
(rdev->family == CHIP_RV620)) { |
rdev->mc.vram_width = chansize; |
} else if ((rdev->family == CHIP_RV630) || |
(rdev->family == CHIP_RV635)) { |
rdev->mc.vram_width = 2 * chansize; |
} |
} |
void r600_vram_info(struct radeon_device *rdev) |
{ |
r600_vram_get_type(rdev); |
rdev->mc.vram_size = RREG32(R600_CONFIG_MEMSIZE); |
/* Could aper size report 0 ? */ |
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
} |
/* |
* Indirect registers accessor |
*/ |
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) |
{ |
uint32_t r; |
WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
(void)RREG32(R600_PCIE_PORT_INDEX); |
r = RREG32(R600_PCIE_PORT_DATA); |
return r; |
} |
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
{ |
WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
(void)RREG32(R600_PCIE_PORT_INDEX); |
WREG32(R600_PCIE_PORT_DATA, (v)); |
(void)RREG32(R600_PCIE_PORT_DATA); |
} |
/drivers/video/drm/radeon/radeon.h |
---|
60,7 → 60,10 |
extern int radeon_modeset; |
extern int radeon_dynclks; |
extern int radeon_r4xx_atom; |
extern int radeon_agpmode; |
extern int radeon_vram_limit; |
extern int radeon_gart_size; |
extern int radeon_benchmarking; |
extern int radeon_connector_table; |
/* |
614,9 → 617,15 |
*(volatile uint32_t __force *) addr = b; |
} |
static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
{ |
*(volatile __u64 *)addr = b; |
} |
#define writeb __raw_writeb |
#define writew __raw_writew |
#define writel __raw_writel |
#define writeq __raw_writeq |
//#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
//#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
1201,5 → 1210,6 |
resource_size_t |
drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
bool set_mode(struct drm_device *dev, int width, int height); |
#endif |
/drivers/video/drm/radeon/radeon_asic.h |
---|
61,20 → 61,18 |
void r100_ring_start(struct radeon_device *rdev); |
int r100_irq_set(struct radeon_device *rdev); |
int r100_irq_process(struct radeon_device *rdev); |
//void r100_fence_ring_emit(struct radeon_device *rdev, |
// struct radeon_fence *fence); |
//int r100_cs_parse(struct radeon_cs_parser *p); |
void r100_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
int r100_cs_parse(struct radeon_cs_parser *p); |
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
//int r100_copy_blit(struct radeon_device *rdev, |
// uint64_t src_offset, |
// uint64_t dst_offset, |
// unsigned num_pages, |
// struct radeon_fence *fence); |
int r100_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence); |
#if 0 |
static struct radeon_asic r100_asic = { |
.init = &r100_init, |
.errata = &r100_errata, |
82,27 → 80,27 |
.gpu_reset = &r100_gpu_reset, |
.mc_init = &r100_mc_init, |
.mc_fini = &r100_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r100_gart_enable, |
.gart_disable = &r100_pci_gart_disable, |
.gart_tlb_flush = &r100_pci_gart_tlb_flush, |
.gart_set_page = &r100_pci_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r100_ring_start, |
.irq_set = &r100_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r100_fence_ring_emit, |
// .cs_parse = &r100_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = NULL, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
// .set_engine_clock = &radeon_legacy_set_engine_clock, |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
}; |
116,9 → 114,9 |
int r300_mc_init(struct radeon_device *rdev); |
void r300_mc_fini(struct radeon_device *rdev); |
void r300_ring_start(struct radeon_device *rdev); |
//void r300_fence_ring_emit(struct radeon_device *rdev, |
// struct radeon_fence *fence); |
//int r300_cs_parse(struct radeon_cs_parser *p); |
void r300_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
int r300_cs_parse(struct radeon_cs_parser *p); |
int r300_gart_enable(struct radeon_device *rdev); |
void rv370_pcie_gart_disable(struct radeon_device *rdev); |
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
126,11 → 124,11 |
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
//int r300_copy_dma(struct radeon_device *rdev, |
// uint64_t src_offset, |
// uint64_t dst_offset, |
// unsigned num_pages, |
// struct radeon_fence *fence); |
int r300_copy_dma(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence); |
static struct radeon_asic r300_asic = { |
140,29 → 138,30 |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &r300_mc_init, |
.mc_fini = &r300_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_disable = &r100_pci_gart_disable, |
.gart_tlb_flush = &r100_pci_gart_tlb_flush, |
.gart_set_page = &r100_pci_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r300_ring_start, |
.irq_set = &r100_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = &rv370_set_pcie_lanes, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
// .set_engine_clock = &radeon_legacy_set_engine_clock, |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
}; |
/* |
* r420,r423,rv410 |
*/ |
177,27 → 176,27 |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &r420_mc_init, |
.mc_fini = &r420_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_disable = &rv370_pcie_gart_disable, |
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
.gart_set_page = &rv370_pcie_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r300_ring_start, |
.irq_set = &r100_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.set_pcie_lanes = &rv370_set_pcie_lanes, |
.set_clock_gating = &radeon_atom_set_clock_gating, |
// .set_engine_clock = &radeon_atom_set_engine_clock, |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
}; |
221,27 → 220,27 |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs400_mc_init, |
.mc_fini = &rs400_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &rs400_gart_enable, |
.gart_disable = &rs400_gart_disable, |
.gart_tlb_flush = &rs400_gart_tlb_flush, |
.gart_set_page = &rs400_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r300_ring_start, |
.irq_set = &r100_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
// .set_engine_clock = &radeon_legacy_set_engine_clock, |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
}; |
259,6 → 258,7 |
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
static struct radeon_asic rs600_asic = { |
.init = &r300_init, |
.errata = &rs600_errata, |
266,27 → 266,27 |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs600_mc_init, |
.mc_fini = &rs600_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &rs600_gart_enable, |
.gart_disable = &rs600_gart_disable, |
.gart_tlb_flush = &rs600_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r300_ring_start, |
.irq_set = &rs600_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &rs600_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_atom_set_clock_gating, |
// .set_engine_clock = &radeon_atom_set_engine_clock, |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
}; |
306,30 → 306,29 |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs690_mc_init, |
.mc_fini = &rs690_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &rs400_gart_enable, |
.gart_disable = &rs400_gart_disable, |
.gart_tlb_flush = &rs400_gart_tlb_flush, |
.gart_set_page = &rs400_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &r300_ring_start, |
.irq_set = &rs600_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &rs600_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r300_copy_dma, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_atom_set_clock_gating, |
// .set_engine_clock = &radeon_atom_set_engine_clock, |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
}; |
#endif |
/* |
* rv515 |
*/ |
345,7 → 344,7 |
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
/* |
static struct radeon_asic rv515_asic = { |
.init = &rv515_init, |
.errata = &rv515_errata, |
353,41 → 352,30 |
.gpu_reset = &rv515_gpu_reset, |
.mc_init = &rv515_mc_init, |
.mc_fini = &rv515_mc_fini, |
.wb_init = &r100_wb_init, |
.wb_fini = &r100_wb_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_disable = &rv370_pcie_gart_disable, |
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
.gart_set_page = &rv370_pcie_gart_set_page, |
.cp_init = &r100_cp_init, |
.cp_fini = &r100_cp_fini, |
.cp_disable = &r100_cp_disable, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.ring_start = &rv515_ring_start, |
.irq_set = &r100_irq_set, |
.irq_process = &r100_irq_process, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
// .fence_ring_emit = &r300_fence_ring_emit, |
// .cs_parse = &r300_cs_parse, |
// .copy_blit = &r100_copy_blit, |
// .copy_dma = &r300_copy_dma, |
// .copy = &r100_copy_blit, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.set_pcie_lanes = &rv370_set_pcie_lanes, |
.set_clock_gating = &radeon_atom_set_clock_gating, |
// .set_engine_clock = &radeon_atom_set_engine_clock, |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
}; |
*/ |
int r300_gart_enable(struct radeon_device *rdev); |
void rv370_pcie_gart_disable(struct radeon_device *rdev); |
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
/* |
* r520,rv530,rv560,rv570,r580 |
*/ |
/drivers/video/drm/radeon/radeon_atombios.c |
---|
447,7 → 447,7 |
struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; |
atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
ENTRY(); |
supported_devices = |
(union atom_supported_devices *)(ctx->bios + data_offset); |
596,7 → 596,7 |
} |
radeon_link_encoder_connector(dev); |
LEAVE(); |
return true; |
} |
944,8 → 944,6 |
struct radeon_device *rdev = dev->dev_private; |
uint32_t bios_2_scratch, bios_6_scratch; |
dbgprintf("%s\n",__FUNCTION__); |
if (rdev->family >= CHIP_R600) { |
bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); |
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
/drivers/video/drm/radeon/radeon_clocks.c |
---|
94,8 → 94,8 |
if (rdev->is_atom_bios) |
ret = radeon_atom_get_clock_info(dev); |
// else |
// ret = radeon_combios_get_clock_info(dev); |
else |
ret = radeon_combios_get_clock_info(dev); |
if (ret) { |
if (p1pll->reference_div < 2) |
/drivers/video/drm/radeon/radeon_device.c |
---|
250,8 → 250,8 |
/* Don't change order as we are overridding accessor. */ |
if (rdev->family < CHIP_RV515) { |
// rdev->pcie_rreg = &rv370_pcie_rreg; |
// rdev->pcie_wreg = &rv370_pcie_wreg; |
rdev->pcie_rreg = &rv370_pcie_rreg; |
rdev->pcie_wreg = &rv370_pcie_wreg; |
} |
if (rdev->family >= CHIP_RV515) { |
rdev->pcie_rreg = &rv515_pcie_rreg; |
267,20 → 267,20 |
rdev->mc_wreg = &rv515_mc_wreg; |
} |
if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
// rdev->mc_rreg = &rs400_mc_rreg; |
// rdev->mc_wreg = &rs400_mc_wreg; |
rdev->mc_rreg = &rs400_mc_rreg; |
rdev->mc_wreg = &rs400_mc_wreg; |
} |
if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
// rdev->mc_rreg = &rs690_mc_rreg; |
// rdev->mc_wreg = &rs690_mc_wreg; |
rdev->mc_rreg = &rs690_mc_rreg; |
rdev->mc_wreg = &rs690_mc_wreg; |
} |
if (rdev->family == CHIP_RS600) { |
// rdev->mc_rreg = &rs600_mc_rreg; |
// rdev->mc_wreg = &rs600_mc_wreg; |
rdev->mc_rreg = &rs600_mc_rreg; |
rdev->mc_wreg = &rs600_mc_wreg; |
} |
if (rdev->family >= CHIP_R600) { |
// rdev->pciep_rreg = &r600_pciep_rreg; |
// rdev->pciep_wreg = &r600_pciep_wreg; |
rdev->pciep_rreg = &r600_pciep_rreg; |
rdev->pciep_wreg = &r600_pciep_wreg; |
} |
} |
304,32 → 304,32 |
case CHIP_RV250: |
case CHIP_RS300: |
case CHIP_RV280: |
// rdev->asic = &r100_asic; |
rdev->asic = &r100_asic; |
break; |
case CHIP_R300: |
case CHIP_R350: |
case CHIP_RV350: |
case CHIP_RV380: |
// rdev->asic = &r300_asic; |
rdev->asic = &r300_asic; |
break; |
case CHIP_R420: |
case CHIP_R423: |
case CHIP_RV410: |
// rdev->asic = &r420_asic; |
rdev->asic = &r420_asic; |
break; |
case CHIP_RS400: |
case CHIP_RS480: |
// rdev->asic = &rs400_asic; |
rdev->asic = &rs400_asic; |
break; |
case CHIP_RS600: |
// rdev->asic = &rs600_asic; |
rdev->asic = &rs600_asic; |
break; |
case CHIP_RS690: |
case CHIP_RS740: |
// rdev->asic = &rs690_asic; |
rdev->asic = &rs690_asic; |
break; |
case CHIP_RV515: |
// rdev->asic = &rv515_asic; |
rdev->asic = &rv515_asic; |
break; |
case CHIP_R520: |
case CHIP_RV530: |
454,7 → 454,7 |
int radeon_combios_init(struct radeon_device *rdev) |
{ |
// radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
return 0; |
} |
869,9 → 869,8 |
// driver->name, driver->major, driver->minor, driver->patchlevel, |
// driver->date, pci_name(pdev), dev->primary->index); |
drm_helper_resume_force_mode(dev); |
set_mode(dev, 1024, 768); |
return 0; |
err_g4: |
931,3 → 930,5 |
return rem; |
} |
/drivers/video/drm/radeon/radeon_fb.c |
---|
1173,3 → 1173,101 |
#undef BYTES_PER_LONG |
} |
static char *manufacturer_name(unsigned char *x) |
{ |
static char name[4]; |
name[0] = ((x[0] & 0x7C) >> 2) + '@'; |
name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
name[2] = (x[1] & 0x1F) + '@'; |
name[3] = 0; |
return name; |
} |
bool set_mode(struct drm_device *dev, int width, int height) |
{ |
struct drm_connector *connector; |
bool ret; |
ENTRY(); |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
{ |
struct drm_display_mode *mode; |
struct drm_encoder *encoder; |
struct drm_crtc *crtc; |
if( connector->status != connector_status_connected) |
continue; |
encoder = connector->encoder; |
if( encoder == NULL) |
continue; |
crtc = encoder->crtc; |
if(crtc == NULL) |
continue; |
list_for_each_entry(mode, &connector->modes, head) |
{ |
char *con_name, *enc_name; |
struct drm_framebuffer *fb; |
if (drm_mode_width(mode) == width && |
drm_mode_height(mode) == height) |
{ |
char con_edid[128]; |
fb = list_first_entry(&dev->mode_config.fb_kernel_list, |
struct drm_framebuffer, filp_head); |
memcpy(con_edid, connector->edid_blob_ptr->data, 128); |
dbgprintf("Manufacturer: %s Model %x Serial Number %u\n", |
manufacturer_name(con_edid + 0x08), |
(unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
(unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
+ (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
con_name = drm_get_connector_name(connector); |
enc_name = drm_get_encoder_name(encoder); |
dbgprintf("set mode %d %d connector %s encoder %s\n", |
width, height, con_name, enc_name); |
fb->width = width; |
fb->height = height; |
fb->pitch = radeon_align_pitch(dev->dev_private, width, 32) |
* ((32 + 1) / 8); |
crtc->fb = fb; |
ret = drm_crtc_helper_set_mode(crtc, mode, 0, 0, fb); |
sysSetScreen(width,height); |
if (ret == true) |
{ |
} |
else |
{ |
DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
width, height, crtc); |
}; |
return ret; |
}; |
} |
}; |
return false; |
}; |
/drivers/video/drm/radeon/radeon_gart.c |
---|
30,7 → 30,6 |
#include "radeon.h" |
#include "radeon_reg.h" |
#if 0 |
/* |
* Common GART table functions. |
*/ |
38,8 → 37,8 |
{ |
void *ptr; |
ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, |
&rdev->gart.table_addr); |
// ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, |
// &rdev->gart.table_addr); |
if (ptr == NULL) { |
return -ENOMEM; |
} |
67,13 → 66,12 |
rdev->gart.table_size >> PAGE_SHIFT); |
} |
#endif |
pci_free_consistent(rdev->pdev, rdev->gart.table_size, |
(void *)rdev->gart.table.ram.ptr, |
rdev->gart.table_addr); |
// pci_free_consistent(rdev->pdev, rdev->gart.table_size, |
// (void *)rdev->gart.table.ram.ptr, |
// rdev->gart.table_addr); |
rdev->gart.table.ram.ptr = NULL; |
rdev->gart.table_addr = 0; |
} |
#endif |
int radeon_gart_table_vram_alloc(struct radeon_device *rdev) |
{ |
/drivers/video/drm/radeon/radeon_object.c |
---|
769,6 → 769,8 |
return ttm_fbdev_mmap(vma, &robj->tobj); |
} |
#endif |
unsigned long radeon_object_size(struct radeon_object *robj) |
{ |
return robj->tobj.num_pages << PAGE_SHIFT; |
775,4 → 777,3 |
} |
#endif |
/drivers/video/drm/radeon/rs400.c |
---|
0,0 → 1,411 |
/* |
* Copyright 2008 Advanced Micro Devices, Inc. |
* Copyright 2008 Red Hat Inc. |
* Copyright 2009 Jerome Glisse. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
* Alex Deucher |
* Jerome Glisse |
*/ |
//#include <linux/seq_file.h> |
#include <drmP.h> |
#include "radeon_reg.h" |
#include "radeon.h" |
/* rs400,rs480 depends on : */ |
void r100_hdp_reset(struct radeon_device *rdev); |
void r100_mc_disable_clients(struct radeon_device *rdev); |
int r300_mc_wait_for_idle(struct radeon_device *rdev); |
void r420_pipes_init(struct radeon_device *rdev); |
/* This files gather functions specifics to : |
* rs400,rs480 |
* |
* Some of these functions might be used by newer ASICs. |
*/ |
void rs400_gpu_init(struct radeon_device *rdev); |
int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
/* |
* GART functions. |
*/ |
void rs400_gart_adjust_size(struct radeon_device *rdev) |
{ |
/* Check gart size */ |
switch (rdev->mc.gtt_size/(1024*1024)) { |
case 32: |
case 64: |
case 128: |
case 256: |
case 512: |
case 1024: |
case 2048: |
break; |
default: |
DRM_ERROR("Unable to use IGP GART size %uM\n", |
rdev->mc.gtt_size >> 20); |
DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); |
DRM_ERROR("Forcing to 32M GART size\n"); |
rdev->mc.gtt_size = 32 * 1024 * 1024; |
return; |
} |
if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
/* FIXME: RS400 & RS480 seems to have issue with GART size |
* if 4G of system memory (needs more testing) */ |
rdev->mc.gtt_size = 32 * 1024 * 1024; |
DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); |
} |
} |
void rs400_gart_tlb_flush(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
unsigned int timeout = rdev->usec_timeout; |
WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); |
do { |
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) |
break; |
DRM_UDELAY(1); |
timeout--; |
} while (timeout > 0); |
WREG32_MC(RS480_GART_CACHE_CNTRL, 0); |
} |
int rs400_gart_enable(struct radeon_device *rdev) |
{ |
uint32_t size_reg; |
uint32_t tmp; |
int r; |
/* Initialize common gart structure */ |
r = radeon_gart_init(rdev); |
if (r) { |
return r; |
} |
if (rs400_debugfs_pcie_gart_info_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); |
} |
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
/* Check gart size */ |
switch(rdev->mc.gtt_size / (1024 * 1024)) { |
case 32: |
size_reg = RS480_VA_SIZE_32MB; |
break; |
case 64: |
size_reg = RS480_VA_SIZE_64MB; |
break; |
case 128: |
size_reg = RS480_VA_SIZE_128MB; |
break; |
case 256: |
size_reg = RS480_VA_SIZE_256MB; |
break; |
case 512: |
size_reg = RS480_VA_SIZE_512MB; |
break; |
case 1024: |
size_reg = RS480_VA_SIZE_1GB; |
break; |
case 2048: |
size_reg = RS480_VA_SIZE_2GB; |
break; |
default: |
return -EINVAL; |
} |
if (rdev->gart.table.ram.ptr == NULL) { |
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
r = radeon_gart_table_ram_alloc(rdev); |
if (r) { |
return r; |
} |
} |
/* It should be fine to program it to max value */ |
if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); |
WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); |
} else { |
WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); |
WREG32(RS480_AGP_BASE_2, 0); |
} |
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); |
tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16); |
if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); |
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
WREG32(RADEON_BUS_CNTL, tmp); |
} else { |
WREG32(RADEON_MC_AGP_LOCATION, tmp); |
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
WREG32(RADEON_BUS_CNTL, tmp); |
} |
/* Table should be in 32bits address space so ignore bits above. */ |
tmp = rdev->gart.table_addr & 0xfffff000; |
WREG32_MC(RS480_GART_BASE, tmp); |
/* TODO: more tweaking here */ |
WREG32_MC(RS480_GART_FEATURE_ID, |
(RS480_TLB_ENABLE | |
RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); |
/* Disable snooping */ |
WREG32_MC(RS480_AGP_MODE_CNTL, |
(1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); |
/* Disable AGP mode */ |
/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
WREG32_MC(RS480_MC_MISC_CNTL, |
(RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); |
} else { |
WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
} |
/* Enable gart */ |
WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
rs400_gart_tlb_flush(rdev); |
rdev->gart.ready = true; |
return 0; |
} |
void rs400_gart_disable(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
} |
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
{ |
if (i < 0 || i > rdev->gart.num_gpu_pages) { |
return -EINVAL; |
} |
rdev->gart.table.ram.ptr[i] = cpu_to_le32(((uint32_t)addr) | 0xC); |
return 0; |
} |
/* |
* MC functions. |
*/ |
int rs400_mc_init(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
int r; |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
rs400_gpu_init(rdev); |
rs400_gart_disable(rdev); |
rdev->mc.gtt_location = rdev->mc.vram_size; |
rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
rdev->mc.vram_location = 0xFFFFFFFFUL; |
r = radeon_mc_setup(rdev); |
if (r) { |
return r; |
} |
r100_mc_disable_clients(rdev); |
if (r300_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
WREG32(RADEON_MC_FB_LOCATION, tmp); |
tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS; |
WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
(void)RREG32(RADEON_HOST_PATH_CNTL); |
WREG32(RADEON_HOST_PATH_CNTL, tmp); |
(void)RREG32(RADEON_HOST_PATH_CNTL); |
return 0; |
} |
void rs400_mc_fini(struct radeon_device *rdev) |
{ |
rs400_gart_disable(rdev); |
radeon_gart_table_ram_free(rdev); |
radeon_gart_fini(rdev); |
} |
/* |
* Global GPU functions |
*/ |
void rs400_errata(struct radeon_device *rdev) |
{ |
rdev->pll_errata = 0; |
} |
void rs400_gpu_init(struct radeon_device *rdev) |
{ |
/* FIXME: HDP same place on rs400 ? */ |
r100_hdp_reset(rdev); |
/* FIXME: is this correct ? */ |
r420_pipes_init(rdev); |
if (r300_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
} |
/* |
* VRAM info. |
*/ |
void rs400_vram_info(struct radeon_device *rdev) |
{ |
uint32_t tom; |
rs400_gart_adjust_size(rdev); |
/* DDR for all card after R300 & IGP */ |
rdev->mc.vram_is_ddr = true; |
rdev->mc.vram_width = 128; |
/* read NB_TOM to get the amount of ram stolen for the GPU */ |
tom = RREG32(RADEON_NB_TOM); |
rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
/* Could aper size report 0 ? */ |
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
} |
/* |
* Indirect registers accessor |
*/ |
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
{ |
uint32_t r; |
WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
r = RREG32(RS480_NB_MC_DATA); |
WREG32(RS480_NB_MC_INDEX, 0xff); |
return r; |
} |
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
{ |
WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
WREG32(RS480_NB_MC_DATA, (v)); |
WREG32(RS480_NB_MC_INDEX, 0xff); |
} |
/* |
* Debugfs info |
*/ |
#if defined(CONFIG_DEBUG_FS) |
static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
{ |
struct drm_info_node *node = (struct drm_info_node *) m->private; |
struct drm_device *dev = node->minor->dev; |
struct radeon_device *rdev = dev->dev_private; |
uint32_t tmp; |
tmp = RREG32(RADEON_HOST_PATH_CNTL); |
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
tmp = RREG32(RADEON_BUS_CNTL); |
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); |
if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); |
seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); |
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); |
seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
tmp = RREG32_MC(0x100); |
seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
tmp = RREG32(0x134); |
seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
} else { |
tmp = RREG32(RADEON_AGP_BASE); |
seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
tmp = RREG32(RS480_AGP_BASE_2); |
seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); |
tmp = RREG32(RADEON_MC_AGP_LOCATION); |
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
} |
tmp = RREG32_MC(RS480_GART_BASE); |
seq_printf(m, "GART_BASE 0x%08x\n", tmp); |
tmp = RREG32_MC(RS480_GART_FEATURE_ID); |
seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); |
tmp = RREG32_MC(RS480_AGP_MODE_CNTL); |
seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); |
tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); |
tmp = RREG32_MC(0x5F); |
seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); |
tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); |
seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); |
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); |
tmp = RREG32_MC(0x3B); |
seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); |
tmp = RREG32_MC(0x3C); |
seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); |
tmp = RREG32_MC(0x30); |
seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); |
tmp = RREG32_MC(0x31); |
seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); |
tmp = RREG32_MC(0x32); |
seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); |
tmp = RREG32_MC(0x33); |
seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); |
tmp = RREG32_MC(0x34); |
seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); |
tmp = RREG32_MC(0x35); |
seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); |
tmp = RREG32_MC(0x36); |
seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); |
tmp = RREG32_MC(0x37); |
seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); |
return 0; |
} |
static struct drm_info_list rs400_gart_info_list[] = { |
{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
}; |
#endif |
int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
{ |
#if defined(CONFIG_DEBUG_FS) |
return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
#else |
return 0; |
#endif |
} |
/drivers/video/drm/radeon/rs600.c |
---|
0,0 → 1,324 |
/* |
* Copyright 2008 Advanced Micro Devices, Inc. |
* Copyright 2008 Red Hat Inc. |
* Copyright 2009 Jerome Glisse. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
* Alex Deucher |
* Jerome Glisse |
*/ |
#include "drmP.h" |
#include "radeon_reg.h" |
#include "radeon.h" |
/* rs600 depends on : */ |
void r100_hdp_reset(struct radeon_device *rdev); |
int r100_gui_wait_for_idle(struct radeon_device *rdev); |
int r300_mc_wait_for_idle(struct radeon_device *rdev); |
void r420_pipes_init(struct radeon_device *rdev); |
/* This files gather functions specifics to : |
* rs600 |
* |
* Some of these functions might be used by newer ASICs. |
*/ |
void rs600_gpu_init(struct radeon_device *rdev); |
int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
void rs600_disable_vga(struct radeon_device *rdev); |
/* |
* GART. |
*/ |
void rs600_gart_tlb_flush(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; |
WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
} |
int rs600_gart_enable(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
int i; |
int r; |
/* Initialize common gart structure */ |
r = radeon_gart_init(rdev); |
if (r) { |
return r; |
} |
rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
r = radeon_gart_table_vram_alloc(rdev); |
if (r) { |
return r; |
} |
/* FIXME: setup default page */ |
WREG32_MC(RS600_MC_PT0_CNTL, |
(RS600_EFFECTIVE_L2_CACHE_SIZE(6) | |
RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); |
for (i = 0; i < 19; i++) { |
WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i, |
(RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | |
RS600_SYSTEM_ACCESS_MODE_IN_SYS | |
RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE | |
RS600_EFFECTIVE_L1_CACHE_SIZE(3) | |
RS600_ENABLE_FRAGMENT_PROCESSING | |
RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); |
} |
/* System context map to GART space */ |
WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location); |
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
/* enable first context */ |
WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location); |
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp); |
WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL, |
(RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT)); |
/* disable all other contexts */ |
for (i = 1; i < 8; i++) { |
WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); |
} |
/* setup the page table */ |
WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
rdev->gart.table_addr); |
WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
/* enable page tables */ |
tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT)); |
tmp = RREG32_MC(RS600_MC_CNTL1); |
WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES)); |
rs600_gart_tlb_flush(rdev); |
rdev->gart.ready = true; |
return 0; |
} |
void rs600_gart_disable(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
/* FIXME: disable out of gart access */ |
WREG32_MC(RS600_MC_PT0_CNTL, 0); |
tmp = RREG32_MC(RS600_MC_CNTL1); |
tmp &= ~RS600_ENABLE_PAGE_TABLES; |
WREG32_MC(RS600_MC_CNTL1, tmp); |
// radeon_object_kunmap(rdev->gart.table.vram.robj); |
// radeon_object_unpin(rdev->gart.table.vram.robj); |
} |
#define R600_PTE_VALID (1 << 0) |
#define R600_PTE_SYSTEM (1 << 1) |
#define R600_PTE_SNOOPED (1 << 2) |
#define R600_PTE_READABLE (1 << 5) |
#define R600_PTE_WRITEABLE (1 << 6) |
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
{ |
void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
if (i < 0 || i > rdev->gart.num_gpu_pages) { |
return -EINVAL; |
} |
addr = addr & 0xFFFFFFFFFFFFF000ULL; |
addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
return 0; |
} |
/* |
* MC. |
*/ |
void rs600_mc_disable_clients(struct radeon_device *rdev) |
{ |
unsigned tmp; |
if (r100_gui_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait GUI idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = RREG32(AVIVO_D1VGA_CONTROL); |
WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
tmp = RREG32(AVIVO_D2VGA_CONTROL); |
WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
tmp = RREG32(AVIVO_D1CRTC_CONTROL); |
WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
/* make sure all previous write got through */ |
tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
mdelay(1); |
} |
int rs600_mc_init(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
int r; |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
rs600_gpu_init(rdev); |
rs600_gart_disable(rdev); |
/* Setup GPU memory space */ |
rdev->mc.vram_location = 0xFFFFFFFFUL; |
rdev->mc.gtt_location = 0xFFFFFFFFUL; |
r = radeon_mc_setup(rdev); |
if (r) { |
return r; |
} |
/* Program GPU memory space */ |
/* Enable bus master */ |
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
WREG32(RADEON_BUS_CNTL, tmp); |
/* FIXME: What does AGP means for such chipset ? */ |
WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF); |
/* FIXME: are this AGP reg in indirect MC range ? */ |
WREG32_MC(RS600_MC_AGP_BASE, 0); |
WREG32_MC(RS600_MC_AGP_BASE_2, 0); |
rs600_mc_disable_clients(rdev); |
if (rs600_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); |
tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); |
WREG32_MC(RS600_MC_FB_LOCATION, tmp); |
WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
return 0; |
} |
void rs600_mc_fini(struct radeon_device *rdev) |
{ |
rs600_gart_disable(rdev); |
radeon_gart_table_vram_free(rdev); |
radeon_gart_fini(rdev); |
} |
/* |
* Global GPU functions |
*/ |
void rs600_disable_vga(struct radeon_device *rdev) |
{ |
unsigned tmp; |
WREG32(0x330, 0); |
WREG32(0x338, 0); |
tmp = RREG32(0x300); |
tmp &= ~(3 << 16); |
WREG32(0x300, tmp); |
WREG32(0x308, (1 << 8)); |
WREG32(0x310, rdev->mc.vram_location); |
WREG32(0x594, 0); |
} |
int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
{ |
unsigned i; |
uint32_t tmp; |
for (i = 0; i < rdev->usec_timeout; i++) { |
/* read MC_STATUS */ |
tmp = RREG32_MC(RS600_MC_STATUS); |
if (tmp & RS600_MC_STATUS_IDLE) { |
return 0; |
} |
DRM_UDELAY(1); |
} |
return -1; |
} |
void rs600_errata(struct radeon_device *rdev) |
{ |
rdev->pll_errata = 0; |
} |
void rs600_gpu_init(struct radeon_device *rdev) |
{ |
/* FIXME: HDP same place on rs600 ? */ |
r100_hdp_reset(rdev); |
rs600_disable_vga(rdev); |
/* FIXME: is this correct ? */ |
r420_pipes_init(rdev); |
if (rs600_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
} |
/* |
* VRAM info. |
*/ |
void rs600_vram_info(struct radeon_device *rdev) |
{ |
/* FIXME: to do or is these values sane ? */ |
rdev->mc.vram_is_ddr = true; |
rdev->mc.vram_width = 128; |
} |
/* |
* Indirect registers accessor |
*/ |
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
{ |
uint32_t r; |
WREG32(RS600_MC_INDEX, |
((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); |
r = RREG32(RS600_MC_DATA); |
return r; |
} |
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
{ |
WREG32(RS600_MC_INDEX, |
RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | |
((reg) & RS600_MC_ADDR_MASK)); |
WREG32(RS600_MC_DATA, v); |
} |
/drivers/video/drm/radeon/rs690.c |
---|
0,0 → 1,181 |
/* |
* Copyright 2008 Advanced Micro Devices, Inc. |
* Copyright 2008 Red Hat Inc. |
* Copyright 2009 Jerome Glisse. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
* Alex Deucher |
* Jerome Glisse |
*/ |
#include "drmP.h" |
#include "radeon_reg.h" |
#include "radeon.h" |
/* rs690,rs740 depends on : */ |
void r100_hdp_reset(struct radeon_device *rdev); |
int r300_mc_wait_for_idle(struct radeon_device *rdev); |
void r420_pipes_init(struct radeon_device *rdev); |
void rs400_gart_disable(struct radeon_device *rdev); |
int rs400_gart_enable(struct radeon_device *rdev); |
void rs400_gart_adjust_size(struct radeon_device *rdev); |
void rs600_mc_disable_clients(struct radeon_device *rdev); |
void rs600_disable_vga(struct radeon_device *rdev); |
/* This files gather functions specifics to : |
* rs690,rs740 |
* |
* Some of these functions might be used by newer ASICs. |
*/ |
void rs690_gpu_init(struct radeon_device *rdev); |
int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
/* |
* MC functions. |
*/ |
int rs690_mc_init(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
int r; |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
rs690_gpu_init(rdev); |
rs400_gart_disable(rdev); |
/* Setup GPU memory space */ |
rdev->mc.gtt_location = rdev->mc.vram_size; |
rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
rdev->mc.vram_location = 0xFFFFFFFFUL; |
r = radeon_mc_setup(rdev); |
if (r) { |
return r; |
} |
/* Program GPU memory space */ |
rs600_mc_disable_clients(rdev); |
if (rs690_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16); |
tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16); |
WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp); |
/* FIXME: Does this reg exist on RS480,RS740 ? */ |
WREG32(0x310, rdev->mc.vram_location); |
WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
return 0; |
} |
void rs690_mc_fini(struct radeon_device *rdev) |
{ |
rs400_gart_disable(rdev); |
radeon_gart_table_ram_free(rdev); |
radeon_gart_fini(rdev); |
} |
/* |
* Global GPU functions |
*/ |
int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
{ |
unsigned i; |
uint32_t tmp; |
for (i = 0; i < rdev->usec_timeout; i++) { |
/* read MC_STATUS */ |
tmp = RREG32_MC(RS690_MC_STATUS); |
if (tmp & RS690_MC_STATUS_IDLE) { |
return 0; |
} |
DRM_UDELAY(1); |
} |
return -1; |
} |
void rs690_errata(struct radeon_device *rdev) |
{ |
rdev->pll_errata = 0; |
} |
void rs690_gpu_init(struct radeon_device *rdev) |
{ |
/* FIXME: HDP same place on rs690 ? */ |
r100_hdp_reset(rdev); |
rs600_disable_vga(rdev); |
/* FIXME: is this correct ? */ |
r420_pipes_init(rdev); |
if (rs690_mc_wait_for_idle(rdev)) { |
printk(KERN_WARNING "Failed to wait MC idle while " |
"programming pipes. Bad things might happen.\n"); |
} |
} |
/* |
* VRAM info. |
*/ |
void rs690_vram_info(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
rs400_gart_adjust_size(rdev); |
/* DDR for all card after R300 & IGP */ |
rdev->mc.vram_is_ddr = true; |
/* FIXME: is this correct for RS690/RS740 ? */ |
tmp = RREG32(RADEON_MEM_CNTL); |
if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
rdev->mc.vram_width = 128; |
} else { |
rdev->mc.vram_width = 64; |
} |
rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
} |
/* |
* Indirect registers accessor |
*/ |
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
{ |
uint32_t r; |
WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK)); |
r = RREG32(RS690_MC_DATA); |
WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK); |
return r; |
} |
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
{ |
WREG32(RS690_MC_INDEX, |
RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK)); |
WREG32(RS690_MC_DATA, v); |
WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
} |
/drivers/video/drm/radeon/rv515.c |
---|
52,7 → 52,6 |
void rv515_gpu_init(struct radeon_device *rdev); |
int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
#if 0 |
/* |
* MC |
*/ |
61,15 → 60,15 |
uint32_t tmp; |
int r; |
if (r100_debugfs_rbbm_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
} |
if (rv515_debugfs_pipes_info_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
} |
if (rv515_debugfs_ga_info_init(rdev)) { |
DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
} |
// if (r100_debugfs_rbbm_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
// } |
// if (rv515_debugfs_pipes_info_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
// } |
// if (rv515_debugfs_ga_info_init(rdev)) { |
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
// } |
rv515_gpu_init(rdev); |
rv370_pcie_gart_disable(rdev); |
130,7 → 129,6 |
radeon_gart_fini(rdev); |
} |
#endif |
/* |
* Global GPU functions |
256,7 → 254,6 |
return -1; |
} |
#if 0 |
void rv515_gpu_init(struct radeon_device *rdev) |
{ |
unsigned pipe_select_current, gb_pipe_select, tmp; |
288,7 → 285,6 |
} |
} |
#endif |
int rv515_ga_reset(struct radeon_device *rdev) |
{ |