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955 | serge | 1 | |
2 | //#define ATOM_BIOS_PARSER 1 |
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3 | |||
4 | |||
5 | |||
6 | |||
7 | |||
8 | |||
9 | |||
10 | |||
11 | #define TRUE 1 |
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12 | |||
13 | |||
14 | |||
15 | |||
16 | |||
17 | |||
18 | typedef unsigned short u16_t; |
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19 | typedef unsigned int u32_t; |
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20 | |||
21 | |||
22 | typedef unsigned int size_t; |
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23 | |||
24 | |||
25 | #define MAX_VREFRESH 8 |
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26 | #define INTERLACE_REFRESH_WEIGHT 1.5 |
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27 | #define SYNC_TOLERANCE 0.01 /* 1 percent */ |
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28 | #define CLOCK_TOLERANCE 2000 /* Clock matching tolerance (2MHz) */ |
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29 | |||
30 | |||
31 | |||
32 | |||
33 | |||
34 | #define IMPORT __attribute__ ((dllimport)) |
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35 | |||
36 | |||
37 | |||
38 | void* STDCALL KernelAlloc(unsigned size)__asm__("KernelAlloc"); |
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39 | int KernelFree(void *); |
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40 | |||
41 | |||
42 | |||
43 | |||
44 | u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16"); |
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45 | u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32"); |
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46 | |||
47 | |||
48 | PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
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49 | |||
50 | |||
51 | u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16"); |
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52 | u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32"); |
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53 | |||
54 | |||
55 | PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
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56 | |||
57 | |||
58 | |||
59 | |||
60 | |||
61 | |||
62 | void *calloc( size_t num, size_t size ); |
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63 | void *realloc(void*, size_t); |
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64 | void free(void*); |
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65 | |||
66 | |||
67 | |||
68 | #define xnfalloc malloc |
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69 | |||
70 | |||
71 | #define xnfcalloc calloc |
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72 | |||
73 | |||
74 | |||
75 | |||
76 | |||
77 | |||
78 | |||
79 | |||
80 | void* memcpy(void * dest, const void *src, size_t n); |
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81 | int memcmp(const void *s1, const void *s2, size_t n); |
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82 | |||
83 | |||
84 | char* strcpy(char *to, const char *from); |
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85 | char* strcat(char *s, const char *append); |
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86 | char* strdup(const char *s); |
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87 | char* strchr(const char *s, int c); |
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88 | int strcmp(const char *s1, const char *s2); |
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89 | |||
90 | |||
91 | |||
92 | |||
93 | |||
94 | |||
95 | int printf(const char* format, ...); |
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96 | int dbg_open(char *path); |
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97 | int dbgprintf(const char* format, ...); |
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98 | |||
99 | |||
100 | |||
101 | |||
102 | typedef enum { |
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103 | MODE_OK = 0, /* Mode OK */ |
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104 | MODE_HSYNC, /* hsync out of range */ |
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105 | MODE_VSYNC, /* vsync out of range */ |
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106 | MODE_H_ILLEGAL, /* mode has illegal horizontal timings */ |
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107 | MODE_V_ILLEGAL, /* mode has illegal horizontal timings */ |
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108 | MODE_BAD_WIDTH, /* requires an unsupported linepitch */ |
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109 | MODE_NOMODE, /* no mode with a maching name */ |
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110 | MODE_NO_INTERLACE, /* interlaced mode not supported */ |
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111 | MODE_NO_DBLESCAN, /* doublescan mode not supported */ |
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112 | MODE_NO_VSCAN, /* multiscan mode not supported */ |
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113 | MODE_MEM, /* insufficient video memory */ |
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114 | MODE_VIRTUAL_X, /* mode width too large for specified virtual size */ |
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115 | MODE_VIRTUAL_Y, /* mode height too large for specified virtual size */ |
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116 | MODE_MEM_VIRT, /* insufficient video memory given virtual size */ |
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117 | MODE_NOCLOCK, /* no fixed clock available */ |
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118 | MODE_CLOCK_HIGH, /* clock required is too high */ |
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119 | MODE_CLOCK_LOW, /* clock required is too low */ |
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120 | MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */ |
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121 | MODE_BAD_HVALUE, /* horizontal timing was out of range */ |
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122 | MODE_BAD_VVALUE, /* vertical timing was out of range */ |
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123 | MODE_BAD_VSCAN, /* VScan value out of range */ |
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124 | MODE_HSYNC_NARROW, /* horizontal sync too narrow */ |
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125 | MODE_HSYNC_WIDE, /* horizontal sync too wide */ |
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126 | MODE_HBLANK_NARROW, /* horizontal blanking too narrow */ |
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127 | MODE_HBLANK_WIDE, /* horizontal blanking too wide */ |
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128 | MODE_VSYNC_NARROW, /* vertical sync too narrow */ |
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129 | MODE_VSYNC_WIDE, /* vertical sync too wide */ |
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130 | MODE_VBLANK_NARROW, /* vertical blanking too narrow */ |
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131 | MODE_VBLANK_WIDE, /* vertical blanking too wide */ |
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132 | MODE_PANEL, /* exceeds panel dimensions */ |
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133 | MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */ |
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134 | MODE_ONE_WIDTH, /* only one width is supported */ |
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135 | MODE_ONE_HEIGHT, /* only one height is supported */ |
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136 | MODE_ONE_SIZE, /* only one resolution is supported */ |
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137 | MODE_BAD = -2, /* unspecified reason */ |
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138 | MODE_ERROR = -1 /* error condition */ |
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139 | } ModeStatus; |
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140 | |||
141 | |||
142 | V_PHSYNC = 0x0001, |
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143 | V_NHSYNC = 0x0002, |
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144 | V_PVSYNC = 0x0004, |
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145 | V_NVSYNC = 0x0008, |
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146 | V_INTERLACE = 0x0010, |
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147 | V_DBLSCAN = 0x0020, |
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148 | V_CSYNC = 0x0040, |
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149 | V_PCSYNC = 0x0080, |
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150 | V_NCSYNC = 0x0100, |
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151 | V_HSKEW = 0x0200, /* hskew provided */ |
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152 | V_BCAST = 0x0400, |
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153 | V_PIXMUX = 0x1000, |
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154 | V_DBLCLK = 0x2000, |
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155 | V_CLKDIV2 = 0x4000 |
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156 | } ModeFlags; |
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157 | |||
158 | |||
159 | # define M_T_USERDEF 0x20 /* One of the modes from the config file */ |
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160 | |||
161 | |||
162 | |||
163 | typedef struct _DisplayModeRec { |
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164 | struct _DisplayModeRec * prev; |
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165 | struct _DisplayModeRec * next; |
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166 | char * name; /* identifier for the mode */ |
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167 | ModeStatus status; |
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168 | int type; |
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169 | |||
170 | |||
171 | int Clock; /* pixel clock freq */ |
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172 | int HDisplay; /* horizontal timing */ |
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173 | int HSyncStart; |
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174 | int HSyncEnd; |
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175 | int HTotal; |
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176 | int HSkew; |
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177 | int VDisplay; /* vertical timing */ |
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178 | int VSyncStart; |
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179 | int VSyncEnd; |
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180 | int VTotal; |
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181 | int VScan; |
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182 | int Flags; |
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183 | |||
184 | |||
185 | int ClockIndex; |
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186 | int SynthClock; /* Actual clock freq to |
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187 | * be programmed */ |
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188 | int CrtcHDisplay; |
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189 | int CrtcHBlankStart; |
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190 | int CrtcHSyncStart; |
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191 | int CrtcHSyncEnd; |
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192 | int CrtcHBlankEnd; |
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193 | int CrtcHTotal; |
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194 | int CrtcHSkew; |
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195 | int CrtcVDisplay; |
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196 | int CrtcVBlankStart; |
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197 | int CrtcVSyncStart; |
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198 | int CrtcVSyncEnd; |
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199 | int CrtcVBlankEnd; |
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200 | int CrtcVTotal; |
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201 | Bool CrtcHAdjusted; |
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202 | Bool CrtcVAdjusted; |
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203 | int PrivSize; |
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204 | CARD32* Private; |
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205 | int PrivFlags; |
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206 | |||
207 | |||
208 | } DisplayModeRec, *DisplayModePtr; |
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209 | |||
210 | |||
211 | { |
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212 | unsigned short red, green, blue; |
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213 | } LOCO; |
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214 | |||
215 | |||
216 | |||
217 | __clear (void * dst, unsigned len) |
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218 | { u32_t tmp; |
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219 | asm __volatile__ |
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220 | ( |
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221 | "xor eax, eax \n\t" |
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222 | "cld \n\t" |
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223 | "rep stosb" |
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224 | :"=c"(tmp),"=D"(tmp) |
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225 | :"c"(len),"D"(dst) |
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226 | :"memory","eax","cc" |
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227 | ); |
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228 | }; |
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229 | |||
230 | |||
231 | abs (int i) |
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232 | { |
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233 | return i < 0 ? -i : i; |
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234 | }; |
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235 | |||
236 | |||
237 | #define DPMSModeStandby 1 |
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238 | #define DPMSModeSuspend 2 |
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239 | #define DPMSModeOff 3 |
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240 | |||
241 | |||
242 | |||
243 | |||
244 | #define min(x,y) (((y)<(x))?(y):(x)) |
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245 | |||
246 | |||
247 | |||
248 | |||
249 |