WebSVN – Kolibri OS – Blame – /programs/system/drivers/ati2d/rhd_regs.h

Rev	Author	Line No.	Line
808	serge	1	/*
		2	* Copyright 2007, 2008 Luc Verhaegen
		3	* Copyright 2007, 2008 Matthias Hopf
		4	* Copyright 2007, 2008 Egbert Eich
		5	* Copyright 2007, 2008 Advanced Micro Devices, Inc.
		6	*
		7	* Permission is hereby granted, free of charge, to any person obtaining a
		8	* copy of this software and associated documentation files (the "Software"),
		9	* to deal in the Software without restriction, including without limitation
		10	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		11	* and/or sell copies of the Software, and to permit persons to whom the
		12	* Software is furnished to do so, subject to the following conditions:
		13	*
		14	* The above copyright notice and this permission notice shall be included in
		15	* all copies or substantial portions of the Software.
		16	*
		17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		20	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		21	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		22	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		23	* OTHER DEALINGS IN THE SOFTWARE.
		24	*/
		25	#ifndef _RHD_REGS_H
		26	# define _RHD_REGS_H
		27
		28	enum {
		29	CLOCK_CNTL_INDEX = 0x8, /* (RW) */
		30	CLOCK_CNTL_DATA = 0xC, /* (RW) */
		31	BUS_CNTL = 0x4C, /* (RW) */
		32	MC_IND_INDEX = 0x70, /* (RW) */
		33	MC_IND_DATA = 0x74, /* (RW) */
		34	CONFIG_CNTL = 0xE0,
		35	/* RS690 ?? */
		36	RS69_MC_INDEX = 0xE8,
		37	RS69_MC_DATA = 0xEC,
		38	R5XX_CONFIG_MEMSIZE = 0x00F8,
		39
		40	HDP_FB_LOCATION = 0x0134,
		41
		42	SEPROM_CNTL1 = 0x1C0, /* (RW) */
		43	GPIOPAD_MASK = 0x198, /* (RW) */
		44	GPIOPAD_A = 0x19C, /* (RW) */
		45	GPIOPAD_EN = 0x1A0, /* (RW) */
		46	VIPH_CONTROL = 0xC40, /* (RW) */
		47
		48	/* VGA registers */
		49	VGA_RENDER_CONTROL = 0x0300,
		50	VGA_MODE_CONTROL = 0x0308,
		51	VGA_MEMORY_BASE_ADDRESS = 0x0310,
		52	VGA_HDP_CONTROL = 0x0328,
		53	D1VGA_CONTROL = 0x0330,
		54	D2VGA_CONTROL = 0x0338,
		55
		56	EXT1_PPLL_REF_DIV_SRC = 0x0400,
		57	EXT1_PPLL_REF_DIV = 0x0404,
		58	EXT1_PPLL_UPDATE_LOCK = 0x0408,
		59	EXT1_PPLL_UPDATE_CNTL = 0x040C,
		60	EXT2_PPLL_REF_DIV_SRC = 0x0410,
		61	EXT2_PPLL_REF_DIV = 0x0414,
		62	EXT2_PPLL_UPDATE_LOCK = 0x0418,
		63	EXT2_PPLL_UPDATE_CNTL = 0x041C,
		64
		65	EXT1_PPLL_FB_DIV = 0x0430,
		66	EXT2_PPLL_FB_DIV = 0x0434,
		67	EXT1_PPLL_POST_DIV_SRC = 0x0438,
		68	EXT1_PPLL_POST_DIV = 0x043C,
		69	EXT2_PPLL_POST_DIV_SRC = 0x0440,
		70	EXT2_PPLL_POST_DIV = 0x0444,
		71	EXT1_PPLL_CNTL = 0x0448,
		72	EXT2_PPLL_CNTL = 0x044C,
		73	P1PLL_CNTL = 0x0450,
		74	P2PLL_CNTL = 0x0454,
		75	P1PLL_INT_SS_CNTL = 0x0458,
		76	P2PLL_INT_SS_CNTL = 0x045C,
		77
		78	P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */
		79	P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */
		80	EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */
		81	EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */
		82
		83	PCLK_CRTC1_CNTL = 0x0480,
		84	PCLK_CRTC2_CNTL = 0x0484,
		85
		86	DCCG_DISP_CLK_SRCSEL = 0x0538, /* rv620+ */
		87
		88	R6XX_MC_VM_FB_LOCATION = 0x2180,
		89	R6XX_HDP_NONSURFACE_BASE = 0x2C04,
		90	R6XX_CONFIG_MEMSIZE = 0x5428,
		91	R6XX_CONFIG_FB_BASE = 0x542C, /* AKA CONFIG_F0_BASE */
		92
		93	/* CRTC1 registers */
		94	D1CRTC_H_TOTAL = 0x6000,
		95	D1CRTC_H_BLANK_START_END = 0x6004,
		96	D1CRTC_H_SYNC_A = 0x6008,
		97	D1CRTC_H_SYNC_A_CNTL = 0x600C,
		98	D1CRTC_H_SYNC_B = 0x6010,
		99	D1CRTC_H_SYNC_B_CNTL = 0x6014,
		100
		101	D1CRTC_V_TOTAL = 0x6020,
		102	D1CRTC_V_BLANK_START_END = 0x6024,
		103	D1CRTC_V_SYNC_A = 0x6028,
		104	D1CRTC_V_SYNC_A_CNTL = 0x602C,
		105	D1CRTC_V_SYNC_B = 0x6030,
		106	D1CRTC_V_SYNC_B_CNTL = 0x6034,
		107
		108	D1CRTC_CONTROL = 0x6080,
		109	D1CRTC_BLANK_CONTROL = 0x6084,
		110	D1CRTC_INTERLACE_CONTROL = 0x6088,
		111	D1CRTC_BLACK_COLOR = 0x6098,
		112	D1CRTC_STATUS = 0x609C,
		113	D1CRTC_COUNT_CONTROL = 0x60B4,
		114
		115	/* D1GRPH registers */
		116	D1GRPH_ENABLE = 0x6100,
		117	D1GRPH_CONTROL = 0x6104,
		118	D1GRPH_LUT_SEL = 0x6108,
		119	D1GRPH_SWAP_CNTL = 0x610C,
		120	D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
		121	D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118,
		122	D1GRPH_PITCH = 0x6120,
		123	D1GRPH_SURFACE_OFFSET_X = 0x6124,
		124	D1GRPH_SURFACE_OFFSET_Y = 0x6128,
		125	D1GRPH_X_START = 0x612C,
		126	D1GRPH_Y_START = 0x6130,
		127	D1GRPH_X_END = 0x6134,
		128	D1GRPH_Y_END = 0x6138,
		129	D1GRPH_UPDATE = 0x6144,
		130
		131	/* LUT */
		132	DC_LUT_RW_SELECT = 0x6480,
		133	DC_LUT_RW_MODE = 0x6484,
		134	DC_LUT_RW_INDEX = 0x6488,
		135	DC_LUT_SEQ_COLOR = 0x648C,
		136	DC_LUT_PWL_DATA = 0x6490,
		137	DC_LUT_30_COLOR = 0x6494,
		138	DC_LUT_READ_PIPE_SELECT = 0x6498,
		139	DC_LUT_WRITE_EN_MASK = 0x649C,
		140	DC_LUT_AUTOFILL = 0x64A0,
		141
		142	/* LUTA */
		143	DC_LUTA_CONTROL = 0x64C0,
		144	DC_LUTA_BLACK_OFFSET_BLUE = 0x64C4,
		145	DC_LUTA_BLACK_OFFSET_GREEN = 0x64C8,
		146	DC_LUTA_BLACK_OFFSET_RED = 0x64CC,
		147	DC_LUTA_WHITE_OFFSET_BLUE = 0x64D0,
		148	DC_LUTA_WHITE_OFFSET_GREEN = 0x64D4,
		149	DC_LUTA_WHITE_OFFSET_RED = 0x64D8,
		150
		151	/* D1CUR */
		152	D1CUR_CONTROL = 0x6400,
		153	D1CUR_SURFACE_ADDRESS = 0x6408,
		154	D1CUR_SIZE = 0x6410,
		155	D1CUR_POSITION = 0x6414,
		156	D1CUR_HOT_SPOT = 0x6418,
		157	D1CUR_UPDATE = 0x6424,
		158
		159	/* D1MODE */
		160	D1MODE_DESKTOP_HEIGHT = 0x652C,
		161	D1MODE_VIEWPORT_START = 0x6580,
		162	D1MODE_VIEWPORT_SIZE = 0x6584,
		163	D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588,
		164	D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C,
		165	D1MODE_DATA_FORMAT = 0x6528,
		166
		167	/* D1SCL */
		168	D1SCL_ENABLE = 0x6590,
		169	D1SCL_TAP_CONTROL = 0x6594,
		170	D1MODE_CENTER = 0x659C, /* guess */
		171	D1SCL_HVSCALE = 0x65A4, /* guess */
		172	D1SCL_HFILTER = 0x65B0, /* guess */
		173	D1SCL_VFILTER = 0x65C0, /* guess */
		174	D1SCL_UPDATE = 0x65CC,
		175	D1SCL_DITHER = 0x65D4, /* guess */
		176	D1SCL_FLIP_CONTROL = 0x65D8, /* guess */
		177
		178	/* CRTC2 registers */
		179	D2CRTC_H_TOTAL = 0x6800,
		180	D2CRTC_H_BLANK_START_END = 0x6804,
		181	D2CRTC_H_SYNC_A = 0x6808,
		182	D2CRTC_H_SYNC_A_CNTL = 0x680C,
		183	D2CRTC_H_SYNC_B = 0x6810,
		184	D2CRTC_H_SYNC_B_CNTL = 0x6814,
		185
		186	D2CRTC_V_TOTAL = 0x6820,
		187	D2CRTC_V_BLANK_START_END = 0x6824,
		188	D2CRTC_V_SYNC_A = 0x6828,
		189	D2CRTC_V_SYNC_A_CNTL = 0x682C,
		190	D2CRTC_V_SYNC_B = 0x6830,
		191	D2CRTC_V_SYNC_B_CNTL = 0x6834,
		192
		193	D2CRTC_CONTROL = 0x6880,
		194	D2CRTC_BLANK_CONTROL = 0x6884,
		195	D2CRTC_BLACK_COLOR = 0x6898,
		196	D2CRTC_INTERLACE_CONTROL = 0x6888,
		197	D2CRTC_STATUS = 0x689C,
		198	D2CRTC_COUNT_CONTROL = 0x68B4,
		199
		200	/* D2GRPH registers */
		201	D2GRPH_ENABLE = 0x6900,
		202	D2GRPH_CONTROL = 0x6904,
		203	D2GRPH_LUT_SEL = 0x6908,
		204	D2GRPH_SWAP_CNTL = 0x690C,
		205	D2GRPH_PRIMARY_SURFACE_ADDRESS = 0x6910,
		206	D2GRPH_PITCH = 0x6920,
		207	D2GRPH_SURFACE_OFFSET_X = 0x6924,
		208	D2GRPH_SURFACE_OFFSET_Y = 0x6928,
		209	D2GRPH_X_START = 0x692C,
		210	D2GRPH_Y_START = 0x6930,
		211	D2GRPH_X_END = 0x6934,
		212	D2GRPH_Y_END = 0x6938,
		213
		214	/* LUTB */
		215	DC_LUTB_CONTROL = 0x6CC0,
		216	DC_LUTB_BLACK_OFFSET_BLUE = 0x6CC4,
		217	DC_LUTB_BLACK_OFFSET_GREEN = 0x6CC8,
		218	DC_LUTB_BLACK_OFFSET_RED = 0x6CCC,
		219	DC_LUTB_WHITE_OFFSET_BLUE = 0x6CD0,
		220	DC_LUTB_WHITE_OFFSET_GREEN = 0x6CD4,
		221	DC_LUTB_WHITE_OFFSET_RED = 0x6CD8,
		222
		223	/* D2MODE */
		224	D2MODE_DESKTOP_HEIGHT = 0x6D2C,
		225	D2MODE_VIEWPORT_START = 0x6D80,
		226	D2MODE_VIEWPORT_SIZE = 0x6D84,
		227	D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88,
		228	D2MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x6D8C,
		229	D2MODE_DATA_FORMAT = 0x6D28,
		230
		231	/* D2SCL */
		232	D2SCL_ENABLE = 0x6D90,
		233	D2SCL_TAP_CONTROL = 0x6D94,
		234	D2MODE_CENTER = 0x6D9C, /* guess */
		235	D2SCL_HVSCALE = 0x6DA4, /* guess */
		236	D2SCL_HFILTER = 0x6DB0, /* guess */
		237	D2SCL_VFILTER = 0x6DC0, /* guess */
		238	D2SCL_UPDATE = 0x6DCC,
		239	D2SCL_DITHER = 0x6DD4, /* guess */
		240	D2SCL_FLIP_CONTROL = 0x6DD8, /* guess */
		241
		242	/* R500 DAC A */
		243	DACA_ENABLE = 0x7800,
		244	DACA_SOURCE_SELECT = 0x7804,
		245	DACA_SYNC_TRISTATE_CONTROL = 0x7820,
		246	DACA_SYNC_SELECT = 0x7824,
		247	DACA_AUTODETECT_CONTROL = 0x7828,
		248	DACA_FORCE_OUTPUT_CNTL = 0x783C,
		249	DACA_FORCE_DATA = 0x7840,
		250	DACA_POWERDOWN = 0x7850,
		251	DACA_CONTROL1 = 0x7854,
		252	DACA_CONTROL2 = 0x7858,
		253	DACA_COMPARATOR_ENABLE = 0x785C,
		254	DACA_COMPARATOR_OUTPUT = 0x7860,
		255
		256	/* TMDSA */
		257	TMDSA_CNTL = 0x7880,
		258	TMDSA_SOURCE_SELECT = 0x7884,
		259	TMDSA_COLOR_FORMAT = 0x7888,
		260	TMDSA_FORCE_OUTPUT_CNTL = 0x788C,
		261	TMDSA_BIT_DEPTH_CONTROL = 0x7894,
		262	TMDSA_DCBALANCER_CONTROL = 0x78D0,
		263	TMDSA_DATA_SYNCHRONIZATION_R500 = 0x78D8,
		264	TMDSA_DATA_SYNCHRONIZATION_R600 = 0x78DC,
		265	TMDSA_TRANSMITTER_ENABLE = 0x7904,
		266	TMDSA_LOAD_DETECT = 0x7908,
		267	TMDSA_MACRO_CONTROL = 0x790C, /* r5x0 and r600: 3 for pll and 1 for TX */
		268	TMDSA_PLL_ADJUST = 0x790C, /* rv6x0: pll only */
		269	TMDSA_TRANSMITTER_CONTROL = 0x7910,
		270	TMDSA_TRANSMITTER_ADJUST = 0x7920, /* rv6x0: TX part of macro control */
		271
		272	/* DAC B */
		273	DACB_ENABLE = 0x7A00,
		274	DACB_SOURCE_SELECT = 0x7A04,
		275	DACB_SYNC_TRISTATE_CONTROL = 0x7A20,
		276	DACB_SYNC_SELECT = 0x7A24,
		277	DACB_AUTODETECT_CONTROL = 0x7A28,
		278	DACB_FORCE_OUTPUT_CNTL = 0x7A3C,
		279	DACB_FORCE_DATA = 0x7A40,
		280	DACB_POWERDOWN = 0x7A50,
		281	DACB_CONTROL1 = 0x7A54,
		282	DACB_CONTROL2 = 0x7A58,
		283	DACB_COMPARATOR_ENABLE = 0x7A5C,
		284	DACB_COMPARATOR_OUTPUT = 0x7A60,
		285
		286	/* LVTMA */
		287	LVTMA_CNTL = 0x7A80,
		288	LVTMA_SOURCE_SELECT = 0x7A84,
		289	LVTMA_COLOR_FORMAT = 0x7A88,
		290	LVTMA_FORCE_OUTPUT_CNTL = 0x7A8C,
		291	LVTMA_BIT_DEPTH_CONTROL = 0x7A94,
		292	LVTMA_DCBALANCER_CONTROL = 0x7AD0,
		293
		294	/* no longer shared between both r5xx and r6xx */
		295	LVTMA_R500_DATA_SYNCHRONIZATION = 0x7AD8,
		296	LVTMA_R500_PWRSEQ_REF_DIV = 0x7AE4,
		297	LVTMA_R500_PWRSEQ_DELAY1 = 0x7AE8,
		298	LVTMA_R500_PWRSEQ_DELAY2 = 0x7AEC,
		299	LVTMA_R500_PWRSEQ_CNTL = 0x7AF0,
		300	LVTMA_R500_PWRSEQ_STATE = 0x7AF4,
		301	LVTMA_R500_LVDS_DATA_CNTL = 0x7AFC,
		302	LVTMA_R500_MODE = 0x7B00,
		303	LVTMA_R500_TRANSMITTER_ENABLE = 0x7B04,
		304	LVTMA_R500_MACRO_CONTROL = 0x7B0C,
		305	LVTMA_R500_TRANSMITTER_CONTROL = 0x7B10,
		306	LVTMA_R500_REG_TEST_OUTPUT = 0x7B14,
		307
		308	/* R600 adds an undocumented register at 0x7AD8,
		309	* shifting all subsequent registers by exactly one. */
		310	LVTMA_R600_DATA_SYNCHRONIZATION = 0x7ADC,
		311	LVTMA_R600_PWRSEQ_REF_DIV = 0x7AE8,
		312	LVTMA_R600_PWRSEQ_DELAY1 = 0x7AEC,
		313	LVTMA_R600_PWRSEQ_DELAY2 = 0x7AF0,
		314	LVTMA_R600_PWRSEQ_CNTL = 0x7AF4,
		315	LVTMA_R600_PWRSEQ_STATE = 0x7AF8,
		316	LVTMA_R600_LVDS_DATA_CNTL = 0x7B00,
		317	LVTMA_R600_MODE = 0x7B04,
		318	LVTMA_R600_TRANSMITTER_ENABLE = 0x7B08,
		319	LVTMA_R600_MACRO_CONTROL = 0x7B10,
		320	LVTMA_R600_TRANSMITTER_CONTROL = 0x7B14,
		321	LVTMA_R600_REG_TEST_OUTPUT = 0x7B18,
		322
		323	LVTMA_TRANSMITTER_ADJUST = 0x7B24, /* RV630 */
		324	LVTMA_PREEMPHASIS_CONTROL = 0x7B28, /* RV630 */
		325
		326	/* I2C in separate enum */
		327
		328	/* HPD */
		329	DC_GPIO_HPD_MASK = 0x7E90,
		330	DC_GPIO_HPD_A = 0x7E94,
		331	DC_GPIO_HPD_EN = 0x7E98,
		332	DC_GPIO_HPD_Y = 0x7E9C
		333	};
		334
		335	enum CONFIG_CNTL_BITS {
		336	RS69_CFG_ATI_REV_ID_SHIFT = 8,
		337	RS69_CFG_ATI_REV_ID_MASK = 0xF << RS69_CFG_ATI_REV_ID_SHIFT
		338	};
		339
		340	enum rv620Regs {
		341	/* DAC common */
		342	RV620_DAC_COMPARATOR_MISC = 0x7da4,
		343	RV620_DAC_COMPARATOR_OUTPUT = 0x7da8,
		344
		345	/* RV620 DAC A */
		346	RV620_DACA_ENABLE = 0x7000,
		347	RV620_DACA_SOURCE_SELECT = 0x7004,
		348	RV620_DACA_SYNC_TRISTATE_CONTROL = 0x7020,
		349	/* RV620_DACA_SYNC_SELECT = 0x7024, ?? */
		350	RV620_DACA_AUTODETECT_CONTROL = 0x7028,
		351	RV620_DACA_AUTODETECT_STATUS = 0x7034,
		352	RV620_DACA_AUTODETECT_INT_CONTROL = 0x7038,
		353	RV620_DACA_FORCE_OUTPUT_CNTL = 0x703C,
		354	RV620_DACA_FORCE_DATA = 0x7040,
		355	RV620_DACA_POWERDOWN = 0x7050,
		356	/* RV620_DACA_CONTROL1 moved */
		357	RV620_DACA_CONTROL2 = 0x7058,
		358	RV620_DACA_COMPARATOR_ENABLE = 0x705C,
		359	/* RV620_DACA_COMPARATOR_OUTPUT changed */
		360	RV620_DACA_BGADJ_SRC = 0x7ef0,
		361	RV620_DACA_MACRO_CNTL = 0x7ef4,
		362	RV620_DACA_AUTO_CALIB_CONTROL = 0x7ef8,
		363
		364	/* DAC B */
		365	RV620_DACB_ENABLE = 0x7100,
		366	RV620_DACB_SOURCE_SELECT = 0x7104,
		367	RV620_DACB_SYNC_TRISTATE_CONTROL = 0x7120,
		368	/* RV620_DACB_SYNC_SELECT = 0x7124, ?? */
		369	RV620_DACB_AUTODETECT_CONTROL = 0x7128,
		370	RV620_DACB_AUTODETECT_STATUS = 0x7134,
		371	RV620_DACB_AUTODETECT_INT_CONTROL = 0x7138,
		372	RV620_DACB_FORCE_OUTPUT_CNTL = 0x713C,
		373	RV620_DACB_FORCE_DATA = 0x7140,
		374	RV620_DACB_POWERDOWN = 0x7150,
		375	/* RV620_DACB_CONTROL1 moved */
		376	RV620_DACB_CONTROL2 = 0x7158,
		377	RV620_DACB_COMPARATOR_ENABLE = 0x715C,
		378	RV620_DACB_BGADJ_SRC = 0x7ef0,
		379	RV620_DACB_MACRO_CNTL = 0x7ff4,
		380	RV620_DACB_AUTO_CALIB_CONTROL = 0x7ef8,
		381	/* DIG1 */
		382	RV620_DIG1_CNTL = 0x75A0,
		383	RV620_DIG1_CLOCK_PATTERN = 0x75AC,
		384	RV620_LVDS1_DATA_CNTL = 0x75BC,
		385	RV620_TMDS1_CNTL = 0x75C0,
		386	/* DIG2 */
		387	RV620_DIG2_CNTL = 0x79A0,
		388	RV620_DIG2_CLOCK_PATTERN = 0x79AC,
		389	RV620_LVDS2_DATA_CNTL = 0x79BC,
		390	RV620_TMDS2_CNTL = 0x79C0,
		391
		392	/* RV62x I2C */
		393	RV62_GENERIC_I2C_CONTROL = 0x7d80, /* (RW) */
		394	RV62_GENERIC_I2C_INTERRUPT_CONTROL = 0x7d84, /* (RW) */
		395	RV62_GENERIC_I2C_STATUS = 0x7d88, /* (RW) */
		396	RV62_GENERIC_I2C_SPEED = 0x7d8c, /* (RW) */
		397	RV62_GENERIC_I2C_SETUP = 0x7d90, /* (RW) */
		398	RV62_GENERIC_I2C_TRANSACTION = 0x7d94, /* (RW) */
		399	RV62_GENERIC_I2C_DATA = 0x7d98, /* (RW) */
		400	RV62_GENERIC_I2C_PIN_SELECTION = 0x7d9c, /* (RW) */
		401	RV62_DC_GPIO_DDC4_MASK = 0x7e20, /* (RW) */
		402	RV62_DC_GPIO_DDC1_MASK = 0x7e40, /* (RW) */
		403	RV62_DC_GPIO_DDC2_MASK = 0x7e50, /* (RW) */
		404	RV62_DC_GPIO_DDC3_MASK = 0x7e60, /* (RW) */
		405
		406	/* ?? */
		407	RV620_DCIO_LINK_STEER_CNTL = 0x7FA4,
		408
		409	RV620_LVTMA_TRANSMITTER_CONTROL= 0x7F00,
		410	RV620_LVTMA_TRANSMITTER_ENABLE = 0x7F04,
		411	RV620_LVTMA_TRANSMITTER_ADJUST = 0x7F18,
		412	RV620_LVTMA_PREEMPHASIS_CONTROL= 0x7F1C,
		413	RV620_LVTMA_MACRO_CONTROL = 0x7F0C,
		414	RV620_LVTMA_DATA_SYNCHRONIZATION = 0x7F98,
		415
		416	RV620_FMT1_CONTROL = 0x6700,
		417	RV620_FMT1_BIT_DEPTH_CONTROL= 0x6710,
		418	RV620_FMT1_CLAMP_CNTL = 0x672C,
		419	RV620_FMT2_CONTROL = 0x6F00,
		420	RV620_FMT2_CNTL = 0x6F10,
		421	RV620_FMT2_CLAMP_CNTL = 0x6F2C,
		422
		423	RV620_DCCG_PCLK_DIGA_CNTL = 0x04b0,
		424	RV620_DCCG_PCLK_DIGB_CNTL = 0x04b4,
		425	RV620_DCCG_SYMCLK_CNTL = 0x04b8
		426	};
		427
		428	enum RV620_LVTMA_TRANSMITTER_CONTROL_BITS {
		429	RV62_LVTMA_PLL_ENABLE = 1 << 0,
		430	RV62_LVTMA_PLL_RESET = 1 << 1,
		431	RV62_LVTMA_IDSCKSEL = 1 << 4,
		432	RV62_LVTMA_BGSLEEP = 1 << 5,
		433	RV62_LVTMA_IDCLK_SEL = 1 << 6,
		434	RV62_LVTMA_TMCLK = 1 << 8,
		435	RV62_LVTMA_TMCLK_FROM_PADS = 1 << 13,
		436	RV62_LVTMA_TDCLK = 1 << 14,
		437	RV62_LVTMA_TDCLK_FROM_PADS = 1 << 15,
		438	RV62_LVTMA_BYPASS_PLL = 1 << 28,
		439	RV62_LVTMA_USE_CLK_DATA = 1 << 29,
		440	RV62_LVTMA_MODE = 1 << 30,
		441	RV62_LVTMA_INPUT_TEST_CLK_SEL = 1 << 31
		442	};
		443
		444	enum RV620_DCCG_SYMCLK_CNTL {
		445	RV62_SYMCLKA_SRC_SHIFT = 8,
		446	RV62_SYMCLKB_SRC_SHIFT = 12
		447	};
		448
		449	enum RV620_DCCG_DIG_CNTL {
		450	RV62_PCLK_DIGA_ON = 0x1
		451	};
		452
		453	enum RV620_DCIO_LINK_STEER_CNTL {
		454	RV62_LINK_STEER_SWAP = 1 << 0,
		455	RV62_LINK_STEER_PLLSEL_OVERWRITE_EN = 1 << 16,
		456	RV62_LINK_STEER_PLLSELA = 1 << 17,
		457	RV62_LINK_STEER_PLLSELB = 1 << 18
		458	};
		459
		460	enum R620_LVTMA_TRANSMITTER_ENABLE_BITS {
		461	RV62_LVTMA_LNK0EN = 1 << 0,
		462	RV62_LVTMA_LNK1EN = 1 << 1,
		463	RV62_LVTMA_LNK2EN = 1 << 2,
		464	RV62_LVTMA_LNK3EN = 1 << 3,
		465	RV62_LVTMA_LNK4EN = 1 << 4,
		466	RV62_LVTMA_LNK5EN = 1 << 5,
		467	RV62_LVTMA_LNK6EN = 1 << 6,
		468	RV62_LVTMA_LNK7EN = 1 << 7,
		469	RV62_LVTMA_LNK8EN = 1 << 8,
		470	RV62_LVTMA_LNK9EN = 1 << 9,
		471	RV62_LVTMA_LNKL = RV62_LVTMA_LNK0EN \| RV62_LVTMA_LNK1EN
		472	\| RV62_LVTMA_LNK2EN \| RV62_LVTMA_LNK3EN,
		473	RV62_LVTMA_LNKU = RV62_LVTMA_LNK4EN \| RV62_LVTMA_LNK5EN
		474	\| RV62_LVTMA_LNK6EN \| RV62_LVTMA_LNK7EN,
		475	RV62_LVTMA_LNK_ALL = RV62_LVTMA_LNKL \| RV62_LVTMA_LNKU
		476	\| RV62_LVTMA_LNK8EN \| RV62_LVTMA_LNK9EN,
		477	RV62_LVTMA_LNKEN_HPD_MASK = 1 << 16
		478	};
		479
		480	enum RV620_LVTMA_DATA_SYNCHRONIZATION {
		481	RV62_LVTMA_DSYNSEL = (1 << 0),
		482	RV62_LVTMA_PFREQCHG = (1 << 8)
		483	};
		484
		485
		486	enum RV620_DIG_CNTL_BITS {
		487	/* 0x75A0 */
		488	RV62_DIG_SWAP = (0x1 << 16),
		489	RV62_DIG_DUAL_LINK_ENABLE = (0x1 << 12),
		490	RV62_DIG_START = (0x1 << 6),
		491	RV62_DIG_MODE = (0x7 << 8),
		492	RV62_DIG_STEREOSYNC_SELECT = (1 << 2),
		493	RV62_DIG_SOURCE_SELECT = (1 << 0)
		494	};
		495
		496	enum RV620_DIG_LVDS_DATA_CNTL_BITS {
		497	/* 0x75BC */
		498	RV62_LVDS_24BIT_ENABLE = (0x1 << 0),
		499	RV62_LVDS_24BIT_FORMAT = (0x1 << 4)
		500	};
		501
		502	enum RV620_TMDS_CNTL_BITS {
		503	/* 0x75C0 */
		504	RV62_TMDS_PIXEL_ENCODING = (0x1 << 4),
		505	RV62_TMDS_COLOR_FORMAT = (0x3 << 8)
		506	};
		507
		508	enum RV620_FMT_BIT_DEPTH_CONTROL {
		509	RV62_FMT_TRUNCATE_EN = 1 << 0,
		510	RV62_FMT_TRUNCATE_DEPTH = 1 << 4,
		511	RV62_FMT_SPATIAL_DITHER_EN = 1 << 8,
		512	RV62_FMT_SPATIAL_DITHER_MODE = 1 << 9,
		513	RV62_FMT_SPATIAL_DITHER_DEPTH = 1 << 12,
		514	RV62_FMT_FRAME_RANDOM_ENABLE = 1 << 13,
		515	RV62_FMT_RGB_RANDOM_ENABLE = 1 << 14,
		516	RV62_FMT_HIGHPASS_RANDOM_ENABLE = 1 << 15,
		517	RV62_FMT_TEMPORAL_DITHER_EN = 1 << 16,
		518	RV62_FMT_TEMPORAL_DITHER_DEPTH = 1 << 20,
		519	RV62_FMT_TEMPORAL_DITHER_OFFSET = 3 << 21,
		520	RV62_FMT_TEMPORAL_LEVEL = 1 << 24,
		521	RV62_FMT_TEMPORAL_DITHER_RESET = 1 << 25,
		522	RV62_FMT_25FRC_SEL = 3 << 26,
		523	RV62_FMT_50FRC_SEL = 3 << 28,
		524	RV62_FMT_75FRC_SEL = 3 << 30
		525	};
		526
		527	enum RV620_FMT_CONTROL {
		528	RV62_FMT_PIXEL_ENCODING = 1 << 16
		529	};
		530
		531	enum _r5xxMCRegs {
		532	R5XX_MC_STATUS = 0x0000,
		533	RV515_MC_FB_LOCATION = 0x0001,
		534	R5XX_MC_FB_LOCATION = 0x0004,
		535	RV515_MC_STATUS = 0x0008
		536	};
		537
		538	enum _r5xxRegs {
		539	/* I2C */
		540	R5_DC_I2C_STATUS1 = 0x7D30, /* (RW) */
		541	R5_DC_I2C_RESET = 0x7D34, /* (RW) */
		542	R5_DC_I2C_CONTROL1 = 0x7D38, /* (RW) */
		543	R5_DC_I2C_CONTROL2 = 0x7D3C, /* (RW) */
		544	R5_DC_I2C_CONTROL3 = 0x7D40, /* (RW) */
		545	R5_DC_I2C_DATA = 0x7D44, /* (RW) */
		546	R5_DC_I2C_INTERRUPT_CONTROL = 0x7D48, /* (RW) */
		547	R5_DC_I2C_ARBITRATION = 0x7D50, /* (RW) */
		548
		549	R5_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
		550	R5_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
		551	R5_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
		552	R5_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
		553	R5_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
		554	R5_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
		555	R5_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
		556	R5_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
		557	R5_DC_GPIO_DDC3_EN = 0x7E68 /* (RW) */
		558	};
		559
		560	enum _r5xxSPLLRegs {
		561	SPLL_FUNC_CNTL = 0x0 /* (RW) */
		562	};
		563
		564	enum _r6xxRegs {
		565	/* MCLK */
		566	R6_MCLK_PWRMGT_CNTL = 0x620,
		567	/* I2C */
		568	R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */
		569	R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */
		570	R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
		571	R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */
		572	R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */
		573	R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */
		574	R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */
		575	R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */
		576	R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */
		577	R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */
		578	R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */
		579	R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */
		580	R6_DC_I2C_DATA = 0x7D74, /* (RW) */
		581	R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */
		582	R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */
		583	R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */
		584	R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */
		585	R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */
		586	R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
		587	R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
		588	R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
		589	R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */
		590	R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
		591	R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
		592	R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
		593	R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */
		594	R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
		595	R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
		596	R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */
		597	R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */
		598	};
		599
		600	enum R6_MCLK_PWRMGT_CNTL {
		601	R6_MC_BUSY = (1 << 5)
		602	};
		603
		604
		605	/* _Q: questionbable /
		606	enum _rs69xRegs {
		607	/* I2C */
		608	RS69_DC_I2C_CONTROL = 0x7D30, /* (RW) // */
		609	RS69_DC_I2C_UNKNOWN_2 = 0x7D34, /* (RW) */
		610	RS69_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
		611	RS69_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) //*/
		612	RS69_DC_I2C_UNKNOWN_1 = 0x7d40,
		613	RS69_DC_I2C_DDC_SETUP_Q = 0x7D44, /* (RW) */
		614	RS69_DC_I2C_DATA = 0x7D58, /* (RW) //*/
		615	RS69_DC_I2C_TRANSACTION0 = 0x7D48, /* (RW) //*/
		616	RS69_DC_I2C_TRANSACTION1 = 0x7D4C, /* (RW) //*/
		617	/* DDIA */
		618	RS69_DDIA_CNTL = 0x7200,
		619	RS69_DDIA_SOURCE_SELECT = 0x7204,
		620	RS69_DDIA_BIT_DEPTH_CONTROL = 0x7214,
		621	RS69_DDIA_DCBALANCER_CONTROL = 0x7250,
		622	RS69_DDIA_PATH_CONTROL = 0x7264,
		623	RS69_DDIA_PCIE_LINK_CONTROL2 = 0x7278,
		624	RS69_DDIA_PCIE_LINK_CONTROL3 = 0x727c,
		625	RS69_DDIA_PCIE_PHY_CONTROL1 = 0x728c,
		626	RS69_DDIA_PCIE_PHY_CONTROL2 = 0x7290
		627	};
		628
		629	enum RS69_DDIA_CNTL_BITS {
		630	RS69_DDIA_ENABLE = 1 << 0,
		631	RS69_DDIA_HDMI_EN = 1 << 2,
		632	RS69_DDIA_ENABLE_HPD_MASK = 1 << 4,
		633	RS69_DDIA_HPD_SELECT = 1 << 8,
		634	RS69_DDIA_SYNC_PHASE = 1 << 12,
		635	RS69_DDIA_PIXEL_ENCODING = 1 << 16,
		636	RS69_DDIA_DUAL_LINK_ENABLE = 1 << 24,
		637	RS69_DDIA_SWAP = 1 << 28
		638	};
		639
		640	enum RS69_DDIA_SOURCE_SELECT_BITS {
		641	RS69_DDIA_SOURCE_SELECT_BIT = 1 << 0,
		642	RS69_DDIA_SYNC_SELECT = 1 << 8,
		643	RS69_DDIA_STEREOSYNC_SELECT = 1 << 16
		644	};
		645
		646	enum RS69_DDIA_LINK_CONTROL2_SHIFT {
		647	RS69_DDIA_PCIE_OUTPUT_MUX_SEL0 = 0,
		648	RS69_DDIA_PCIE_OUTPUT_MUX_SEL1 = 4,
		649	RS69_DDIA_PCIE_OUTPUT_MUX_SEL2 = 8,
		650	RS69_DDIA_PCIE_OUTPUT_MUX_SEL3 = 12
		651	};
		652
		653	enum RS69_DDIA_BIT_DEPTH_CONTROL_BITS {
		654	RS69_DDIA_TRUNCATE_EN = 1 << 0,
		655	RS69_DDIA_TRUNCATE_DEPTH = 1 << 4,
		656	RS69_DDIA_SPATIAL_DITHER_EN = 1 << 8,
		657	RS69_DDIA_SPATIAL_DITHER_DEPTH = 1 << 12,
		658	RS69_DDIA_TEMPORAL_DITHER_EN = 1 << 16,
		659	RS69_DDIA_TEMPORAL_DITHER_DEPTH = 1 << 20,
		660	RS69_DDIA_TEMPORAL_LEVEL = 1 << 24,
		661	RS69_DDIA_TEMPORAL_DITHER_RESET = 1 << 25
		662	};
		663
		664	enum RS69_DDIA_DCBALANCER_CONTROL_BITS {
		665	RS69_DDIA_DCBALANCER_EN = 1 << 0,
		666	RS69_DDIA_SYNC_DCBAL_EN = 1 << 4,
		667	RS69_DDIA_DCBALANCER_TEST_EN = 1 << 8,
		668	RS69_DDIA_DCBALANCER_TEST_IN_SHIFT = 16,
		669	RS69_DDIA_DCBALANCER_FORCE = 1 << 24
		670	};
		671
		672	enum RS69_DDIA_PATH_CONTROL_BITS {
		673	RS69_DDIA_PATH_SELECT_SHIFT = 0,
		674	RS69_DDIA_DDPII_DE_ALIGN_EN = 1 << 4,
		675	RS69_DDIA_DDPII_TRAIN_EN = 1 << 8,
		676	RS69_DDIA_DDPII_TRAIN_SELECT = 1 << 12,
		677	RS69_DDIA_DDPII_SCRAMBLE_EN = 1 << 16,
		678	RS69_DDIA_REPL_MODE_SELECT = 1 << 20,
		679	RS69_DDIA_RB_30b_SWAP_EN = 1 << 24,
		680	RS69_DDIA_PIXVLD_RESET = 1 << 28,
		681	RS69_DDIA_REARRANGER_EN = 1 << 30
		682	};
		683
		684	enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS {
		685	RS69_DDIA_PCIE_MIRROR_EN = 1 << 0,
		686	RS69_DDIA_PCIE_CFGDUALLINK = 1 << 4,
		687	RS69_DDIA_PCIE_NCHG3EN = 1 << 8,
		688	RS69_DDIA_PCIE_RX_PDNB_SHIFT = 12
		689	};
		690
		691	enum RS69_MC_INDEX_BITS {
		692	RS69_MC_IND_ADDR = (0x1 << 0),
		693	RS69_C_IND_WR_EN = (0x1 << 9)
		694	};
		695
		696	enum _rs690MCRegs {
		697	RS69_MC_SYSTEM_STATUS = 0x90, /* (RW) */
		698	RS69_MCCFG_FB_LOCATION = 0x100,
		699	RS69MCCFG_AGP_LOCATION = 0x101
		700	};
		701
		702	enum RS69_MC_SYSTEM_STATUS_BITS {
		703	RS69_MC_SYSTEM_IDLE = (0x1 << 0),
		704	RS69_MC_SEQUENCER_IDLE = (0x1 << 1),
		705	RS69_MC_ARBITER_IDLE = (0x1 << 2),
		706	RS69_MC_SELECT_PM = (0x1 << 3),
		707	RS69_RESERVED4 = (0xf << 4),
		708	RS69_RESERVED8 = (0xf << 8),
		709	RS69_RESERVED12_SYSTEM_STATUS = (0xf << 12),
		710	RS69_MCA_INIT_EXECUTED = (0x1 << 16),
		711	RS69_MCA_IDLE = (0x1 << 17),
		712	RS69_MCA_SEQ_IDLE = (0x1 << 18),
		713	RS69_MCA_ARB_IDLE = (0x1 << 19),
		714	RS69_RESERVED20_SYSTEM_STATUS = (0xfff << 20)
		715	};
		716
		717	enum R5XX_MC_STATUS_BITS {
		718	R5XX_MEM_PWRUP_COMPL = (0x1 << 0),
		719	R5XX_MC_IDLE = (0x1 << 1)
		720	};
		721
		722	enum RV515_MC_STATUS_BITS {
		723	RV515_MC_IDLE = (0x1 << 4)
		724	};
		725
		726	enum BUS_CNTL_BITS {
		727	/* BUS_CNTL */
		728	BUS_DBL_RESYNC = (0x1 << 0),
		729	BIOS_ROM_WRT_EN = (0x1 << 1),
		730	BIOS_ROM_DIS = (0x1 << 2),
		731	PMI_IO_DIS = (0x1 << 3),
		732	PMI_MEM_DIS = (0x1 << 4),
		733	PMI_BM_DIS = (0x1 << 5),
		734	PMI_INT_DIS = (0x1 << 6)
		735	};
		736
		737	enum SEPROM_SNTL1_BITS {
		738	/* SEPROM_CNTL1 */
		739	WRITE_ENABLE = (0x1 << 0),
		740	WRITE_DISABLE = (0x1 << 1),
		741	READ_CONFIG = (0x1 << 2),
		742	WRITE_CONFIG = (0x1 << 3),
		743	READ_STATUS = (0x1 << 4),
		744	SECT_TO_SRAM = (0x1 << 5),
		745	READY_BUSY = (0x1 << 7),
		746	SEPROM_BUSY = (0x1 << 8),
		747	BCNT_OVER_WTE_EN = (0x1 << 9),
		748	RB_MASKB = (0x1 << 10),
		749	SOFT_RESET = (0x1 << 11),
		750	STATE_IDLEb = (0x1 << 12),
		751	SECTOR_ERASE = (0x1 << 13),
		752	BYTE_CNT = (0xff << 16),
		753	SCK_PRESCALE = (0xff << 24)
		754	};
		755
		756	enum VIPH_CONTROL_BITS {
		757	/* VIPH_CONTROL */
		758	VIPH_CLK_SEL = (0xff << 0),
		759	VIPH_REG_RDY = (0x1 << 13),
		760	VIPH_MAX_WAIT = (0xf << 16),
		761	VIPH_DMA_MODE = (0x1 << 20),
		762	VIPH_EN = (0x1 << 21),
		763	VIPH_DV0_WID = (0x1 << 24),
		764	VIPH_DV1_WID = (0x1 << 25),
		765	VIPH_DV2_WID = (0x1 << 26),
		766	VIPH_DV3_WID = (0x1 << 27),
		767	VIPH_PWR_DOWN = (0x1 << 28),
		768	VIPH_PWR_DOWN_AK = (0x1 << 28),
		769	VIPH_VIPCLK_DIS = (0x1 << 29)
		770	};
		771
		772	enum VGA_RENDER_CONTROL_BITS {
		773	/* VGA_RENDER_CONTROL */
		774	VGA_BLINK_RATE = (0x1f << 0),
		775	VGA_BLINK_MODE = (0x3 << 5),
		776	VGA_CURSOR_BLINK_INVERT = (0x1 << 7),
		777	VGA_EXTD_ADDR_COUNT_ENABLE = (0x1 << 8),
		778	VGA_VSTATUS_CNTL = (0x3 << 16),
		779	VGA_LOCK_8DOT = (0x1 << 24),
		780	VGAREG_LINECMP_COMPATIBILITY_SEL = (0x1 << 25)
		781	};
		782
		783	enum D1VGA_CONTROL_BITS {
		784	/* D1VGA_CONTROL */
		785	D1VGA_MODE_ENABLE = (0x1 << 0),
		786	D1VGA_TIMING_SELECT = (0x1 << 8),
		787	D1VGA_SYNC_POLARITY_SELECT = (0x1 << 9),
		788	D1VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10),
		789	D1VGA_OVERSCAN_COLOR_EN = (0x1 << 16),
		790	D1VGA_ROTATE = (0x3 << 24)
		791	};
		792
		793	enum D2VGA_CONTROL_BITS {
		794	/* D2VGA_CONTROL */
		795	D2VGA_MODE_ENABLE = (0x1 << 0),
		796	D2VGA_TIMING_SELECT = (0x1 << 8),
		797	D2VGA_SYNC_POLARITY_SELECT = (0x1 << 9),
		798	D2VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10),
		799	D2VGA_OVERSCAN_COLOR_EN = (0x1 << 16),
		800	D2VGA_ROTATE = (0x3 << 24)
		801	};
		802
		803	enum {
		804	/* CLOCK_CNTL_INDEX */
		805	PLL_ADDR = (0x3f << 0),
		806	PLL_WR_EN = (0x1 << 7),
		807	PPLL_DIV_SEL = (0x3 << 8),
		808
		809	/* CLOCK_CNTL_DATA */
		810	#define PLL_DATA 0xffffffff
		811
		812	/* SPLL_FUNC_CNTL */
		813	SPLL_CHG_STATUS = (0x1 << 29),
		814	SPLL_BYPASS_EN = (0x1 << 25),
		815
		816	/* MC_IND_INDEX */
		817	MC_IND_ADDR = (0xffff << 0),
		818	MC_IND_SEQ_RBS_0 = (0x1 << 16),
		819	MC_IND_SEQ_RBS_1 = (0x1 << 17),
		820	MC_IND_SEQ_RBS_2 = (0x1 << 18),
		821	MC_IND_SEQ_RBS_3 = (0x1 << 19),
		822	MC_IND_AIC_RBS = (0x1 << 20),
		823	MC_IND_CITF_ARB0 = (0x1 << 21),
		824	MC_IND_CITF_ARB1 = (0x1 << 22),
		825	MC_IND_WR_EN = (0x1 << 23),
		826	MC_IND_RD_INV = (0x1 << 24)
		827	#define MC_IND_ALL (MC_IND_SEQ_RBS_0 \| MC_IND_SEQ_RBS_1 \
		828	\| MC_IND_SEQ_RBS_2 \| MC_IND_SEQ_RBS_3 \
		829	\| MC_IND_AIC_RBS \| MC_IND_CITF_ARB0 \| MC_IND_CITF_ARB1)
		830
		831	/* MC_IND_DATA */
		832	#define MC_IND_DATA_BIT 0xffffffff
		833	};
		834
		835
		836	#endif /* _RHD_REGS_H */

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(root)/programs/system/drivers/ati2d/rhd_regs.h @ 878 – Rev 808