Rev 883 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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808 | serge | 1 | |
868 | serge | 2 | |
812 | serge | 3 | |
808 | serge | 4 | |
5 | |||
6 | |||
7 | |||
8 | |||
813 | serge | 9 | |
10 | |||
11 | # define RADEON_PLL_WR_EN (1 << 7) |
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12 | # define RADEON_PLL_DIV_SEL (3 << 8) |
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13 | # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
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14 | |||
15 | |||
16 | # define RADEON_FORCEON_MCLKA (1 << 16) |
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17 | # define RADEON_FORCEON_MCLKB (1 << 17) |
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18 | # define RADEON_FORCEON_YCLKA (1 << 18) |
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19 | # define RADEON_FORCEON_YCLKB (1 << 19) |
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20 | # define RADEON_FORCEON_MC (1 << 20) |
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21 | # define RADEON_FORCEON_AIC (1 << 21) |
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22 | # define R300_DISABLE_MC_MCLKA (1 << 21) |
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23 | # define R300_DISABLE_MC_MCLKB (1 << 21) |
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24 | |||
25 | |||
26 | |||
27 | |||
28 | |||
808 | serge | 29 | * Flush all dirty data in the Pixel Cache to memory. |
30 | */ |
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31 | |||
32 | |||
33 | R5xx2DFlush() |
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34 | { |
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35 | int i; |
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36 | |||
37 | |||
38 | R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
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39 | |||
40 | |||
41 | if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
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42 | return TRUE; |
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43 | |||
44 | |||
45 | (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
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46 | return FALSE; |
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47 | } |
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48 | |||
49 | |||
50 | R5xx2DIdleLocal() //R100-R500 |
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51 | { |
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52 | int i; |
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53 | |||
54 | |||
55 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
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56 | if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
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57 | break; |
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58 | |||
59 | |||
60 | dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
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61 | return FALSE; |
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62 | } |
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63 | |||
64 | |||
65 | for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
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66 | if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
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67 | R5xx2DFlush(); |
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68 | return TRUE; |
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69 | } |
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70 | } |
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71 | dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
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72 | return FALSE; |
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73 | |||
74 | |||
75 | |||
76 | |||
77 | |||
78 | R5xx2DSetup() |
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79 | { |
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80 | |||
81 | |||
82 | * set them appropriately before any accel ops, but let's avoid |
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83 | * random bogus DMA in case we inadvertently trigger the engine |
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84 | * in the wrong place (happened). */ |
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85 | R5xxFIFOWaitLocal(2); |
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86 | OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
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87 | OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
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88 | |||
89 | |||
90 | MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
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91 | |||
92 | |||
93 | |||
94 | |||
883 | serge | 95 | OUTREG(R5XX_SC_TOP_LEFT, 0); |
96 | OUTREG(R5XX_SC_BOTTOM_RIGHT, |
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97 | RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); |
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98 | OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, |
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808 | serge | 99 | RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); |
883 | serge | 100 | |
101 | |||
808 | serge | 102 | // OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | |
883 | serge | 103 | // R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); |
104 | OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
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105 | |||
808 | serge | 106 | |
107 | OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); |
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108 | OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); |
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109 | OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); |
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110 | OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); |
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111 | OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
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112 | |||
113 | |||
114 | } |
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115 | |||
116 | |||
877 | serge | 117 | { |
808 | serge | 118 | if (!R5xxFIFOWaitLocal(required)) { |
119 | // R5xx2DReset(); |
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883 | serge | 120 | R5xx2DSetup(); |
808 | serge | 121 | } |
122 | } |
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123 | |||
124 | |||
125 | { |
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126 | if (!R5xx2DIdleLocal()) { |
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127 | // R5xx2DReset(); |
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883 | serge | 128 | R5xx2DSetup(); |
808 | serge | 129 | } |
130 | } |
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131 | |||
132 | |||
133 | |||
134 | |||
135 | { |
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136 | u32_t base; |
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877 | serge | 137 | int screensize; |
878 | serge | 138 | int screenpitch; |
139 | |||
808 | serge | 140 | |
878 | serge | 141 | screenpitch = GetScreenPitch(); |
142 | |||
808 | serge | 143 | |
878 | serge | 144 | rhd.displayHeight = screensize & 0xFFFF; |
145 | |||
146 | |||
808 | serge | 147 | rhd.__ymin = 0; |
148 | rhd.__xmax = rhd.displayWidth - 1; |
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149 | rhd.__ymax = rhd.displayHeight - 1; |
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150 | |||
151 | |||
152 | clip.ymin = 0; |
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153 | clip.xmax = rhd.displayWidth - 1; |
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154 | clip.ymax = rhd.displayHeight - 1; |
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155 | |||
156 | |||
883 | serge | 157 | rhd.displayWidth, rhd.displayHeight); |
158 | |||
808 | serge | 159 | |
883 | serge | 160 | | RADEON_GMC_CLR_CMP_CNTL_DIS |
161 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL); |
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162 | |||
808 | serge | 163 | |
164 | |||
165 | |||
166 | |||
167 | |||
883 | serge | 168 | (rhd.fbLocation >> 10)); |
169 | |||
170 | |||
171 | |||
808 | serge | 172 | |
173 | |||
815 | serge | 174 | scr_pixmap.height = rhd.displayHeight; |
175 | scr_pixmap.format = PICT_a8r8g8b8; |
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176 | scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch; |
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885 | serge | 177 | scr_pixmap.local = (void*)rhd.fbLocation; |
881 | serge | 178 | scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
815 | serge | 179 | scr_pixmap.mapped = (void*)0; |
876 | serge | 180 | |
815 | serge | 181 | |
883 | serge | 182 | OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
183 | OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
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184 | |||
815 | serge | 185 | |
883 | serge | 186 | MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
187 | |||
808 | serge | 188 | |
883 | serge | 189 | |
808 | serge | 190 | |
883 | serge | 191 | #else |
192 | init_cp(&rhd); |
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193 | #endif |
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194 | |||
195 | |||
808 | serge | 196 | |
197 | |||
198 |