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Rev | Author | Line No. | Line |
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808 | serge | 1 | |
868 | serge | 2 | |
812 | serge | 3 | |
808 | serge | 4 | |
5 | |||
6 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
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7 | |||
8 | |||
9 | |||
10 | #define RADEON_SCRATCH_ADDR 0x0774 |
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11 | |||
12 | |||
13 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
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14 | #define RADEON_CP_ME_RAM_DATAH 0x07dc |
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15 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
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16 | |||
17 | |||
18 | #define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
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19 | |||
20 | |||
21 | |||
22 | #define RADEON_CP_RB_CNTL 0x0704 |
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23 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
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24 | # define RADEON_RB_NO_UPDATE (1 << 27) |
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25 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
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26 | #define RADEON_CP_RB_RPTR 0x0710 |
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27 | #define RADEON_CP_RB_WPTR 0x0714 |
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28 | |||
29 | |||
30 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
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31 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
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32 | |||
33 | |||
34 | |||
35 | |||
36 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
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37 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
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38 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
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39 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
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40 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
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41 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
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42 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
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43 | |||
44 | |||
45 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
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46 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
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47 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
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48 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
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49 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
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50 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
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51 | |||
52 | |||
53 | |||
54 | |||
55 | |||
56 | |||
813 | serge | 57 | |
58 | |||
59 | # define RADEON_PLL_WR_EN (1 << 7) |
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60 | # define RADEON_PLL_DIV_SEL (3 << 8) |
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61 | # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
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62 | |||
63 | |||
64 | # define RADEON_FORCEON_MCLKA (1 << 16) |
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65 | # define RADEON_FORCEON_MCLKB (1 << 17) |
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66 | # define RADEON_FORCEON_YCLKA (1 << 18) |
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67 | # define RADEON_FORCEON_YCLKB (1 << 19) |
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68 | # define RADEON_FORCEON_MC (1 << 20) |
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69 | # define RADEON_FORCEON_AIC (1 << 21) |
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70 | # define R300_DISABLE_MC_MCLKA (1 << 21) |
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71 | # define R300_DISABLE_MC_MCLKB (1 << 21) |
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72 | |||
73 | |||
74 | |||
75 | { |
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76 | |||
77 | |||
78 | * revisions of the R300. This workaround should be called after every |
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79 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
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80 | * may not be correct. |
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81 | */ |
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82 | if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
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881 | serge | 83 | { |
813 | serge | 84 | u32_t save, tmp; |
85 | |||
86 | |||
87 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
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88 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
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89 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
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90 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
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91 | } |
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92 | } |
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93 | |||
94 | |||
95 | |||
96 | u32_t RADEONINPLL(int addr) |
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97 | { |
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98 | u32_t data; |
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99 | |||
100 | |||
101 | //RADEONPllErrataAfterIndex(); |
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102 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
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103 | RADEONPllErrataAfterData(); |
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104 | |||
105 | |||
106 | }; |
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107 | |||
108 | |||
109 | void RADEONOUTPLL(int addr, u32_t data) |
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110 | { |
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111 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
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112 | RADEON_PLL_WR_EN)); |
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113 | // RADEONPllErrataAfterIndex(info); |
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114 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
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115 | RADEONPllErrataAfterData(); |
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116 | } |
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117 | |||
118 | |||
119 | |||
120 | |||
808 | serge | 121 | R5xxFIFOWaitLocal(u32_t required) //R100-R500 |
877 | serge | 122 | { |
808 | serge | 123 | int i; |
124 | |||
125 | |||
126 | if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
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127 | return TRUE; |
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128 | |||
129 | |||
130 | (unsigned int) INREG(R5XX_RBBM_STATUS)); |
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131 | return FALSE; |
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132 | } |
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133 | |||
134 | |||
135 | * Flush all dirty data in the Pixel Cache to memory. |
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136 | */ |
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137 | |||
138 | |||
139 | R5xx2DFlush() |
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140 | { |
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141 | int i; |
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142 | |||
143 | |||
144 | R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
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145 | |||
146 | |||
147 | if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
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148 | return TRUE; |
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149 | |||
150 | |||
151 | (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
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152 | return FALSE; |
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153 | } |
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154 | |||
155 | |||
156 | R5xx2DIdleLocal() //R100-R500 |
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157 | { |
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158 | int i; |
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159 | |||
160 | |||
161 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
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162 | if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
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163 | break; |
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164 | |||
165 | |||
166 | dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
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167 | return FALSE; |
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168 | } |
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169 | |||
170 | |||
171 | for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
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172 | if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
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173 | R5xx2DFlush(); |
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174 | return TRUE; |
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175 | } |
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176 | } |
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177 | dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
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178 | return FALSE; |
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179 | |||
180 | |||
181 | |||
182 | |||
183 | R5xx2DReset() |
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184 | { |
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185 | u32_t save, tmp; |
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877 | serge | 186 | u32_t clock_cntl_index; |
813 | serge | 187 | u32_t mclk_cntl; |
188 | |||
808 | serge | 189 | |
190 | * an R300 after the command processor got stuck. */ |
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191 | save = INREG(R5XX_RBBM_SOFT_RESET); |
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192 | tmp = save | R5XX_SOFT_RESET_CP | |
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193 | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE | |
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194 | R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP | |
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195 | R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB; |
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196 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
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197 | |||
198 | |||
199 | tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | |
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200 | R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE | |
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201 | R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 | |
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202 | R5XX_SOFT_RESET_RB); |
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203 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
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204 | |||
205 | |||
206 | OUTREG(R5XX_RBBM_SOFT_RESET, save); |
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207 | INREG(R5XX_RBBM_SOFT_RESET); |
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208 | |||
209 | |||
210 | |||
211 | |||
813 | serge | 212 | clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
213 | RADEONPllErrataAfterIndex(info); |
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214 | |||
215 | |||
216 | |||
217 | |||
218 | RADEON_FORCEON_MCLKA | |
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219 | RADEON_FORCEON_MCLKB | |
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220 | RADEON_FORCEON_YCLKA | |
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221 | RADEON_FORCEON_YCLKB | |
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222 | RADEON_FORCEON_MC | |
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223 | RADEON_FORCEON_AIC)); |
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224 | #endif |
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225 | |||
226 | |||
808 | serge | 227 | * unexpected behaviour on some machines. Here we use |
228 | * R5XX_HOST_PATH_CNTL to reset it. */ |
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229 | save = INREG(R5XX_HOST_PATH_CNTL); |
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230 | |||
231 | |||
232 | tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2; |
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233 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
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234 | |||
235 | |||
236 | OUTREG(R5XX_RBBM_SOFT_RESET, 0); |
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237 | |||
238 | |||
239 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
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240 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
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241 | |||
242 | |||
243 | INREG(R5XX_HOST_PATH_CNTL); |
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244 | OUTREG(R5XX_HOST_PATH_CNTL, save); |
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245 | |||
813 | serge | 246 | |
247 | OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
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248 | RADEONPllErrataAfterIndex(info); |
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249 | RADEONOUTPLL(RADEON_MCLK_CNTL, mclk_cntl); |
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250 | #endif |
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251 | } |
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808 | serge | 252 | |
253 | |||
254 | R5xx2DSetup() |
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255 | { |
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256 | |||
257 | |||
258 | * set them appropriately before any accel ops, but let's avoid |
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259 | * random bogus DMA in case we inadvertently trigger the engine |
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260 | * in the wrong place (happened). */ |
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261 | R5xxFIFOWaitLocal(2); |
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262 | OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
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263 | OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
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264 | |||
265 | |||
266 | MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
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267 | |||
268 | |||
269 | |||
270 | |||
271 | OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, |
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272 | R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX); |
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273 | R5xxFIFOWaitLocal(1); |
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274 | OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | |
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275 | R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); |
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276 | |||
277 | |||
278 | OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); |
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279 | OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); |
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280 | OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); |
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281 | OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); |
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282 | OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
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283 | |||
284 | |||
285 | } |
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286 | |||
287 | |||
877 | serge | 288 | { |
808 | serge | 289 | if (!R5xxFIFOWaitLocal(required)) { |
290 | R5xx2DReset(); |
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291 | R5xx2DSetup(); |
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292 | } |
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293 | } |
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294 | |||
295 | |||
296 | { |
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297 | if (!R5xx2DIdleLocal()) { |
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298 | R5xx2DReset(); |
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299 | R5xx2DSetup(); |
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300 | } |
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301 | } |
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302 | |||
303 | |||
304 | { |
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305 | u32_t ifl; |
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877 | serge | 306 | int i; |
808 | serge | 307 | |
308 | |||
309 | |||
310 | |||
812 | serge | 311 | |
312 | |||
808 | serge | 313 | |
812 | serge | 314 | |
881 | serge | 315 | { |
808 | serge | 316 | case CHIP_FAMILY_R300: |
881 | serge | 317 | case CHIP_FAMILY_R350: |
318 | case CHIP_FAMILY_RV350: |
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319 | dbgprintf("Loading R300 microcode\n"); |
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812 | serge | 320 | for (i = 0; i < 256; i++) |
321 | { |
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322 | OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); |
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323 | OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); |
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324 | } |
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325 | break; |
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326 | /* |
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881 | serge | 327 | case RHD_RV505: |
812 | serge | 328 | case RHD_RV515: |
329 | case RHD_RV516: |
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330 | case RHD_R520: |
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331 | case RHD_RV530: |
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332 | case RHD_RV535: |
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333 | case RHD_RV550: |
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334 | case RHD_RV560: |
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335 | case RHD_RV570: |
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336 | case RHD_R580: |
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337 | dbgprintf("Loading R500 microcode\n"); |
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338 | for (i = 0; i < 256; i++) |
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339 | { |
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340 | OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); |
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341 | OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); |
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342 | } |
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343 | */ |
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881 | serge | 344 | } |
808 | serge | 345 | safe_sti(ifl); |
346 | }; |
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347 | |||
348 | |||
349 | |||
350 | { |
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351 | u32_t base; |
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877 | serge | 352 | int screensize; |
878 | serge | 353 | int screenpitch; |
354 | |||
808 | serge | 355 | |
878 | serge | 356 | screenpitch = GetScreenPitch(); |
357 | |||
808 | serge | 358 | |
878 | serge | 359 | rhd.displayHeight = screensize & 0xFFFF; |
360 | |||
361 | |||
808 | serge | 362 | rhd.__ymin = 0; |
363 | rhd.__xmax = rhd.displayWidth - 1; |
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364 | rhd.__ymax = rhd.displayHeight - 1; |
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365 | |||
366 | |||
367 | clip.ymin = 0; |
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368 | clip.xmax = rhd.displayWidth - 1; |
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369 | clip.ymax = rhd.displayHeight - 1; |
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370 | |||
371 | |||
372 | dbgprintf("height %d \n", rhd.displayHeight); |
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373 | |||
374 | |||
375 | R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL; |
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376 | |||
377 | |||
378 | |||
379 | |||
380 | rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10); |
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881 | serge | 381 | |
808 | serge | 382 | |
383 | |||
384 | |||
815 | serge | 385 | |
386 | scr_pixmap.height = rhd.displayHeight; |
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387 | scr_pixmap.format = PICT_a8r8g8b8; |
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388 | scr_pixmap.pitch = screenpitch; |
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878 | serge | 389 | scr_pixmap.local = (void*)rhd.fbLocation; |
881 | serge | 390 | scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
815 | serge | 391 | scr_pixmap.mapped = (void*)0; |
876 | serge | 392 | |
815 | serge | 393 | |
394 | |||
808 | serge | 395 | OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN); |
396 | MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG); |
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397 | MASKREG(R5XX_RB2D_DSTCACHE_MODE, |
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398 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
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399 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
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400 | |||
401 | |||
402 | |||
403 | R5xx2DSetup(); |
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404 | |||
405 | |||
406 | |||
407 | |||
868 | serge | 408 | |
808 | serge | 409 | |
879 | serge | 410 | // dbgprintf("create cp ring buffer %x\n", rhd.ring_base); |
411 | // base = GetPgAddr(rhd.ring_base); |
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412 | |||
808 | serge | 413 | |
879 | serge | 414 | // dbgprintf("ring base %x\n", base); |
415 | |||
808 | serge | 416 | |
879 | serge | 417 | |
808 | serge | 418 | |
879 | serge | 419 | // OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
420 | |||
808 | serge | 421 | |
879 | serge | 422 | |
808 | serge | 423 | |
879 | serge | 424 | // OUTREG(RADEON_SCRATCH_UMSK, 0); // no scratch update |
425 | |||
808 | serge | 426 | |
879 | serge | 427 | |
808 | serge | 428 | |
879 | serge | 429 | |
808 | serge | 430 | |
879 | serge | 431 | // RADEON_ISYNC_ANY3D_IDLE2D | |
432 | // RADEON_ISYNC_WAIT_IDLEGUI | |
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433 | // RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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434 | |||
808 | serge | 435 | |
879 | serge | 436 | |
808 | serge | 437 | |
438 |