Rev 877 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
808 | serge | 1 | |
881 | serge | 2 | #include "radeon_chipset_gen.h" |
3 | #include "radeon_chipinfo_gen.h" |
||
4 | |||
808 | serge | 5 | |
812 | serge | 6 | |
7 | |||
808 | serge | 8 | xf86TokenToString(SymTabPtr table, int token) |
9 | { |
||
10 | int i; |
||
11 | |||
12 | |||
13 | |||
14 | |||
15 | return NULL; |
||
16 | else |
||
17 | return(table[i].name); |
||
18 | } |
||
19 | |||
20 | |||
881 | serge | 21 | |
22 | |||
23 | { |
||
24 | while(list->pci_device_id) |
||
25 | { |
||
26 | if(dev == list->pci_device_id) |
||
27 | return list; |
||
28 | list++; |
||
29 | } |
||
30 | return 0; |
||
31 | } |
||
32 | |||
33 | |||
34 | |||
808 | serge | 35 | { |
36 | const RADEONCardInfo *dev; |
||
881 | serge | 37 | u32_t bus, last_bus; |
877 | serge | 38 | |
808 | serge | 39 | |
40 | return 0; |
||
41 | |||
42 | |||
43 | { |
||
44 | u32_t devfn; |
||
877 | serge | 45 | |
808 | serge | 46 | |
47 | { |
||
48 | u32_t id; |
||
877 | serge | 49 | id = PciRead32(bus,devfn, 0); |
808 | serge | 50 | |
51 | |||
877 | serge | 52 | continue; |
808 | serge | 53 | |
54 | |||
881 | serge | 55 | |
56 | |||
57 | { |
||
808 | serge | 58 | u32_t reg2C; |
877 | serge | 59 | int i; |
808 | serge | 60 | |
61 | |||
881 | serge | 62 | if (!rhd.chipset) |
63 | { |
||
64 | dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
||
65 | return FALSE; |
||
66 | } |
||
67 | dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",rhd.chipset,rhd.PciDeviceID); |
||
68 | |||
808 | serge | 69 | |
70 | rhd.devfn = devfn; |
||
71 | rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
||
72 | |||
73 | |||
881 | serge | 74 | rhd.IsMobility = dev->mobility; |
75 | rhd.IsIGP = dev->igp; |
||
76 | |||
808 | serge | 77 | |
78 | |||
79 | |||
80 | rhd.subdevice_id = reg2C >> 16; |
||
81 | |||
82 | |||
881 | serge | 83 | dbgprintf("R600 unsupported yet.\nExit\n"); |
84 | |||
85 | |||
86 | |||
808 | serge | 87 | { |
88 | u32_t base; |
||
877 | serge | 89 | Bool validSize; |
808 | serge | 90 | |
91 | |||
92 | if(base) |
||
93 | { |
||
94 | if (base & PCI_MAP_IO) |
||
95 | { |
||
96 | rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
||
877 | serge | 97 | rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
808 | serge | 98 | } |
99 | else |
||
100 | { |
||
101 | rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
||
877 | serge | 102 | rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
808 | serge | 103 | } |
104 | } |
||
105 | rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
||
106 | } |
||
107 | return &rhd; |
||
108 | } |
||
109 | }; |
||
110 | }; |
||
111 | return NULL; |
||
112 | } |
||
113 | |||
114 | |||
115 | |||
116 | |||
877 | serge | 117 | { |
808 | serge | 118 | int offset; |
119 | u32_t addr1; |
||
877 | serge | 120 | u32_t addr2; |
121 | u32_t mask1; |
||
122 | u32_t mask2; |
||
123 | int bits = 0; |
||
808 | serge | 124 | |
125 | |||
126 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
||
127 | * the 6 base address registers, and 6 is the ROM base address register. |
||
128 | */ |
||
129 | if (index < 0 || index > 6) |
||
130 | return 0; |
||
131 | |||
132 | |||
133 | *min = destructive; |
||
134 | |||
135 | |||
136 | if (index == 6) |
||
137 | offset = PCI_MAP_ROM_REG; |
||
138 | else |
||
139 | offset = PCI_MAP_REG_START + (index << 2); |
||
140 | |||
141 | |||
142 | /* |
||
143 | * Check if this is the second part of a 64 bit address. |
||
144 | * XXX need to check how endianness affects 64 bit addresses. |
||
145 | */ |
||
146 | if (index > 0 && index < 6) { |
||
147 | addr2 = PciRead32(bus, devfn, offset - 4); |
||
148 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
||
149 | return 0; |
||
150 | } |
||
151 | |||
152 | |||
153 | PciWrite32(bus, devfn, offset, 0xffffffff); |
||
154 | mask1 = PciRead32(bus, devfn, offset); |
||
155 | PciWrite32(bus, devfn, offset, addr1); |
||
156 | } else { |
||
157 | mask1 = addr1; |
||
158 | } |
||
159 | |||
160 | |||
161 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
||
162 | { |
||
163 | if (PCIGETMEMORY(mask1) == 0) |
||
164 | { |
||
165 | addr2 = PciRead32(bus, devfn, offset + 4); |
||
166 | if (destructive) |
||
167 | { |
||
168 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
||
169 | mask2 = PciRead32(bus, devfn, offset + 4); |
||
170 | PciWrite32(bus, devfn, offset + 4, addr2); |
||
171 | } |
||
172 | else |
||
173 | { |
||
174 | mask2 = addr2; |
||
175 | } |
||
176 | if (mask2 == 0) |
||
177 | return 0; |
||
178 | bits = 32; |
||
179 | while ((mask2 & 1) == 0) |
||
180 | { |
||
181 | bits++; |
||
182 | mask2 >>= 1; |
||
183 | } |
||
184 | if (bits > 32) |
||
185 | return bits; |
||
186 | } |
||
187 | } |
||
188 | if (index < 6) |
||
189 | if (PCI_MAP_IS_MEM(mask1)) |
||
190 | mask1 = PCIGETMEMORY(mask1); |
||
191 | else |
||
192 | mask1 = PCIGETIO(mask1); |
||
193 | else |
||
194 | mask1 = PCIGETROM(mask1); |
||
195 | if (mask1 == 0) |
||
196 | return 0; |
||
197 | bits = 0; |
||
198 | while ((mask1 & 1) == 0) { |
||
199 | bits++; |
||
200 | mask1 >>= 1; |
||
201 | } |
||
202 | /* I/O maps can be no larger than 8 bits */ |
||
203 | |||
204 | |||
205 | bits = 8; |
||
206 | /* ROM maps can be no larger than 24 bits */ |
||
207 | if (index == 6 && bits > 24) |
||
208 | bits = 24; |
||
209 | return bits; |
||
210 | }>>>>><>>><>>256;devfn++) |
||
211 | >=last_bus;bus++) |
||
212 | |||
213 |