Rev 812 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 808 | serge | 1 | |
| 2 | /* R500 */ |
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| 3 | { RHD_RV505, "RV505" }, |
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| 4 | { RHD_RV515, "RV515" }, |
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| 5 | { RHD_RV516, "RV516" }, |
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| 6 | { RHD_R520, "R520" }, |
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| 7 | { RHD_RV530, "RV530" }, |
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| 8 | { RHD_RV535, "RV535" }, |
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| 9 | { RHD_RV550, "RV550" }, |
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| 10 | { RHD_RV560, "RV560" }, |
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| 11 | { RHD_RV570, "RV570" }, |
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| 12 | { RHD_R580, "R580" }, |
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| 13 | /* R500 Mobility */ |
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| 14 | { RHD_M52, "M52" }, |
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| 15 | { RHD_M54, "M54" }, |
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| 16 | { RHD_M56, "M56" }, |
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| 17 | { RHD_M58, "M58" }, |
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| 18 | { RHD_M62, "M62" }, |
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| 19 | { RHD_M64, "M64" }, |
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| 20 | { RHD_M66, "M66" }, |
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| 21 | { RHD_M68, "M68" }, |
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| 22 | { RHD_M71, "M71" }, |
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| 23 | /* R500 integrated */ |
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| 24 | { RHD_RS600, "RS600" }, |
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| 25 | { RHD_RS690, "RS690" }, |
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| 26 | { RHD_RS740, "RS740" }, |
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| 27 | /* R600 */ |
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| 28 | { RHD_R600, "R600" }, |
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| 29 | { RHD_RV610, "RV610" }, |
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| 30 | { RHD_RV630, "RV630" }, |
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| 31 | /* R600 Mobility */ |
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| 32 | { RHD_M72, "M72" }, |
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| 33 | { RHD_M74, "M74" }, |
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| 34 | { RHD_M76, "M76" }, |
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| 35 | /* RV670 came into existence after RV6x0 and M7x */ |
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| 36 | { RHD_RV670, "RV670" }, |
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| 37 | { RHD_R680, "R680" }, |
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| 38 | { RHD_RV620, "RV620" }, |
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| 39 | { RHD_RV635, "RV635" }, |
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| 40 | { -1, NULL } |
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| 41 | }; |
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| 42 | |||
| 43 | |||
| 812 | serge | 44 | |
| 45 | |||
| 46 | enum RHD_FAMILIES family; |
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| 47 | Bool IGP; |
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| 48 | } rhdChipsetMap[] = { |
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| 49 | { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_UNKNOWN */ |
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| 50 | |||
| 51 | |||
| 52 | { RHD_FAMILY_R350, 0 }, /* RHD_R350 */ |
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| 53 | { RHD_FAMILY_RV350, 0 }, /* RHD_RV350 */ |
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| 54 | { RHD_FAMILY_RV380, 0 }, /* RHD_RV370 */ |
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| 55 | { RHD_FAMILY_RV380, 0 }, /* RHD_RV380 */ |
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| 56 | |||
| 57 | |||
| 58 | |||
| 59 | { RHD_FAMILY_RV515, 0 }, /* RHD_RV515 */ |
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| 60 | { RHD_FAMILY_RV515, 0 }, /* RHD_RV516 */ |
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| 61 | { RHD_FAMILY_R520, 0 }, /* RHD_R520 */ |
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| 62 | { RHD_FAMILY_RV530, 0 }, /* RHD_RV530 */ |
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| 63 | { RHD_FAMILY_RV530, 0 }, /* RHD_RV535 */ |
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| 64 | { RHD_FAMILY_RV515, 0 }, /* RHD_RV550 */ |
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| 65 | { RHD_FAMILY_RV560, 0 }, /* RHD_RV560 */ |
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| 66 | { RHD_FAMILY_RV570, 0 }, /* RHD_RV570 */ |
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| 67 | { RHD_FAMILY_R580, 0 }, /* RHD_R580 */ |
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| 68 | { RHD_FAMILY_RV515, 0 }, /* RHD_M52 */ |
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| 69 | { RHD_FAMILY_RV515, 0 }, /* RHD_M54 */ |
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| 70 | { RHD_FAMILY_RV530, 0 }, /* RHD_M56 */ |
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| 71 | { RHD_FAMILY_R520, 0 }, /* RHD_M58 */ |
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| 72 | { RHD_FAMILY_RV515, 0 }, /* RHD_M62 */ |
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| 73 | { RHD_FAMILY_RV515, 0 }, /* RHD_M64 */ |
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| 74 | { RHD_FAMILY_RV530, 0 }, /* RHD_M66 */ |
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| 75 | { RHD_FAMILY_R580, 0 }, /* RHD_M68 */ |
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| 76 | { RHD_FAMILY_RV515, 0 }, /* RHD_M71 */ |
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| 77 | { RHD_FAMILY_RS690, 1 }, /* RHD_RS600 */ |
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| 78 | { RHD_FAMILY_RS690, 1 }, /* RHD_RS690 */ |
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| 79 | { RHD_FAMILY_RS690, 1 }, /* RHD_RS740 */ |
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| 80 | { RHD_FAMILY_R600, 0 }, /* RHD_R600 */ |
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| 81 | { RHD_FAMILY_RV610, 0 }, /* RHD_RV610 */ |
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| 82 | { RHD_FAMILY_RV630, 0 }, /* RHD_RV630 */ |
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| 83 | { RHD_FAMILY_RV610, 0 }, /* RHD_M72 */ |
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| 84 | { RHD_FAMILY_RV610, 0 }, /* RHD_M74 */ |
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| 85 | { RHD_FAMILY_RV630, 0 }, /* RHD_M76 */ |
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| 86 | { RHD_FAMILY_RV670, 0 }, /* RHD_RV670 */ |
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| 87 | { RHD_FAMILY_RV670, 0 }, /* RHD_R680 */ |
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| 88 | { RHD_FAMILY_RV620, 0 }, /* RHD_RV620 */ |
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| 89 | { RHD_FAMILY_RV620, 0 }, /* RHD_M82 */ |
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| 90 | { RHD_FAMILY_RV635, 0 }, /* RHD_RV635 */ |
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| 91 | { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_M86 */ |
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| 92 | { RHD_FAMILY_RS780, 1 } /* RHD_RS780 */ |
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| 93 | /* RHD_CHIP_END */ |
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| 94 | }; |
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| 95 | |||
| 96 | |||
| 97 | |||
| 808 | serge | 98 | # define PCI_ID_LIST PciChipset_t RHDPCIchipsets[] |
| 99 | # define LIST_END { 0, 0} |
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| 100 | |||
| 101 | |||
| 102 | |||
| 812 | serge | 103 | |
| 104 | RHD_DEVICE_MATCH( 0x4145, RHD_R300 ), /* ATI Radeon 9500 */ |
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| 105 | RHD_DEVICE_MATCH( 0x4146, RHD_R300 ), /* ATI Radeon 9600TX */ |
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| 106 | RHD_DEVICE_MATCH( 0x4147, RHD_R300 ), /* ATI FireGL Z1 */ |
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| 107 | RHD_DEVICE_MATCH( 0x4148, RHD_R350 ), /* ATI Radeon 9800SE */ |
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| 108 | RHD_DEVICE_MATCH( 0x4149, RHD_R350 ), /* ATI Radeon 9800 */ |
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| 109 | RHD_DEVICE_MATCH( 0x414A, RHD_R350 ), /* ATI Radeon 9800 */ |
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| 110 | RHD_DEVICE_MATCH( 0x414B, RHD_R350 ), /* ATI FireGL X2 */ |
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| 111 | |||
| 112 | |||
| 113 | RHD_DEVICE_MATCH( 0x4151, RHD_RV350 ), /* ATI Radeon 9600SE */ |
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| 114 | RHD_DEVICE_MATCH( 0x4152, RHD_RV350 ), /* ATI Radeon 9600XT */ |
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| 115 | RHD_DEVICE_MATCH( 0x4153, RHD_RV350 ), /* ATI Radeon 9600 */ |
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| 116 | RHD_DEVICE_MATCH( 0x4154, RHD_RV350 ), /* ATI FireGL T2 */ |
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| 117 | RHD_DEVICE_MATCH( 0x4155, RHD_RV350 ), /* ATI Radeon 9650 */ |
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| 118 | RHD_DEVICE_MATCH( 0x4156, RHD_RV350 ), /* ATI FireGL RV360 */ |
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| 119 | |||
| 120 | |||
| 121 | RHD_DEVICE_MATCH( 0x4E45, RHD_R300 ), |
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| 122 | RHD_DEVICE_MATCH( 0x4E46, RHD_R300 ), |
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| 123 | RHD_DEVICE_MATCH( 0x4E47, RHD_R300 ), |
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| 124 | RHD_DEVICE_MATCH( 0x4E48, RHD_R350 ), |
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| 125 | RHD_DEVICE_MATCH( 0x4E49, RHD_R350 ), |
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| 126 | RHD_DEVICE_MATCH( 0x4E4A, RHD_R350 ), |
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| 127 | RHD_DEVICE_MATCH( 0x4E4B, RHD_R350 ), |
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| 128 | RHD_DEVICE_MATCH( 0x4E50, RHD_RV350 ), |
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| 129 | RHD_DEVICE_MATCH( 0x4E51, RHD_RV350 ), |
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| 130 | RHD_DEVICE_MATCH( 0x4E52, RHD_RV350 ), |
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| 131 | RHD_DEVICE_MATCH( 0x4E53, RHD_RV350 ), |
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| 132 | RHD_DEVICE_MATCH( 0x4E54, RHD_RV350 ), |
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| 133 | RHD_DEVICE_MATCH( 0x4E56, RHD_RV350 ), |
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| 134 | |||
| 135 | |||
| 136 | |||
| 137 | RHD_DEVICE_MATCH( 0x5B62, RHD_RV380 ), |
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| 138 | RHD_DEVICE_MATCH( 0x5B63, RHD_RV380 ), |
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| 139 | RHD_DEVICE_MATCH( 0x5B64, RHD_RV380 ), |
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| 140 | RHD_DEVICE_MATCH( 0x5B65, RHD_RV380 ), |
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| 141 | |||
| 142 | |||
| 808 | serge | 143 | RHD_DEVICE_MATCH( 0x7101, RHD_M58 ), /* Mobility Radeon X1800 XT */ |
| 144 | RHD_DEVICE_MATCH( 0x7102, RHD_M58 ), /* Mobility Radeon X1800 */ |
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| 145 | RHD_DEVICE_MATCH( 0x7103, RHD_M58 ), /* Mobility FireGL V7200 */ |
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| 146 | RHD_DEVICE_MATCH( 0x7104, RHD_R520 ), /* FireGL V7200 */ |
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| 147 | RHD_DEVICE_MATCH( 0x7105, RHD_R520 ), /* FireGL V5300 */ |
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| 148 | RHD_DEVICE_MATCH( 0x7106, RHD_M58 ), /* Mobility FireGL V7100 */ |
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| 149 | RHD_DEVICE_MATCH( 0x7108, RHD_R520 ), /* Radeon X1800 */ |
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| 150 | RHD_DEVICE_MATCH( 0x7109, RHD_R520 ), /* Radeon X1800 */ |
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| 151 | RHD_DEVICE_MATCH( 0x710A, RHD_R520 ), /* Radeon X1800 */ |
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| 152 | RHD_DEVICE_MATCH( 0x710B, RHD_R520 ), /* Radeon X1800 */ |
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| 153 | RHD_DEVICE_MATCH( 0x710C, RHD_R520 ), /* Radeon X1800 */ |
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| 154 | RHD_DEVICE_MATCH( 0x710E, RHD_R520 ), /* FireGL V7300 */ |
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| 155 | RHD_DEVICE_MATCH( 0x710F, RHD_R520 ), /* FireGL V7350 */ |
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| 156 | RHD_DEVICE_MATCH( 0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */ |
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| 157 | RHD_DEVICE_MATCH( 0x7141, RHD_RV505 ), /* RV505 */ |
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| 158 | RHD_DEVICE_MATCH( 0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */ |
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| 159 | RHD_DEVICE_MATCH( 0x7143, RHD_RV505 ), /* Radeon X1550 */ |
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| 160 | RHD_DEVICE_MATCH( 0x7144, RHD_M54 ), /* M54-GL */ |
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| 161 | RHD_DEVICE_MATCH( 0x7145, RHD_M54 ), /* Mobility Radeon X1400 */ |
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| 162 | RHD_DEVICE_MATCH( 0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */ |
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| 163 | RHD_DEVICE_MATCH( 0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */ |
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| 164 | RHD_DEVICE_MATCH( 0x7149, RHD_M52 ), /* Mobility Radeon X1300 */ |
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| 165 | RHD_DEVICE_MATCH( 0x714A, RHD_M52 ), /* Mobility Radeon X1300 */ |
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| 166 | RHD_DEVICE_MATCH( 0x714B, RHD_M52 ), /* Mobility Radeon X1300 */ |
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| 167 | RHD_DEVICE_MATCH( 0x714C, RHD_M52 ), /* Mobility Radeon X1300 */ |
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| 168 | RHD_DEVICE_MATCH( 0x714D, RHD_RV515 ), /* Radeon X1300 */ |
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| 169 | RHD_DEVICE_MATCH( 0x714E, RHD_RV515 ), /* Radeon X1300 */ |
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| 170 | RHD_DEVICE_MATCH( 0x714F, RHD_RV505 ), /* RV505 */ |
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| 171 | RHD_DEVICE_MATCH( 0x7151, RHD_RV505 ), /* RV505 */ |
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| 172 | RHD_DEVICE_MATCH( 0x7152, RHD_RV515 ), /* FireGL V3300 */ |
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| 173 | RHD_DEVICE_MATCH( 0x7153, RHD_RV515 ), /* FireGL V3350 */ |
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| 174 | RHD_DEVICE_MATCH( 0x715E, RHD_RV515 ), /* Radeon X1300 */ |
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| 175 | RHD_DEVICE_MATCH( 0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */ |
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| 176 | RHD_DEVICE_MATCH( 0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */ |
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| 177 | RHD_DEVICE_MATCH( 0x7181, RHD_RV516 ), /* Radeon X1600 */ |
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| 178 | RHD_DEVICE_MATCH( 0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */ |
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| 179 | RHD_DEVICE_MATCH( 0x7186, RHD_M64 ), /* Mobility Radeon X1450 */ |
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| 180 | RHD_DEVICE_MATCH( 0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */ |
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| 181 | RHD_DEVICE_MATCH( 0x7188, RHD_M64 ), /* Mobility Radeon X2300 */ |
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| 182 | RHD_DEVICE_MATCH( 0x718A, RHD_M64 ), /* Mobility Radeon X2300 */ |
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| 183 | RHD_DEVICE_MATCH( 0x718B, RHD_M62 ), /* Mobility Radeon X1350 */ |
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| 184 | RHD_DEVICE_MATCH( 0x718C, RHD_M62 ), /* Mobility Radeon X1350 */ |
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| 185 | RHD_DEVICE_MATCH( 0x718D, RHD_M64 ), /* Mobility Radeon X1450 */ |
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| 186 | RHD_DEVICE_MATCH( 0x718F, RHD_RV516 ), /* Radeon X1300 */ |
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| 187 | RHD_DEVICE_MATCH( 0x7193, RHD_RV516 ), /* Radeon X1550 */ |
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| 188 | RHD_DEVICE_MATCH( 0x7196, RHD_M62 ), /* Mobility Radeon X1350 */ |
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| 189 | RHD_DEVICE_MATCH( 0x719B, RHD_RV516 ), /* FireMV 2250 */ |
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| 190 | RHD_DEVICE_MATCH( 0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */ |
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| 191 | RHD_DEVICE_MATCH( 0x71C0, RHD_RV530 ), /* Radeon X1600 */ |
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| 192 | RHD_DEVICE_MATCH( 0x71C1, RHD_RV535 ), /* Radeon X1650 */ |
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| 193 | RHD_DEVICE_MATCH( 0x71C2, RHD_RV530 ), /* Radeon X1600 */ |
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| 194 | RHD_DEVICE_MATCH( 0x71C3, RHD_RV535 ), /* Radeon X1600 */ |
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| 195 | RHD_DEVICE_MATCH( 0x71C4, RHD_M56 ), /* Mobility FireGL V5200 */ |
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| 196 | RHD_DEVICE_MATCH( 0x71C5, RHD_M56 ), /* Mobility Radeon X1600 */ |
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| 197 | RHD_DEVICE_MATCH( 0x71C6, RHD_RV530 ), /* Radeon X1650 */ |
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| 198 | RHD_DEVICE_MATCH( 0x71C7, RHD_RV535 ), /* Radeon X1650 */ |
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| 199 | RHD_DEVICE_MATCH( 0x71CD, RHD_RV530 ), /* Radeon X1600 */ |
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| 200 | RHD_DEVICE_MATCH( 0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */ |
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| 201 | RHD_DEVICE_MATCH( 0x71D2, RHD_RV530 ), /* FireGL V3400 */ |
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| 202 | RHD_DEVICE_MATCH( 0x71D4, RHD_M66 ), /* Mobility FireGL V5250 */ |
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| 203 | RHD_DEVICE_MATCH( 0x71D5, RHD_M66 ), /* Mobility Radeon X1700 */ |
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| 204 | RHD_DEVICE_MATCH( 0x71D6, RHD_M66 ), /* Mobility Radeon X1700 XT */ |
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| 205 | RHD_DEVICE_MATCH( 0x71DA, RHD_RV530 ), /* FireGL V5200 */ |
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| 206 | RHD_DEVICE_MATCH( 0x71DE, RHD_M66 ), /* Mobility Radeon X1700 */ |
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| 207 | RHD_DEVICE_MATCH( 0x7200, RHD_RV550 ), /* Radeon X2300HD */ |
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| 208 | RHD_DEVICE_MATCH( 0x7210, RHD_M71 ), /* Mobility Radeon HD 2300 */ |
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| 209 | RHD_DEVICE_MATCH( 0x7211, RHD_M71 ), /* Mobility Radeon HD 2300 */ |
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| 210 | RHD_DEVICE_MATCH( 0x7240, RHD_R580 ), /* Radeon X1950 */ |
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| 211 | RHD_DEVICE_MATCH( 0x7243, RHD_R580 ), /* Radeon X1900 */ |
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| 212 | RHD_DEVICE_MATCH( 0x7244, RHD_R580 ), /* Radeon X1950 */ |
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| 213 | RHD_DEVICE_MATCH( 0x7245, RHD_R580 ), /* Radeon X1900 */ |
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| 214 | RHD_DEVICE_MATCH( 0x7246, RHD_R580 ), /* Radeon X1900 */ |
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| 215 | RHD_DEVICE_MATCH( 0x7247, RHD_R580 ), /* Radeon X1900 */ |
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| 216 | RHD_DEVICE_MATCH( 0x7248, RHD_R580 ), /* Radeon X1900 */ |
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| 217 | RHD_DEVICE_MATCH( 0x7249, RHD_R580 ), /* Radeon X1900 */ |
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| 218 | RHD_DEVICE_MATCH( 0x724A, RHD_R580 ), /* Radeon X1900 */ |
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| 219 | RHD_DEVICE_MATCH( 0x724B, RHD_R580 ), /* Radeon X1900 */ |
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| 220 | RHD_DEVICE_MATCH( 0x724C, RHD_R580 ), /* Radeon X1900 */ |
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| 221 | RHD_DEVICE_MATCH( 0x724D, RHD_R580 ), /* Radeon X1900 */ |
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| 222 | RHD_DEVICE_MATCH( 0x724E, RHD_R580 ), /* AMD Stream Processor */ |
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| 223 | RHD_DEVICE_MATCH( 0x724F, RHD_R580 ), /* Radeon X1900 */ |
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| 224 | RHD_DEVICE_MATCH( 0x7280, RHD_RV570 ), /* Radeon X1950 */ |
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| 225 | RHD_DEVICE_MATCH( 0x7281, RHD_RV560 ), /* RV560 */ |
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| 226 | RHD_DEVICE_MATCH( 0x7283, RHD_RV560 ), /* RV560 */ |
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| 227 | RHD_DEVICE_MATCH( 0x7284, RHD_M68 ), /* Mobility Radeon X1900 */ |
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| 228 | RHD_DEVICE_MATCH( 0x7287, RHD_RV560 ), /* RV560 */ |
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| 229 | RHD_DEVICE_MATCH( 0x7288, RHD_RV570 ), /* Radeon X1950 GT */ |
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| 230 | RHD_DEVICE_MATCH( 0x7289, RHD_RV570 ), /* RV570 */ |
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| 231 | RHD_DEVICE_MATCH( 0x728B, RHD_RV570 ), /* RV570 */ |
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| 232 | RHD_DEVICE_MATCH( 0x728C, RHD_RV570 ), /* ATI FireGL V7400 */ |
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| 233 | RHD_DEVICE_MATCH( 0x7290, RHD_RV560 ), /* RV560 */ |
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| 234 | RHD_DEVICE_MATCH( 0x7291, RHD_RV560 ), /* Radeon X1650 */ |
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| 235 | RHD_DEVICE_MATCH( 0x7293, RHD_RV560 ), /* Radeon X1650 */ |
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| 236 | RHD_DEVICE_MATCH( 0x7297, RHD_RV560 ), /* RV560 */ |
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| 237 | RHD_DEVICE_MATCH( 0x791E, RHD_RS690 ), /* Radeon X1200 */ |
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| 238 | RHD_DEVICE_MATCH( 0x791F, RHD_RS690 ), /* Radeon X1200 */ |
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| 239 | RHD_DEVICE_MATCH( 0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */ |
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| 240 | RHD_DEVICE_MATCH( 0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */ |
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| 241 | RHD_DEVICE_MATCH( 0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */ |
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| 242 | RHD_DEVICE_MATCH( 0x796C, RHD_RS740 ), /* RS740 */ |
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| 243 | RHD_DEVICE_MATCH( 0x796D, RHD_RS740 ), /* RS740M */ |
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| 244 | RHD_DEVICE_MATCH( 0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */ |
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| 245 | RHD_DEVICE_MATCH( 0x796F, RHD_RS740 ), /* RS740M */ |
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| 246 | RHD_DEVICE_MATCH( 0x9400, RHD_R600 ), /* Radeon HD 2900 XT */ |
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| 247 | RHD_DEVICE_MATCH( 0x9401, RHD_R600 ), /* Radeon HD 2900 XT */ |
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| 248 | RHD_DEVICE_MATCH( 0x9402, RHD_R600 ), /* Radeon HD 2900 XT */ |
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| 249 | RHD_DEVICE_MATCH( 0x9403, RHD_R600 ), /* Radeon HD 2900 Pro */ |
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| 250 | RHD_DEVICE_MATCH( 0x9405, RHD_R600 ), /* Radeon HD 2900 GT */ |
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| 251 | RHD_DEVICE_MATCH( 0x940A, RHD_R600 ), /* FireGL V8650 */ |
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| 252 | RHD_DEVICE_MATCH( 0x940B, RHD_R600 ), /* FireGL V8600 */ |
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| 253 | RHD_DEVICE_MATCH( 0x940F, RHD_R600 ), /* FireGL V7600 */ |
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| 254 | RHD_DEVICE_MATCH( 0x94C0, RHD_RV610 ), /* RV610 */ |
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| 255 | RHD_DEVICE_MATCH( 0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */ |
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| 256 | RHD_DEVICE_MATCH( 0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */ |
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| 257 | RHD_DEVICE_MATCH( 0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */ |
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| 258 | RHD_DEVICE_MATCH( 0x94C5, RHD_RV610 ), /* FireGL V4000 */ |
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| 259 | RHD_DEVICE_MATCH( 0x94C6, RHD_RV610 ), /* RV610 */ |
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| 260 | RHD_DEVICE_MATCH( 0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */ |
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| 261 | RHD_DEVICE_MATCH( 0x94C8, RHD_M74 ), /* Mobility Radeon HD 2400 XT */ |
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| 262 | RHD_DEVICE_MATCH( 0x94C9, RHD_M72 ), /* Mobility Radeon HD 2400 */ |
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| 263 | RHD_DEVICE_MATCH( 0x94CB, RHD_M72 ), /* ATI RADEON E2400 */ |
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| 264 | RHD_DEVICE_MATCH( 0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */ |
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| 265 | RHD_DEVICE_MATCH( 0x9500, RHD_RV670 ), /* RV670 */ |
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| 266 | RHD_DEVICE_MATCH( 0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */ |
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| 267 | RHD_DEVICE_MATCH( 0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */ |
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| 268 | RHD_DEVICE_MATCH( 0x9507, RHD_RV670 ), /* RV670 */ |
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| 269 | RHD_DEVICE_MATCH( 0x950F, RHD_R680 ), /* ATI Radeon HD3870 X2 */ |
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| 270 | RHD_DEVICE_MATCH( 0x9511, RHD_RV670 ), /* ATI FireGL V7700 */ |
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| 271 | RHD_DEVICE_MATCH( 0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */ |
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| 272 | RHD_DEVICE_MATCH( 0x9580, RHD_RV630 ), /* RV630 */ |
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| 273 | RHD_DEVICE_MATCH( 0x9581, RHD_M76 ), /* Mobility Radeon HD 2600 */ |
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| 274 | RHD_DEVICE_MATCH( 0x9583, RHD_M76 ), /* Mobility Radeon HD 2600 XT */ |
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| 275 | RHD_DEVICE_MATCH( 0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */ |
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| 276 | RHD_DEVICE_MATCH( 0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */ |
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| 277 | RHD_DEVICE_MATCH( 0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */ |
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| 278 | RHD_DEVICE_MATCH( 0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */ |
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| 279 | RHD_DEVICE_MATCH( 0x958A, RHD_RV630 ), /* Gemini RV630 */ |
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| 280 | RHD_DEVICE_MATCH( 0x958B, RHD_M76 ), /* Gemini ATI Mobility Radeon HD 2600 XT */ |
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| 281 | RHD_DEVICE_MATCH( 0x958C, RHD_RV630 ), /* FireGL V5600 */ |
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| 282 | RHD_DEVICE_MATCH( 0x958D, RHD_RV630 ), /* FireGL V3600 */ |
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| 283 | RHD_DEVICE_MATCH( 0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */ |
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| 284 | RHD_DEVICE_MATCH( 0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ |
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| 285 | RHD_DEVICE_MATCH( 0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */ |
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| 286 | RHD_DEVICE_MATCH( 0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */ |
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| 287 | RHD_DEVICE_MATCH( 0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ |
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| 288 | RHD_DEVICE_MATCH( 0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */ |
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| 289 | RHD_DEVICE_MATCH( 0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ |
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| 290 | RHD_DEVICE_MATCH( 0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */ |
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| 291 | RHD_DEVICE_MATCH( 0x95C2, RHD_M82 ), /* ATI Mobility Radeon HD 3430 (M82) */ |
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| 292 | RHD_DEVICE_MATCH( 0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82) */ |
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| 293 | RHD_DEVICE_MATCH( 0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */ |
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| 294 | RHD_DEVICE_MATCH( 0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */ |
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| 295 | RHD_DEVICE_MATCH( 0x95CD, RHD_RV620 ), /* ATI FireMV 2450 */ |
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| 296 | RHD_DEVICE_MATCH( 0x95CE, RHD_RV620 ), /* ATI FireMV 2260 */ |
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| 297 | RHD_DEVICE_MATCH( 0x95CF, RHD_RV620 ), /* ATI FireMV 2260 */ |
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| 298 | LIST_END |
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| 299 | }; |
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| 300 | |||
| 301 | |||
| 302 | xf86TokenToString(SymTabPtr table, int token) |
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| 303 | { |
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| 304 | int i; |
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| 305 | |||
| 306 | |||
| 307 | |||
| 308 | |||
| 309 | return NULL; |
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| 310 | else |
||
| 311 | return(table[i].name); |
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| 312 | } |
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| 313 | |||
| 314 | |||
| 315 | { |
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| 316 | const PciChipset_t *dev; |
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| 317 | u32_t bus, last_bus; |
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| 877 | serge | 318 | |
| 808 | serge | 319 | |
| 320 | return 0; |
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| 321 | |||
| 322 | |||
| 323 | { |
||
| 324 | u32_t devfn; |
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| 877 | serge | 325 | |
| 808 | serge | 326 | |
| 327 | { |
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| 328 | u32_t id; |
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| 877 | serge | 329 | id = PciRead32(bus,devfn, 0); |
| 808 | serge | 330 | |
| 331 | |||
| 877 | serge | 332 | continue; |
| 808 | serge | 333 | |
| 334 | |||
| 335 | { |
||
| 336 | u32_t reg2C; |
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| 877 | serge | 337 | int i; |
| 808 | serge | 338 | |
| 339 | |||
| 340 | |||
| 341 | |||
| 342 | rhd.devfn = devfn; |
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| 343 | rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
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| 344 | |||
| 345 | |||
| 346 | |||
| 347 | |||
| 348 | |||
| 349 | |||
| 350 | rhd.subdevice_id = reg2C >> 16; |
||
| 351 | |||
| 352 | |||
| 353 | { |
||
| 354 | u32_t base; |
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| 877 | serge | 355 | Bool validSize; |
| 808 | serge | 356 | |
| 357 | |||
| 358 | if(base) |
||
| 359 | { |
||
| 360 | if (base & PCI_MAP_IO) |
||
| 361 | { |
||
| 362 | rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
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| 877 | serge | 363 | rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
| 808 | serge | 364 | } |
| 365 | else |
||
| 366 | { |
||
| 367 | rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
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| 877 | serge | 368 | rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
| 808 | serge | 369 | } |
| 370 | } |
||
| 371 | rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
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| 372 | } |
||
| 373 | rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID); |
||
| 374 | |||
| 375 | |||
| 376 | } |
||
| 377 | }; |
||
| 378 | }; |
||
| 379 | return NULL; |
||
| 380 | } |
||
| 381 | |||
| 382 | |||
| 877 | serge | 383 | { |
| 808 | serge | 384 | while(list->device) |
| 385 | { |
||
| 386 | if(dev==list->device) |
||
| 387 | return list; |
||
| 388 | list++; |
||
| 389 | } |
||
| 390 | return 0; |
||
| 391 | } |
||
| 392 | |||
| 393 | |||
| 394 | |||
| 877 | serge | 395 | { |
| 808 | serge | 396 | int offset; |
| 397 | u32_t addr1; |
||
| 877 | serge | 398 | u32_t addr2; |
| 399 | u32_t mask1; |
||
| 400 | u32_t mask2; |
||
| 401 | int bits = 0; |
||
| 808 | serge | 402 | |
| 403 | |||
| 404 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
||
| 405 | * the 6 base address registers, and 6 is the ROM base address register. |
||
| 406 | */ |
||
| 407 | if (index < 0 || index > 6) |
||
| 408 | return 0; |
||
| 409 | |||
| 410 | |||
| 411 | *min = destructive; |
||
| 412 | |||
| 413 | |||
| 414 | if (index == 6) |
||
| 415 | offset = PCI_MAP_ROM_REG; |
||
| 416 | else |
||
| 417 | offset = PCI_MAP_REG_START + (index << 2); |
||
| 418 | |||
| 419 | |||
| 420 | /* |
||
| 421 | * Check if this is the second part of a 64 bit address. |
||
| 422 | * XXX need to check how endianness affects 64 bit addresses. |
||
| 423 | */ |
||
| 424 | if (index > 0 && index < 6) { |
||
| 425 | addr2 = PciRead32(bus, devfn, offset - 4); |
||
| 426 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
||
| 427 | return 0; |
||
| 428 | } |
||
| 429 | |||
| 430 | |||
| 431 | PciWrite32(bus, devfn, offset, 0xffffffff); |
||
| 432 | mask1 = PciRead32(bus, devfn, offset); |
||
| 433 | PciWrite32(bus, devfn, offset, addr1); |
||
| 434 | } else { |
||
| 435 | mask1 = addr1; |
||
| 436 | } |
||
| 437 | |||
| 438 | |||
| 439 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
||
| 440 | { |
||
| 441 | if (PCIGETMEMORY(mask1) == 0) |
||
| 442 | { |
||
| 443 | addr2 = PciRead32(bus, devfn, offset + 4); |
||
| 444 | if (destructive) |
||
| 445 | { |
||
| 446 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
||
| 447 | mask2 = PciRead32(bus, devfn, offset + 4); |
||
| 448 | PciWrite32(bus, devfn, offset + 4, addr2); |
||
| 449 | } |
||
| 450 | else |
||
| 451 | { |
||
| 452 | mask2 = addr2; |
||
| 453 | } |
||
| 454 | if (mask2 == 0) |
||
| 455 | return 0; |
||
| 456 | bits = 32; |
||
| 457 | while ((mask2 & 1) == 0) |
||
| 458 | { |
||
| 459 | bits++; |
||
| 460 | mask2 >>= 1; |
||
| 461 | } |
||
| 462 | if (bits > 32) |
||
| 463 | return bits; |
||
| 464 | } |
||
| 465 | } |
||
| 466 | if (index < 6) |
||
| 467 | if (PCI_MAP_IS_MEM(mask1)) |
||
| 468 | mask1 = PCIGETMEMORY(mask1); |
||
| 469 | else |
||
| 470 | mask1 = PCIGETIO(mask1); |
||
| 471 | else |
||
| 472 | mask1 = PCIGETROM(mask1); |
||
| 473 | if (mask1 == 0) |
||
| 474 | return 0; |
||
| 475 | bits = 0; |
||
| 476 | while ((mask1 & 1) == 0) { |
||
| 477 | bits++; |
||
| 478 | mask1 >>= 1; |
||
| 479 | } |
||
| 480 | /* I/O maps can be no larger than 8 bits */ |
||
| 481 | |||
| 482 | |||
| 483 | bits = 8; |
||
| 484 | /* ROM maps can be no larger than 24 bits */ |
||
| 485 | if (index == 6 && bits > 24) |
||
| 486 | bits = 24; |
||
| 487 | return bits; |
||
| 488 | } |
||
| 489 | > |
||
| 490 | |||
| 491 |