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Rev | Author | Line No. | Line |
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808 | serge | 1 | |
881 | serge | 2 | #include "radeon_chipset_gen.h" |
3 | #include "radeon_chipinfo_gen.h" |
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4 | |||
808 | serge | 5 | |
812 | serge | 6 | |
7 | |||
808 | serge | 8 | xf86TokenToString(SymTabPtr table, int token) |
9 | { |
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10 | int i; |
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11 | |||
12 | |||
13 | |||
14 | |||
15 | return NULL; |
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16 | else |
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17 | return(table[i].name); |
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18 | } |
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19 | |||
20 | |||
881 | serge | 21 | |
22 | |||
23 | { |
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24 | while(list->pci_device_id) |
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25 | { |
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26 | if(dev == list->pci_device_id) |
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27 | return list; |
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28 | list++; |
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29 | } |
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30 | return 0; |
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31 | } |
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32 | |||
33 | |||
34 | |||
808 | serge | 35 | { |
36 | const RADEONCardInfo *dev; |
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1002 | serge | 37 | u32_t bus, last_bus; |
38 | |||
808 | serge | 39 | |
1002 | serge | 40 | return 0; |
41 | |||
808 | serge | 42 | |
1002 | serge | 43 | { |
808 | serge | 44 | u32_t devfn; |
1002 | serge | 45 | |
808 | serge | 46 | |
1002 | serge | 47 | { |
48 | u32_t id; |
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49 | id = PciRead32(bus,devfn, 0); |
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50 | |||
808 | serge | 51 | |
1002 | serge | 52 | continue; |
53 | |||
881 | serge | 54 | |
1002 | serge | 55 | |
808 | serge | 56 | |
1002 | serge | 57 | { |
58 | u32_t reg2C; |
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59 | int i; |
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60 | |||
808 | serge | 61 | |
1002 | serge | 62 | if (!rhd.chipset){ |
63 | dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
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64 | return FALSE; |
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65 | } |
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66 | dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n", |
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67 | rhd.chipset,rhd.PciDeviceID); |
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68 | |||
808 | serge | 69 | |
1002 | serge | 70 | rhd.devfn = devfn; |
71 | rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
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72 | |||
808 | serge | 73 | |
1002 | serge | 74 | rhd.IsMobility = dev->mobility; |
75 | rhd.IsIGP = dev->igp; |
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76 | rhd.HasCRTC2 = !dev->nocrtc2; |
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77 | |||
808 | serge | 78 | |
1002 | serge | 79 | |
808 | serge | 80 | |
1002 | serge | 81 | rhd.subdevice_id = reg2C >> 16; |
82 | |||
881 | serge | 83 | |
1002 | serge | 84 | dbgprintf("R600 unsupported yet.\nExit\n"); |
85 | |||
881 | serge | 86 | |
808 | serge | 87 | |
1002 | serge | 88 | { |
89 | u32_t base; |
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90 | Bool validSize; |
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91 | |||
92 | |||
93 | if(base) |
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94 | { |
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95 | if (base & PCI_MAP_IO){ |
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96 | rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
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97 | rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
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98 | } |
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99 | else{ |
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100 | rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
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101 | rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
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102 | } |
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103 | } |
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104 | rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
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105 | } |
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106 | return &rhd; |
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107 | } |
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808 | serge | 108 | } |
109 | }; |
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110 | return NULL; |
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1002 | serge | 111 | } |
808 | serge | 112 | |
113 | |||
114 | |||
115 | |||
877 | serge | 116 | { |
808 | serge | 117 | int offset; |
118 | u32_t addr1; |
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877 | serge | 119 | u32_t addr2; |
120 | u32_t mask1; |
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121 | u32_t mask2; |
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122 | int bits = 0; |
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808 | serge | 123 | |
124 | |||
125 | * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
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126 | * the 6 base address registers, and 6 is the ROM base address register. |
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127 | */ |
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128 | if (index < 0 || index > 6) |
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129 | return 0; |
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130 | |||
131 | |||
132 | *min = destructive; |
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133 | |||
134 | |||
135 | if (index == 6) |
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136 | offset = PCI_MAP_ROM_REG; |
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137 | else |
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138 | offset = PCI_MAP_REG_START + (index << 2); |
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139 | |||
140 | |||
141 | /* |
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142 | * Check if this is the second part of a 64 bit address. |
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143 | * XXX need to check how endianness affects 64 bit addresses. |
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144 | */ |
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145 | if (index > 0 && index < 6) { |
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146 | addr2 = PciRead32(bus, devfn, offset - 4); |
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147 | if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
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148 | return 0; |
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149 | } |
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150 | |||
151 | |||
152 | PciWrite32(bus, devfn, offset, 0xffffffff); |
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153 | mask1 = PciRead32(bus, devfn, offset); |
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154 | PciWrite32(bus, devfn, offset, addr1); |
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155 | } else { |
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156 | mask1 = addr1; |
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157 | } |
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158 | |||
159 | |||
160 | if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
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161 | { |
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162 | if (PCIGETMEMORY(mask1) == 0) |
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163 | { |
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164 | addr2 = PciRead32(bus, devfn, offset + 4); |
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165 | if (destructive) |
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166 | { |
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167 | PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
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168 | mask2 = PciRead32(bus, devfn, offset + 4); |
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169 | PciWrite32(bus, devfn, offset + 4, addr2); |
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170 | } |
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171 | else |
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172 | { |
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173 | mask2 = addr2; |
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174 | } |
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175 | if (mask2 == 0) |
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176 | return 0; |
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177 | bits = 32; |
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178 | while ((mask2 & 1) == 0) |
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179 | { |
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180 | bits++; |
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181 | mask2 >>= 1; |
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182 | } |
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183 | if (bits > 32) |
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184 | return bits; |
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185 | } |
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186 | } |
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187 | if (index < 6) |
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188 | if (PCI_MAP_IS_MEM(mask1)) |
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189 | mask1 = PCIGETMEMORY(mask1); |
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190 | else |
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191 | mask1 = PCIGETIO(mask1); |
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192 | else |
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193 | mask1 = PCIGETROM(mask1); |
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194 | if (mask1 == 0) |
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195 | return 0; |
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196 | bits = 0; |
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197 | while ((mask1 & 1) == 0) { |
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198 | bits++; |
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199 | mask1 >>= 1; |
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200 | } |
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201 | /* I/O maps can be no larger than 8 bits */ |
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202 | |||
203 | |||
204 | bits = 8; |
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205 | /* ROM maps can be no larger than 24 bits */ |
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206 | if (index == 6 && bits > 24) |
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207 | bits = 24; |
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208 | return bits; |
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209 | }>>>>><>>><>>256;devfn++) |
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210 | >=last_bus;bus++) |
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211 | |||
212 |