Rev 883 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 883 | serge | 1 | #define RADEON_SCRATCH_REG0 0x15e0 |
| 2 | #define RADEON_SCRATCH_REG1 0x15e4 |
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| 3 | #define RADEON_SCRATCH_REG2 0x15e8 |
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| 4 | #define RADEON_SCRATCH_REG3 0x15ec |
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| 5 | #define RADEON_SCRATCH_REG4 0x15f0 |
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| 6 | #define RADEON_SCRATCH_REG5 0x15f4 |
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| 7 | #define RADEON_SCRATCH_UMSK 0x0770 |
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| 8 | #define RADEON_SCRATCH_ADDR 0x0774 |
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| 9 | |||
| 10 | # define RS400_BUS_MASTER_DIS (1 << 14) |
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| 11 | //# define RADEON_BUS_MASTER_DIS (1 << 6) |
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| 12 | |||
| 13 | #define RADEON_ISYNC_CNTL 0x1724 |
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| 14 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
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| 15 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
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| 16 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
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| 17 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
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| 18 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
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| 19 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
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| 20 | |||
| 21 | |||
| 22 | #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ |
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| 23 | #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ |
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| 24 | |||
| 25 | |||
| 26 | void RADEONPllErrataAfterIndex() |
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| 27 | { |
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| 28 | if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
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| 29 | return; |
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| 30 | |||
| 31 | /* This workaround is necessary on rv200 and RS200 or PLL |
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| 32 | * reads may return garbage (among others...) |
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| 33 | */ |
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| 34 | (void)INREG(RADEON_CLOCK_CNTL_DATA); |
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| 35 | (void)INREG(RADEON_CRTC_GEN_CNTL); |
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| 36 | } |
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| 37 | |||
| 38 | |||
| 39 | void RADEONPllErrataAfterData() |
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| 40 | { |
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| 41 | |||
| 42 | /* This function is required to workaround a hardware bug in some (all?) |
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| 43 | * revisions of the R300. This workaround should be called after every |
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| 44 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
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| 45 | * may not be correct. |
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| 46 | */ |
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| 47 | if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
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| 48 | { |
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| 49 | u32_t save, tmp; |
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| 50 | |||
| 51 | save = INREG(RADEON_CLOCK_CNTL_INDEX); |
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| 52 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
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| 53 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
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| 54 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
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| 55 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
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| 56 | } |
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| 57 | } |
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| 58 | |||
| 59 | |||
| 60 | /* Read PLL register */ |
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| 61 | u32_t RADEONINPLL(int addr) |
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| 62 | { |
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| 63 | u32_t data; |
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| 64 | |||
| 65 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
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| 66 | RADEONPllErrataAfterIndex(); |
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| 67 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
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| 68 | RADEONPllErrataAfterData(); |
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| 69 | |||
| 70 | return data; |
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| 71 | }; |
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| 72 | |||
| 73 | /* Write PLL information */ |
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| 74 | void RADEONOUTPLL(int addr, u32_t data) |
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| 75 | { |
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| 76 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
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| 77 | RADEON_PLL_WR_EN)); |
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| 78 | RADEONPllErrataAfterIndex(); |
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| 79 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
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| 80 | RADEONPllErrataAfterData(); |
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| 81 | } |
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| 82 | |||
| 83 | void RADEONEngineFlush(RHDPtr info) |
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| 84 | { |
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| 85 | int i; |
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| 86 | |||
| 87 | if (info->ChipFamily <= CHIP_FAMILY_RV280) |
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| 88 | { |
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| 89 | MASKREG(RADEON_RB3D_DSTCACHE_CTLSTAT,RADEON_RB3D_DC_FLUSH_ALL, |
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| 90 | ~RADEON_RB3D_DC_FLUSH_ALL); |
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| 91 | for (i = 0; i < RADEON_TIMEOUT; i++) { |
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| 92 | if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) |
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| 93 | break; |
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| 94 | } |
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| 95 | if (i == RADEON_TIMEOUT) { |
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| 96 | dbgprintf("DC flush timeout: %x\n", |
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| 97 | (u32_t)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); |
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| 98 | } |
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| 99 | } |
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| 100 | else |
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| 101 | { |
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| 102 | // MASKREG(R300_DSTCACHE_CTLSTAT,R300_RB2D_DC_FLUSH_ALL, |
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| 103 | // ~R300_RB2D_DC_FLUSH_ALL); |
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| 104 | // for (i = 0; i < RADEON_TIMEOUT; i++) { |
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| 105 | // if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) |
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| 106 | // break; |
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| 107 | // } |
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| 108 | // if (i == RADEON_TIMEOUT) { |
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| 109 | // dbgprintf("DC flush timeout: %x\n", |
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| 110 | // (u32_t)INREG(R300_DSTCACHE_CTLSTAT)); |
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| 111 | // } |
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| 112 | } |
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| 113 | } |
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| 114 | |||
| 115 | static Bool R5xxFIFOWaitLocal(u32_t required) //R100-R500 |
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| 116 | { |
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| 117 | int i; |
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| 118 | |||
| 119 | for (i = 0; i < RADEON_TIMEOUT; i++) |
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| 120 | if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK)) |
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| 121 | return TRUE; |
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| 122 | |||
| 123 | dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS)); |
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| 124 | return FALSE; |
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| 125 | } |
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| 126 | |||
| 127 | static int radeon_do_wait_for_idle() |
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| 128 | { |
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| 129 | int i, ret; |
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| 130 | |||
| 131 | ret = R5xxFIFOWaitLocal(64); |
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| 132 | if (ret) |
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| 133 | return ret; |
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| 134 | |||
| 135 | for (i = 0; i < RADEON_TIMEOUT; i++) |
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| 136 | { |
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| 137 | if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { |
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| 138 | RADEONEngineFlush(&rhd); |
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| 139 | return 0; |
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| 140 | } |
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| 141 | usleep(1); |
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| 142 | } |
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| 143 | dbgprintf("wait idle failed status : 0x%08X 0x%08X\n", |
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| 144 | INREG(RADEON_RBBM_STATUS), |
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| 145 | INREG(R300_VAP_CNTL_STATUS)); |
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| 146 | |||
| 147 | return 1; |
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| 148 | } |
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| 149 | |||
| 150 | |||
| 151 | static void init_pipes(RHDPtr info) |
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| 152 | { |
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| 153 | u32_t gb_tile_config = 0; |
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| 154 | |||
| 155 | if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
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| 156 | (info->ChipFamily == CHIP_FAMILY_R420) || |
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| 157 | (info->ChipFamily == CHIP_FAMILY_RS600) || |
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| 158 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 159 | (info->ChipFamily == CHIP_FAMILY_RS740) || |
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| 160 | (info->ChipFamily == CHIP_FAMILY_RS400) || |
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| 161 | (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
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| 162 | { |
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| 163 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
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| 164 | |||
| 165 | info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
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| 166 | if (IS_R500_3D) |
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| 167 | OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
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| 168 | } |
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| 169 | else |
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| 170 | { |
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| 171 | if ((info->ChipFamily == CHIP_FAMILY_R300) || |
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| 172 | (info->ChipFamily == CHIP_FAMILY_R350)) |
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| 173 | { |
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| 174 | /* R3xx chips */ |
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| 175 | info->num_gb_pipes = 2; |
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| 176 | } |
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| 177 | else { |
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| 178 | /* RV3xx chips */ |
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| 179 | info->num_gb_pipes = 1; |
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| 180 | } |
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| 181 | } |
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| 182 | |||
| 183 | if (IS_R300_3D || IS_R500_3D) |
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| 184 | { |
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| 185 | |||
| 186 | dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
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| 187 | |||
| 188 | switch(info->num_gb_pipes) { |
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| 189 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
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| 190 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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| 191 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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| 192 | default: |
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| 193 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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| 194 | } |
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| 195 | |||
| 196 | OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); |
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| 197 | OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 198 | OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
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| 199 | OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | |
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| 200 | R300_DC_AUTOFLUSH_ENABLE | |
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| 201 | R300_DC_DC_DISABLE_IGNORE_PE)); |
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| 202 | } |
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| 203 | else |
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| 204 | OUTREG(RADEON_RB3D_CNTL, 0); |
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| 205 | }; |
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| 206 | |||
| 207 | /* ================================================================ |
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| 208 | * CP control, initialization |
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| 209 | */ |
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| 210 | |||
| 211 | /* Load the microcode for the CP */ |
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| 212 | |||
| 213 | #include "radeon_microcode.h" |
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| 214 | |||
| 215 | static void load_microcode(RHDPtr info) |
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| 216 | { |
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| 217 | int i; |
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| 218 | const u32_t (*microcode)[2]; |
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| 219 | |||
| 220 | OUTREG(RADEON_CP_ME_RAM_ADDR, 0); |
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| 221 | |||
| 222 | if ( (info->ChipFamily == CHIP_FAMILY_LEGACY ) || |
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| 223 | (info->ChipFamily == CHIP_FAMILY_RADEON ) || |
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| 224 | (info->ChipFamily == CHIP_FAMILY_RV100 ) || |
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| 225 | (info->ChipFamily == CHIP_FAMILY_RV200 ) || |
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| 226 | (info->ChipFamily == CHIP_FAMILY_RS100 ) || |
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| 227 | (info->ChipFamily == CHIP_FAMILY_RS200 )) |
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| 228 | { |
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| 229 | microcode = R100_cp_microcode; |
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| 230 | dbgprintf("Loading R100 Microcode\n"); |
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| 231 | } |
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| 232 | else if ((info->ChipFamily == CHIP_FAMILY_R200 ) || |
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| 233 | (info->ChipFamily == CHIP_FAMILY_RV250) || |
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| 234 | (info->ChipFamily == CHIP_FAMILY_RV280) || |
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| 235 | (info->ChipFamily == CHIP_FAMILY_RS300)) |
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| 236 | { |
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| 237 | microcode = R200_cp_microcode; |
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| 238 | dbgprintf("Loading R200 Microcode\n"); |
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| 239 | } |
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| 240 | else if ((info->ChipFamily == CHIP_FAMILY_R300) || |
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| 241 | (info->ChipFamily == CHIP_FAMILY_R350) || |
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| 242 | (info->ChipFamily == CHIP_FAMILY_RV350) || |
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| 243 | (info->ChipFamily == CHIP_FAMILY_RV380) || |
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| 244 | (info->ChipFamily == CHIP_FAMILY_RS400) || |
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| 245 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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| 246 | { |
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| 247 | dbgprintf("Loading R300 Microcode\n"); |
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| 248 | microcode = R300_cp_microcode; |
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| 249 | } |
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| 250 | else if ((info->ChipFamily == CHIP_FAMILY_R420) || |
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| 251 | (info->ChipFamily == CHIP_FAMILY_RV410)) |
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| 252 | { |
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| 253 | dbgprintf("Loading R400 Microcode\n"); |
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| 254 | microcode = R420_cp_microcode; |
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| 255 | |||
| 256 | } |
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| 257 | else if ((info->ChipFamily == CHIP_FAMILY_RS600) || |
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| 258 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 259 | (info->ChipFamily == CHIP_FAMILY_RS740)) |
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| 260 | { |
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| 261 | dbgprintf("Loading RS690/RS740 Microcode\n"); |
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| 262 | microcode = RS690_cp_microcode; |
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| 263 | } |
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| 264 | else if ((info->ChipFamily == CHIP_FAMILY_RV515) || |
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| 265 | (info->ChipFamily == CHIP_FAMILY_R520) || |
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| 266 | (info->ChipFamily == CHIP_FAMILY_RV530) || |
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| 267 | (info->ChipFamily == CHIP_FAMILY_R580) || |
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| 268 | (info->ChipFamily == CHIP_FAMILY_RV560) || |
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| 269 | (info->ChipFamily == CHIP_FAMILY_RV570)) |
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| 270 | { |
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| 271 | dbgprintf("Loading R500 Microcode\n"); |
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| 272 | microcode = R520_cp_microcode; |
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| 273 | } |
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| 274 | |||
| 275 | for (i = 0; i < 256; i++) { |
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| 276 | OUTREG(RADEON_CP_ME_RAM_DATAH, microcode[i][1]); |
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| 277 | OUTREG(RADEON_CP_ME_RAM_DATAL, microcode[i][0]); |
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| 278 | } |
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| 279 | } |
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| 280 | |||
| 281 | |||
| 282 | void init_ring_buffer(RHDPtr info) |
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| 283 | { |
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| 284 | u32_t ring_base; |
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| 285 | u32_t tmp; |
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| 286 | |||
| 287 | info->ringBase = CreateRingBuffer( 64*1024, PG_SW); |
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| 288 | |||
| 289 | dbgprintf("create cp ring buffer %x\n", rhd.ringBase); |
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| 290 | ring_base = GetPgAddr(rhd.ringBase); |
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| 291 | dbgprintf("ring base %x\n", ring_base); |
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| 292 | |||
| 293 | OUTREG(RADEON_CP_RB_BASE, ring_base); |
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| 294 | |||
| 295 | info->ring_avail = 64*1024/4 ; |
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| 296 | |||
| 297 | /* Set the write pointer delay */ |
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| 298 | OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); |
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| 299 | |||
| 300 | /* Initialize the ring buffer's read and write pointers */ |
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| 301 | rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
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| 302 | rhd.host_rp = rhd.ring_rp; |
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| 303 | |||
| 304 | OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
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| 305 | |||
| 885 | serge | 306 | tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr((void*)&rhd.host_rp); |
| 883 | serge | 307 | |
| 308 | OUTREG(RADEON_CP_RB_RPTR_ADDR, tmp); // ring buffer read pointer |
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| 309 | |||
| 310 | /* Set ring buffer size */ |
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| 311 | OUTREG(RADEON_CP_RB_CNTL, (1<<27)|(0<<18)|(10<<8)|13); |
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| 312 | |||
| 313 | /* Initialize the scratch register pointer. This will cause |
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| 314 | * the scratch register values to be written out to memory |
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| 315 | * whenever they are updated. |
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| 316 | * |
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| 317 | * We simply put this behind the ring read pointer, this works |
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| 318 | * with PCI GART as well as (whatever kind of) AGP GART |
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| 319 | */ |
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| 320 | |||
| 885 | serge | 321 | tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr((void*)&rhd.scratch0); |
| 883 | serge | 322 | OUTREG(RADEON_SCRATCH_ADDR, tmp); |
| 323 | |||
| 324 | OUTREG(RADEON_SCRATCH_UMSK, 0x0); |
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| 325 | //OUTREG(0x778, 1); |
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| 326 | |||
| 327 | /* Turn on bus mastering */ |
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| 328 | if ( (info->ChipFamily == CHIP_FAMILY_RS400) || |
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| 329 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 330 | (info->ChipFamily == CHIP_FAMILY_RS740) ) |
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| 331 | { |
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| 332 | /* rs400, rs690/rs740 */ |
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| 333 | tmp = INREG(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; |
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| 334 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 335 | } |
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| 336 | else if (!((info->ChipFamily == CHIP_FAMILY_RV380) || |
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| 337 | (info->ChipFamily >= CHIP_FAMILY_R420))) |
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| 338 | { |
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| 339 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ |
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| 340 | tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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| 341 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 342 | } /* PCIE cards appears to not need this */ |
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| 343 | |||
| 344 | tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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| 345 | OUTREG(RADEON_BUS_CNTL, tmp); |
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| 346 | |||
| 347 | radeon_do_wait_for_idle(); |
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| 348 | |||
| 349 | /* Sync everything up */ |
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| 350 | OUTREG(RADEON_ISYNC_CNTL, |
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| 351 | (RADEON_ISYNC_ANY2D_IDLE3D | |
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| 352 | RADEON_ISYNC_ANY3D_IDLE2D | |
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| 353 | RADEON_ISYNC_WAIT_IDLEGUI | |
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| 354 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); |
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| 355 | } |
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| 356 | |||
| 357 | |||
| 358 | void radeon_engine_reset(RHDPtr info) |
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| 359 | { |
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| 360 | u32_t clock_cntl_index; |
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| 361 | u32_t mclk_cntl; |
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| 362 | u32_t rbbm_soft_reset; |
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| 363 | u32_t host_path_cntl; |
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| 364 | |||
| 365 | if (info->ChipFamily <= CHIP_FAMILY_RV410) |
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| 366 | { |
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| 367 | /* may need something similar for newer chips */ |
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| 368 | clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
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| 369 | mclk_cntl = INPLL( RADEON_MCLK_CNTL); |
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| 370 | |||
| 371 | OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | |
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| 372 | RADEON_FORCEON_MCLKA | |
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| 373 | RADEON_FORCEON_MCLKB | |
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| 374 | RADEON_FORCEON_YCLKA | |
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| 375 | RADEON_FORCEON_YCLKB | |
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| 376 | RADEON_FORCEON_MC | |
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| 377 | RADEON_FORCEON_AIC)); |
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| 378 | } |
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| 379 | |||
| 380 | rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); |
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| 381 | |||
| 382 | OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | |
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| 383 | RADEON_SOFT_RESET_CP | |
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| 384 | RADEON_SOFT_RESET_HI | |
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| 385 | RADEON_SOFT_RESET_SE | |
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| 386 | RADEON_SOFT_RESET_RE | |
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| 387 | RADEON_SOFT_RESET_PP | |
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| 388 | RADEON_SOFT_RESET_E2 | |
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| 389 | RADEON_SOFT_RESET_RB)); |
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| 390 | INREG(RADEON_RBBM_SOFT_RESET); |
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| 391 | OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & |
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| 392 | ~(RADEON_SOFT_RESET_CP | |
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| 393 | RADEON_SOFT_RESET_HI | |
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| 394 | RADEON_SOFT_RESET_SE | |
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| 395 | RADEON_SOFT_RESET_RE | |
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| 396 | RADEON_SOFT_RESET_PP | |
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| 397 | RADEON_SOFT_RESET_E2 | |
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| 398 | RADEON_SOFT_RESET_RB))); |
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| 399 | INREG(RADEON_RBBM_SOFT_RESET); |
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| 400 | |||
| 401 | if (info->ChipFamily <= CHIP_FAMILY_RV410) { |
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| 402 | OUTPLL(RADEON_MCLK_CNTL, mclk_cntl); |
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| 403 | OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
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| 404 | OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); |
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| 405 | } |
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| 406 | }; |
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| 407 | |||
| 408 | #define RADEON_WAIT_UNTIL_IDLE() do { \ |
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| 409 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 1 ) ); \ |
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| 410 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ |
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| 411 | RADEON_WAIT_3D_IDLECLEAN | \ |
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| 412 | RADEON_WAIT_HOST_IDLECLEAN) ); \ |
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| 413 | } while (0) |
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| 414 | |||
| 415 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
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| 416 | # define RADEON_RB3D_ZC_FLUSH (1 << 0) |
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| 417 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
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| 418 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
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| 419 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
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| 420 | # define R300_ZC_FLUSH (1 << 0) |
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| 421 | # define R300_ZC_FREE (1 << 1) |
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| 422 | # define R300_ZC_BUSY (1 << 31) |
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| 423 | # define RADEON_RB3D_DC_FLUSH (3 << 0) |
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| 424 | # define RADEON_RB3D_DC_FREE (3 << 2) |
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| 425 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
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| 426 | # define RADEON_RB3D_DC_BUSY (1 << 31) |
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| 427 | # define R300_RB3D_DC_FLUSH (2 << 0) |
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| 428 | # define R300_RB3D_DC_FREE (2 << 2) |
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| 429 | # |
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| 430 | #define RADEON_PURGE_CACHE() do { \ |
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| 431 | if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 432 | OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
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| 433 | OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ |
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| 434 | } else { \ |
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| 435 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
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| 436 | OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ |
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| 437 | } \ |
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| 438 | } while (0) |
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| 439 | |||
| 440 | #define RADEON_FLUSH_ZCACHE() do { \ |
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| 441 | if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 442 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 1 ) ); \ |
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| 443 | OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ |
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| 444 | } else { \ |
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| 445 | OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 1 ) ); \ |
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| 446 | OUT_RING( R300_ZC_FLUSH ); \ |
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| 447 | } \ |
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| 448 | } while (0) |
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| 449 | #define RADEON_PURGE_ZCACHE() do { \ |
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| 450 | if (rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
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| 451 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 1)); \ |
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| 452 | OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ |
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| 453 | } else { \ |
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| 454 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 1)); \ |
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| 455 | OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ |
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| 456 | } \ |
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| 457 | } while (0) |
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| 458 | |||
| 459 | static int radeon_cp_start(RHDPtr info) |
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| 460 | { |
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| 461 | u32_t *ring, write; |
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| 462 | u32_t ifl; |
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| 463 | radeon_do_wait_for_idle(64); |
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| 464 | |||
| 465 | OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
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| 466 | |||
| 467 | ifl = safe_cli(); |
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| 468 | |||
| 469 | BEGIN_RING(8); |
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| 470 | /* isync can only be written through cp on r5xx write it here */ |
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| 471 | OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 1)); |
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| 472 | OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | |
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| 473 | RADEON_ISYNC_ANY3D_IDLE2D | |
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| 474 | RADEON_ISYNC_WAIT_IDLEGUI | |
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| 475 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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| 476 | RADEON_PURGE_CACHE(); |
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| 477 | RADEON_PURGE_ZCACHE(); |
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| 478 | RADEON_WAIT_UNTIL_IDLE(); |
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| 479 | ADVANCE_RING(); |
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| 480 | COMMIT_RING(); |
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| 481 | |||
| 482 | safe_sti(ifl); |
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| 483 | |||
| 484 | radeon_do_wait_for_idle(); |
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| 485 | }; |
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| 486 | |||
| 487 | |||
| 488 | Bool init_cp(RHDPtr info) |
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| 489 | { |
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| 490 | load_microcode(&rhd); |
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| 491 | |||
| 492 | init_ring_buffer(&rhd); |
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| 493 | |||
| 494 | radeon_engine_reset(&rhd); |
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| 495 | |||
| 496 | /* setup the raster pipes */ |
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| 497 | init_pipes(&rhd); |
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| 498 | |||
| 499 | rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
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| 500 | OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp); |
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| 501 | |||
| 502 | radeon_cp_start(&rhd); |
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| 503 | |||
| 504 | }; |
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| 505 | |||
| 506 |