Rev 954 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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885 | serge | 1 | |
2 | |||
3 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
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4 | |||
5 | u32_t *ring; |
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6 | |||
7 | |||
8 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
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9 | |||
10 | ifl = safe_cli(); |
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11 | |||
12 | if (IS_R300_3D || IS_R500_3D) { |
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13 | |||
14 | BEGIN_ACCEL(3); |
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15 | |||
16 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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17 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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18 | FINISH_ACCEL(); |
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19 | |||
20 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
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21 | |||
22 | switch(info->num_gb_pipes) |
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23 | |||
24 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
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25 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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26 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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27 | default: |
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28 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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29 | } |
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30 | |||
31 | BEGIN_ACCEL(5); |
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32 | |||
33 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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34 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
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35 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
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36 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
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37 | FINISH_ACCEL(); |
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38 | |||
39 | if (IS_R500_3D) { |
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40 | |||
41 | BEGIN_ACCEL(2); |
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42 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
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43 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
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44 | FINISH_ACCEL(); |
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45 | } |
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46 | |||
47 | BEGIN_ACCEL(3); |
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48 | |||
49 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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50 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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51 | FINISH_ACCEL(); |
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52 | |||
53 | BEGIN_ACCEL(5); |
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54 | |||
55 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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56 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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57 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
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58 | (8 << R300_MS_Y0_SHIFT) | |
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59 | (8 << R300_MS_X1_SHIFT) | |
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60 | (8 << R300_MS_Y1_SHIFT) | |
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61 | (8 << R300_MS_X2_SHIFT) | |
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62 | (8 << R300_MS_Y2_SHIFT) | |
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63 | (8 << R300_MSBD0_Y_SHIFT) | |
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64 | (7 << R300_MSBD0_X_SHIFT))); |
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65 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
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66 | (8 << R300_MS_Y3_SHIFT) | |
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67 | (8 << R300_MS_X4_SHIFT) | |
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68 | (8 << R300_MS_Y4_SHIFT) | |
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69 | (8 << R300_MS_X5_SHIFT) | |
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70 | (8 << R300_MS_Y5_SHIFT) | |
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71 | (8 << R300_MSBD1_SHIFT))); |
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72 | FINISH_ACCEL(); |
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73 | |||
74 | BEGIN_ACCEL(5); |
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75 | |||
76 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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77 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
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78 | R300_COLOR_ROUND_NEAREST)); |
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79 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
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80 | R300_ALPHA0_SHADING_GOURAUD | |
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81 | R300_RGB1_SHADING_GOURAUD | |
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82 | R300_ALPHA1_SHADING_GOURAUD | |
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83 | R300_RGB2_SHADING_GOURAUD | |
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84 | R300_ALPHA2_SHADING_GOURAUD | |
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85 | R300_RGB3_SHADING_GOURAUD | |
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86 | R300_ALPHA3_SHADING_GOURAUD)); |
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87 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
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88 | FINISH_ACCEL(); |
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89 | |||
90 | BEGIN_ACCEL(5); |
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91 | |||
92 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
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93 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
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94 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
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95 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
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96 | FINISH_ACCEL(); |
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97 | |||
98 | /* setup the VAP */ |
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99 | |||
100 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
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101 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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102 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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103 | else |
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104 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
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105 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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106 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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107 | |||
108 | if (info->ChipFamily == CHIP_FAMILY_RV515) |
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109 | |||
110 | else if ((info->ChipFamily == CHIP_FAMILY_RV530) || |
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111 | (info->ChipFamily == CHIP_FAMILY_RV560) || |
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112 | (info->ChipFamily == CHIP_FAMILY_RV570)) |
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113 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
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114 | else if ((info->ChipFamily == CHIP_FAMILY_RV410) || |
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115 | (info->ChipFamily == CHIP_FAMILY_R420)) |
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116 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
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117 | else if ((info->ChipFamily == CHIP_FAMILY_R520) || |
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118 | (info->ChipFamily == CHIP_FAMILY_R580)) |
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119 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
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120 | else |
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121 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
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122 | |||
123 | if (info->has_tcl) |
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124 | |||
125 | else |
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126 | BEGIN_ACCEL(9); |
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127 | |||
128 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
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129 | |||
130 | |||
131 | if (info->has_tcl) |
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132 | |||
133 | else |
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134 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
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135 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
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136 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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137 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
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138 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
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139 | |||
140 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
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141 | |||
142 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
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143 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
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144 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
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145 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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146 | << R300_WRITE_ENA_0_SHIFT) | |
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147 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
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148 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
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149 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
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150 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
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151 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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152 | << R300_WRITE_ENA_1_SHIFT))); |
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153 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
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154 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
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155 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
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156 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
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157 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
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158 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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159 | << R300_WRITE_ENA_2_SHIFT))); |
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160 | |||
161 | if (info->has_tcl) { |
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162 | |||
163 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
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164 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
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165 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
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166 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
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167 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
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168 | } |
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169 | FINISH_ACCEL(); |
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170 | |||
171 | /* pre-load the vertex shaders */ |
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172 | |||
173 | /* exa mask/Xv bicubic shader program |
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174 | |||
175 | dcl_position v0 |
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176 | |||
177 | dcl_texcoord1 v2 |
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178 | |||
179 | mov oPos, v0 |
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180 | |||
181 | mov oT1, v2 */ |
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182 | |||
183 | |||
184 | |||
185 | |||
186 | /* PVS inst 0 */ |
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187 | OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
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188 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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189 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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190 | R300_PVS_DST_OFFSET(0) | |
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191 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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192 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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193 | OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
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194 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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195 | R300_PVS_SRC_OFFSET(0) | |
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196 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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197 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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198 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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199 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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200 | OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
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201 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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202 | R300_PVS_SRC_OFFSET(0) | |
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203 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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204 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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205 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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206 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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207 | OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
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208 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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209 | R300_PVS_SRC_OFFSET(0) | |
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210 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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211 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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212 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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213 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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214 | |||
215 | /* PVS inst 1 */ |
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216 | |||
217 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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218 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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219 | R300_PVS_DST_OFFSET(1) | |
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220 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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221 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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222 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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223 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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224 | R300_PVS_SRC_OFFSET(6) | |
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225 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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226 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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227 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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228 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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229 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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230 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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231 | R300_PVS_SRC_OFFSET(6) | |
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232 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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233 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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234 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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235 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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236 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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237 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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238 | R300_PVS_SRC_OFFSET(6) | |
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239 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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240 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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241 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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242 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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243 | |||
244 | /* PVS inst 2 */ |
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245 | |||
246 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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247 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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248 | R300_PVS_DST_OFFSET(2) | |
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249 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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250 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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251 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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252 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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253 | R300_PVS_SRC_OFFSET(7) | |
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254 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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255 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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256 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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257 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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258 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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259 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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260 | R300_PVS_SRC_OFFSET(7) | |
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261 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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262 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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263 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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264 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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265 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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266 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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267 | R300_PVS_SRC_OFFSET(7) | |
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268 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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269 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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270 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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271 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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272 | FINISH_ACCEL(); |
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273 | |||
274 | BEGIN_ACCEL(9); |
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275 | |||
276 | /* exa no mask instruction |
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277 | |||
278 | dcl_position v0 |
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279 | |||
280 | |||
281 | mov oPos, v0 |
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282 | |||
283 | |||
284 | |||
285 | |||
286 | |||
287 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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288 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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289 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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290 | R300_PVS_DST_OFFSET(0) | |
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291 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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292 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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293 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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294 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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295 | R300_PVS_SRC_OFFSET(0) | |
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296 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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297 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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298 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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299 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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300 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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301 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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302 | R300_PVS_SRC_OFFSET(0) | |
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303 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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304 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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305 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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306 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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307 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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308 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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309 | R300_PVS_SRC_OFFSET(0) | |
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310 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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311 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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312 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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313 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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314 | |||
315 | /* PVS inst 1 */ |
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316 | |||
317 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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318 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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319 | R300_PVS_DST_OFFSET(1) | |
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320 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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321 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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322 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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323 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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324 | R300_PVS_SRC_OFFSET(6) | |
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325 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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326 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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327 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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328 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
329 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
330 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
331 | R300_PVS_SRC_OFFSET(6) | |
||
332 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
333 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
334 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
335 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
336 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
337 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
338 | R300_PVS_SRC_OFFSET(6) | |
||
339 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
340 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
341 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
342 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
343 | FINISH_ACCEL(); |
||
344 | |||
345 | /* Xv shader program */ |
||
346 | |||
347 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
||
348 | |||
349 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
350 | |||
351 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
352 | R300_PVS_DST_OFFSET(0) | |
||
353 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
354 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
355 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
356 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
357 | R300_PVS_SRC_OFFSET(0) | |
||
358 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
359 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
360 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
361 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
362 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
363 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
364 | R300_PVS_SRC_OFFSET(0) | |
||
365 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
366 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
367 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
368 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
369 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
370 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
371 | R300_PVS_SRC_OFFSET(0) | |
||
372 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
373 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
374 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
375 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
376 | |||
377 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
378 | |||
379 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
380 | R300_PVS_DST_OFFSET(1) | |
||
381 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
382 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
383 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
384 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
385 | R300_PVS_SRC_OFFSET(6) | |
||
386 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
387 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
388 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
389 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
390 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
391 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
392 | R300_PVS_SRC_OFFSET(6) | |
||
393 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
394 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
395 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
396 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
397 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
398 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
399 | R300_PVS_SRC_OFFSET(6) | |
||
400 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
401 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
402 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
403 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
404 | FINISH_ACCEL(); |
||
405 | } |
||
406 | |||
407 | /* pre-load the RS instructions */ |
||
408 | |||
409 | if (IS_R300_3D) { |
||
410 | /* rasterizer source table |
||
411 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
412 | * 0,1 are tex0 |
||
413 | * 2,3 are tex1 |
||
414 | */ |
||
415 | OUT_ACCEL_REG(R300_RS_IP_0, |
||
416 | (R300_RS_TEX_PTR(0) | |
||
417 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
418 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
419 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
420 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
421 | OUT_ACCEL_REG(R300_RS_IP_1, |
||
422 | (R300_RS_TEX_PTR(2) | |
||
423 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
424 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
425 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
426 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
427 | /* src tex */ |
||
428 | /* R300_INST_TEX_ID - select the RS source table entry |
||
429 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
||
430 | */ |
||
431 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
||
432 | R300_RS_INST_TEX_CN_WRITE | |
||
433 | R300_INST_TEX_ADDR(0))); |
||
434 | /* mask tex */ |
||
435 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
||
436 | R300_RS_INST_TEX_CN_WRITE | |
||
437 | R300_INST_TEX_ADDR(1))); |
||
438 | |||
439 | } else { |
||
440 | |||
441 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
442 | * 0,1 are tex0 |
||
443 | * 2,3 are tex1 |
||
444 | */ |
||
445 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
446 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
447 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
448 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
449 | |||
450 | OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
451 | |||
452 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
453 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
454 | /* src tex */ |
||
455 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
||
456 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
||
457 | */ |
||
458 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
||
459 | R500_RS_INST_TEX_CN_WRITE | |
||
460 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
461 | /* mask tex */ |
||
462 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
||
463 | R500_RS_INST_TEX_CN_WRITE | |
||
464 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
465 | } |
||
466 | FINISH_ACCEL(); |
||
467 | |||
468 | /* pre-load FS tex instructions */ |
||
469 | |||
470 | BEGIN_ACCEL(2); |
||
471 | /* tex inst for src texture */ |
||
472 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
||
473 | (R300_TEX_SRC_ADDR(0) | |
||
474 | R300_TEX_DST_ADDR(0) | |
||
475 | R300_TEX_ID(0) | |
||
476 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
477 | |||
478 | /* tex inst for mask texture */ |
||
479 | |||
480 | (R300_TEX_SRC_ADDR(1) | |
||
481 | R300_TEX_DST_ADDR(1) | |
||
482 | R300_TEX_ID(1) | |
||
483 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
484 | FINISH_ACCEL(); |
||
485 | } |
||
486 | |||
487 | if (IS_R300_3D) { |
||
488 | |||
489 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
||
490 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
||
491 | (R300_ALU_START(0) | |
||
492 | R300_ALU_SIZE(0) | |
||
493 | R300_TEX_START(0) | |
||
494 | R300_TEX_SIZE(0))); |
||
495 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
||
496 | (R300_ALU_START(0) | |
||
497 | R300_ALU_SIZE(0) | |
||
498 | R300_TEX_START(0) | |
||
499 | R300_TEX_SIZE(0))); |
||
500 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
||
501 | (R300_ALU_START(0) | |
||
502 | R300_ALU_SIZE(0) | |
||
503 | R300_TEX_START(0) | |
||
504 | R300_TEX_SIZE(0))); |
||
505 | } else { |
||
506 | BEGIN_ACCEL(6); |
||
507 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
||
508 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
||
509 | } |
||
510 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
||
511 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
||
512 | R300_OUT_FMT_C0_SEL_BLUE | |
||
513 | R300_OUT_FMT_C1_SEL_GREEN | |
||
514 | R300_OUT_FMT_C2_SEL_RED | |
||
515 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
516 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
||
517 | R300_OUT_FMT_C0_SEL_BLUE | |
||
518 | R300_OUT_FMT_C1_SEL_GREEN | |
||
519 | R300_OUT_FMT_C2_SEL_RED | |
||
520 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
521 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
||
522 | R300_OUT_FMT_C0_SEL_BLUE | |
||
523 | R300_OUT_FMT_C1_SEL_GREEN | |
||
524 | R300_OUT_FMT_C2_SEL_RED | |
||
525 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
526 | FINISH_ACCEL(); |
||
527 | |||
528 | |||
529 | |||
530 | |||
531 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
||
532 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
||
533 | FINISH_ACCEL(); |
||
534 | |||
535 | BEGIN_ACCEL(13); |
||
536 | |||
537 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
||
538 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
||
539 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
||
540 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
||
541 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
||
542 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
||
543 | |||
544 | OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
||
545 | |||
546 | R300_GREEN_MASK_EN | |
||
547 | R300_RED_MASK_EN | |
||
548 | R300_ALPHA_MASK_EN)); |
||
549 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
550 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
||
551 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
||
552 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
553 | FINISH_ACCEL(); |
||
554 | |||
555 | BEGIN_ACCEL(7); |
||
556 | |||
557 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
||
558 | (0 << R300_SCISSOR_Y_SHIFT))); |
||
559 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
||
560 | (8191 << R300_SCISSOR_Y_SHIFT))); |
||
561 | |||
562 | if (IS_R300_3D) { |
||
563 | |||
564 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
||
565 | (1088 << R300_CLIP_Y_SHIFT))); |
||
566 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
||
567 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
||
568 | } else { |
||
569 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
||
570 | (0 << R300_CLIP_Y_SHIFT))); |
||
571 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
||
572 | (4080 << R300_CLIP_Y_SHIFT))); |
||
573 | } |
||
574 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
575 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
||
576 | FINISH_ACCEL(); |
||
577 | } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || |
||
578 | (info->ChipFamily == CHIP_FAMILY_RV280) || |
||
579 | (info->ChipFamily == CHIP_FAMILY_RS300) || |
||
580 | (info->ChipFamily == CHIP_FAMILY_R200)) { |
||
581 | |||
582 | BEGIN_ACCEL(7); |
||
583 | |||
584 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
585 | } else { |
||
586 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
||
587 | } |
||
588 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
||
589 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
||
590 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
||
591 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
||
592 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
||
593 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
||
594 | R200_VAP_VF_MAX_VTX_NUM); |
||
595 | FINISH_ACCEL(); |
||
596 | |||
597 | BEGIN_ACCEL(5); |
||
598 | |||
599 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
600 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
601 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
602 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
603 | RADEON_BFACE_SOLID | |
||
604 | RADEON_FFACE_SOLID | |
||
605 | RADEON_VTX_PIX_CENTER_OGL | |
||
606 | RADEON_ROUND_MODE_ROUND | |
||
607 | RADEON_ROUND_PREC_4TH_PIX)); |
||
608 | FINISH_ACCEL(); |
||
609 | } else { |
||
610 | BEGIN_ACCEL(2); |
||
611 | if ((info->ChipFamily == CHIP_FAMILY_RADEON) || |
||
612 | (info->ChipFamily == CHIP_FAMILY_RV200)) |
||
613 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
||
614 | else |
||
615 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
616 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
||
617 | RADEON_VTX_ST0_NONPARAMETRIC | |
||
954 | serge | 618 | RADEON_VTX_ST1_NONPARAMETRIC | |
619 | RADEON_TEX1_W_ROUTING_USE_W0); |
||
620 | FINISH_ACCEL(); |
||
621 | |||
885 | serge | 622 | BEGIN_ACCEL(5); |
623 | |||
624 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
625 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
626 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
627 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
628 | RADEON_BFACE_SOLID | |
||
629 | RADEON_FFACE_SOLID | |
||
630 | RADEON_VTX_PIX_CENTER_OGL | |
||
631 | RADEON_ROUND_MODE_ROUND | |
||
632 | RADEON_ROUND_PREC_4TH_PIX)); |
||
633 | FINISH_ACCEL(); |
||
634 | } |
||
635 | |||
636 | safe_sti(ifl); |
||
637 | |||
638 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
||
639 |