Rev 879 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 808 | serge | 1 | |
| 2 | |||
| 881 | serge | 3 | rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR]; |
| 808 | serge | 4 | rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR], |
| 881 | serge | 5 | rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE); |
| 6 | if( rhdPtr->MMIOBase==0) |
||
| 7 | return 0; |
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| 8 | |||
| 9 | DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize)); |
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| 808 | serge | 10 | |
| 881 | serge | 11 | } |
| 12 | |||
| 808 | serge | 13 | /* Read MC register */ |
| 14 | |||
| 881 | serge | 15 | { |
| 16 | u32_t data; |
||
| 17 | |||
| 18 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 19 | |||
| 20 | OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
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| 21 | data = INREG(RS690_MC_DATA); |
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| 22 | } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
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| 23 | OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
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| 24 | data = INREG(RS600_MC_DATA); |
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| 25 | } else if (IS_AVIVO_VARIANT) { |
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| 26 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
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| 27 | (void)INREG(AVIVO_MC_INDEX); |
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| 28 | data = INREG(AVIVO_MC_DATA); |
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| 29 | |||
| 30 | OUTREG(AVIVO_MC_INDEX, 0); |
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| 31 | |||
| 32 | } else { |
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| 33 | OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
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| 34 | (void)INREG(R300_MC_IND_INDEX); |
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| 35 | data = INREG(R300_MC_IND_DATA); |
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| 36 | |||
| 37 | OUTREG(R300_MC_IND_INDEX, 0); |
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| 38 | |||
| 39 | } |
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| 40 | |||
| 41 | return data; |
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| 42 | |||
| 43 | |||
| 44 | |||
| 45 | |||
| 46 | |||
| 47 | |||
| 48 | static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask, |
||
| 49 | |||
| 50 | { |
||
| 51 | |||
| 52 | if (info->ChipFamily >= CHIP_FAMILY_RV770) { |
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| 53 | |||
| 54 | *fb_loc = INREG(R700_MC_VM_FB_LOCATION); |
||
| 55 | if (mask & LOC_AGP) { |
||
| 56 | *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
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| 57 | *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
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| 58 | } |
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| 59 | } else if (info->ChipFamily >= CHIP_FAMILY_R600) { |
||
| 60 | if (mask & LOC_FB) |
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| 61 | *fb_loc = INREG(R600_MC_VM_FB_LOCATION); |
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| 62 | if (mask & LOC_AGP) { |
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| 63 | *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
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| 64 | *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
||
| 65 | } |
||
| 66 | } else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
||
| 67 | if (mask & LOC_FB) |
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| 68 | *fb_loc = INMC(info, RV515_MC_FB_LOCATION); |
||
| 69 | if (mask & LOC_AGP) { |
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| 70 | *agp_loc = INMC(info, RV515_MC_AGP_LOCATION); |
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| 71 | *agp_loc_hi = 0; |
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| 72 | } |
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| 73 | } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
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| 74 | if (mask & LOC_FB) |
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| 75 | *fb_loc = INMC(info, RS600_MC_FB_LOCATION); |
||
| 76 | if (mask & LOC_AGP) { |
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| 77 | *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); |
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| 78 | *agp_loc_hi = 0; |
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| 79 | } |
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| 80 | } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
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| 81 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
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| 82 | if (mask & LOC_FB) |
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| 83 | *fb_loc = INMC(info, RS690_MC_FB_LOCATION); |
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| 84 | if (mask & LOC_AGP) { |
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| 85 | *agp_loc = INMC(info, RS690_MC_AGP_LOCATION); |
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| 86 | *agp_loc_hi = 0; |
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| 87 | } |
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| 88 | } else if (info->ChipFamily >= CHIP_FAMILY_R520) { |
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| 89 | if (mask & LOC_FB) |
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| 90 | *fb_loc = INMC(info, R520_MC_FB_LOCATION); |
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| 91 | if (mask & LOC_AGP) { |
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| 92 | *agp_loc = INMC(info, R520_MC_AGP_LOCATION); |
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| 93 | *agp_loc_hi = 0; |
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| 94 | } |
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| 95 | } else { |
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| 96 | if (mask & LOC_FB) |
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| 97 | *fb_loc = INREG(RADEON_MC_FB_LOCATION); |
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| 98 | if (mask & LOC_AGP) |
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| 99 | *agp_loc = INREG(RADEON_MC_AGP_LOCATION); |
||
| 100 | } |
||
| 101 | } |
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| 102 | |||
| 103 | static void RADEONInitMemoryMap(RHDPtr info) |
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| 104 | |||
| 105 | u32_t mem_size; |
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| 106 | u32_t aper_size; |
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| 107 | |||
| 108 | radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
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| 109 | |||
| 110 | |||
| 111 | /* We shouldn't use info->videoRam here which might have been clipped |
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| 112 | |||
| 113 | */ |
||
| 114 | if (info->ChipFamily >= CHIP_FAMILY_R600){ |
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| 115 | mem_size = INREG(R600_CONFIG_MEMSIZE); |
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| 116 | aper_size = INREG(R600_CONFIG_APER_SIZE); |
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| 117 | } |
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| 118 | else { |
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| 119 | mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
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| 120 | aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
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| 121 | } |
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| 122 | |||
| 123 | if (mem_size == 0) |
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| 124 | |||
| 125 | |||
| 126 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
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| 127 | |||
| 128 | if (aper_size > mem_size) |
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| 129 | mem_size = aper_size; |
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| 130 | |||
| 131 | |||
| 132 | |||
| 133 | |||
| 134 | (info->ChipFamily != CHIP_FAMILY_RS740)) { |
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| 135 | if (info->IsIGP) |
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| 136 | info->mc_fb_location = INREG(RADEON_NB_TOM); |
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| 137 | else |
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| 138 | { |
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| 139 | u32_t aper0_base; |
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| 140 | |||
| 141 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
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| 142 | |||
| 143 | } |
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| 144 | else { |
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| 145 | aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
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| 146 | } |
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| 147 | |||
| 148 | /* Recent chips have an "issue" with the memory controller, the |
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| 149 | |||
| 150 | * too bad if we walk over the top of system memory, we don't |
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| 151 | * use DMA without a remapped anyway. |
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| 152 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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| 153 | */ |
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| 154 | if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
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| 155 | info->ChipFamily == CHIP_FAMILY_R300 || |
||
| 156 | info->ChipFamily == CHIP_FAMILY_R350 || |
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| 157 | info->ChipFamily == CHIP_FAMILY_RV350 || |
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| 158 | info->ChipFamily == CHIP_FAMILY_RV380 || |
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| 159 | info->ChipFamily == CHIP_FAMILY_R420 || |
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| 160 | info->ChipFamily == CHIP_FAMILY_RV410) |
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| 161 | aper0_base &= ~(mem_size - 1); |
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| 162 | |||
| 163 | if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
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| 164 | |||
| 165 | (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
||
| 166 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
||
| 167 | } |
||
| 168 | else { |
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| 169 | info->mc_fb_location = (aper0_base >> 16) | |
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| 170 | ((aper0_base + mem_size - 1) & 0xffff0000U); |
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| 171 | } |
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| 172 | } |
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| 173 | } |
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| 174 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
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| 175 | info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
||
| 176 | } |
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| 177 | else { |
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| 178 | info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
||
| 179 | } |
||
| 180 | /* Just disable the damn AGP apertures for now, it may be |
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| 181 | * re-enabled later by the DRM |
||
| 182 | */ |
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| 183 | |||
| 184 | if (IS_AVIVO_VARIANT) { |
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| 185 | |||
| 186 | OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
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| 187 | } |
||
| 188 | else { |
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| 189 | OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
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| 190 | } |
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| 191 | info->mc_agp_location = 0x003f0000; |
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| 192 | } |
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| 193 | else |
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| 194 | info->mc_agp_location = 0xffffffc0; |
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| 195 | |||
| 196 | dbgprintf("RADEONInitMemoryMap() : \n"); |
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| 197 | |||
| 198 | dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
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| 199 | dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
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| 200 | } |
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| 201 | |||
| 202 | static void RADEONGetVRamType(RHDPtr info) |
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| 203 | |||
| 204 | u32_t tmp; |
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| 205 | |||
| 206 | if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) |
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| 207 | |||
| 208 | else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
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| 209 | info->IsDDR = TRUE; |
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| 210 | else |
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| 211 | info->IsDDR = FALSE; |
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| 212 | |||
| 213 | if ( (info->ChipFamily >= CHIP_FAMILY_R600) && |
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| 214 | |||
| 215 | { |
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| 216 | int chansize; |
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| 217 | /* r6xx */ |
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| 218 | tmp = INREG(R600_RAMCFG); |
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| 219 | if (tmp & R600_CHANSIZE_OVERRIDE) |
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| 220 | chansize = 16; |
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| 221 | else if (tmp & R600_CHANSIZE) |
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| 222 | chansize = 64; |
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| 223 | else |
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| 224 | chansize = 32; |
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| 225 | if (info->ChipFamily == CHIP_FAMILY_R600) |
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| 226 | info->RamWidth = 8 * chansize; |
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| 227 | else if (info->ChipFamily == CHIP_FAMILY_RV670) |
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| 228 | info->RamWidth = 4 * chansize; |
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| 229 | else if ((info->ChipFamily == CHIP_FAMILY_RV610) || |
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| 230 | (info->ChipFamily == CHIP_FAMILY_RV620)) |
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| 231 | info->RamWidth = chansize; |
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| 232 | else if ((info->ChipFamily == CHIP_FAMILY_RV630) || |
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| 233 | (info->ChipFamily == CHIP_FAMILY_RV635)) |
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| 234 | info->RamWidth = 2 * chansize; |
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| 235 | } |
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| 236 | else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
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| 237 | /* rv515/rv550 */ |
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| 238 | tmp = INMC(info, RV515_MC_CNTL); |
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| 239 | tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
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| 240 | switch (tmp) { |
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| 241 | case 0: info->RamWidth = 64; break; |
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| 242 | case 1: info->RamWidth = 128; break; |
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| 243 | default: info->RamWidth = 128; break; |
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| 244 | } |
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| 245 | } |
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| 246 | else if ((info->ChipFamily >= CHIP_FAMILY_R520) && |
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| 247 | (info->ChipFamily <= CHIP_FAMILY_RV570)){ |
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| 248 | /* r520/rv530/rv560/rv570/r580 */ |
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| 249 | tmp = INMC(info, R520_MC_CNTL0); |
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| 250 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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| 251 | case 0: info->RamWidth = 32; break; |
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| 252 | case 1: info->RamWidth = 64; break; |
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| 253 | case 2: info->RamWidth = 128; break; |
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| 254 | case 3: info->RamWidth = 256; break; |
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| 255 | default: info->RamWidth = 64; break; |
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| 256 | } |
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| 257 | if (tmp & R520_MC_CHANNEL_SIZE) { |
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| 258 | info->RamWidth *= 2; |
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| 259 | } |
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| 260 | } |
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| 261 | else if ((info->ChipFamily >= CHIP_FAMILY_R300) && |
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| 262 | (info->ChipFamily <= CHIP_FAMILY_RV410)) { |
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| 263 | /* r3xx, r4xx */ |
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| 264 | tmp = INREG(RADEON_MEM_CNTL); |
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| 265 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
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| 266 | switch (tmp) { |
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| 267 | case 0: info->RamWidth = 64; break; |
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| 268 | case 1: info->RamWidth = 128; break; |
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| 269 | case 2: info->RamWidth = 256; break; |
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| 270 | default: info->RamWidth = 128; break; |
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| 271 | } |
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| 272 | } |
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| 273 | else if ((info->ChipFamily == CHIP_FAMILY_RV100) || |
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| 274 | (info->ChipFamily == CHIP_FAMILY_RS100) || |
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| 275 | (info->ChipFamily == CHIP_FAMILY_RS200)){ |
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| 276 | tmp = INREG(RADEON_MEM_CNTL); |
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| 277 | if (tmp & RV100_HALF_MODE) |
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| 278 | info->RamWidth = 32; |
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| 279 | else |
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| 280 | info->RamWidth = 64; |
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| 281 | |||
| 282 | /// if (!info->HasCRTC2) { |
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| 283 | |||
| 284 | /// info->IsDDR = TRUE; |
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| 285 | /// } |
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| 286 | } |
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| 287 | else if (info->ChipFamily <= CHIP_FAMILY_RV280) { |
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| 288 | tmp = INREG(RADEON_MEM_CNTL); |
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| 289 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) |
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| 290 | info->RamWidth = 128; |
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| 291 | else |
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| 292 | info->RamWidth = 64; |
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| 293 | } else { |
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| 294 | /* newer IGPs */ |
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| 295 | info->RamWidth = 128; |
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| 296 | } |
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| 297 | |||
| 298 | /* This may not be correct, as some cards can have half of channel disabled |
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| 299 | |||
| 300 | */ |
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| 301 | } |
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| 302 | |||
| 303 | /* |
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| 304 | |||
| 305 | * accessible to the CPU can vary. This function is our best shot at figuring |
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| 306 | * it out. Returns a value in KB. |
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| 307 | */ |
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| 308 | static u32_t RADEONGetAccessibleVRAM(RHDPtr info) |
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| 309 | { |
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| 310 | u32_t aper_size; |
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| 311 | unsigned char byte; |
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| 312 | |||
| 313 | if (info->ChipFamily >= CHIP_FAMILY_R600) |
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| 314 | |||
| 315 | else |
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| 316 | aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; |
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| 317 | |||
| 318 | |||
| 319 | |||
| 320 | |||
| 321 | */ |
||
| 322 | if (info->ChipFamily == CHIP_FAMILY_RV280 || |
||
| 323 | info->ChipFamily == CHIP_FAMILY_RV350 || |
||
| 324 | info->ChipFamily == CHIP_FAMILY_RV380 || |
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| 325 | info->ChipFamily == CHIP_FAMILY_R420 || |
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| 326 | info->ChipFamily == CHIP_FAMILY_RV410 || |
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| 327 | IS_AVIVO_VARIANT) { |
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| 328 | MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
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| 329 | ~RADEON_HDP_APER_CNTL); |
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| 330 | dbgprintf("Generation 2 PCI interface, using max accessible memory\n"); |
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| 331 | return aper_size * 2; |
||
| 332 | } |
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| 333 | |||
| 334 | /* Older cards have all sorts of funny issues to deal with. First |
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| 335 | |||
| 336 | * header type... Limit those to one aperture size |
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| 337 | */ |
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| 338 | // PCI_READ_BYTE(info->PciInfo, &byte, 0xe); |
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| 339 | // if (byte & 0x80) { |
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| 340 | // xf86DrvMsg(pScrn->scrnIndex, X_INFO, |
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| 341 | // "Generation 1 PCI interface in multifunction mode" |
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| 342 | // ", accessible memory limited to one aperture\n"); |
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| 343 | // return aper_size; |
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| 344 | // } |
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| 345 | |||
| 346 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
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| 347 | |||
| 348 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
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| 349 | */ |
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| 350 | // if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
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| 351 | // return aper_size * 2; |
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| 352 | |||
| 353 | return aper_size; |
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| 354 | |||
| 355 | |||
| 356 | |||
| 357 | |||
| 358 | |||
| 359 | u32_t accessible, bar_size; |
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| 360 | |||
| 361 | if ((!IS_AVIVO_VARIANT) && info->IsIGP) |
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| 362 | |||
| 363 | u32_t tom = INREG(RADEON_NB_TOM); |
||
| 364 | |||
| 365 | info->videoRam = (((tom >> 16) - |
||
| 366 | |||
| 367 | |||
| 368 | OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024); |
||
| 369 | |||
| 370 | else |
||
| 371 | { |
||
| 372 | if (info->ChipFamily >= CHIP_FAMILY_R600) |
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| 373 | info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; |
||
| 374 | else |
||
| 375 | { |
||
| 376 | /* Read VRAM size from card */ |
||
| 377 | info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; |
||
| 378 | |||
| 379 | /* Some production boards of m6 will return 0 if it's 8 MB */ |
||
| 380 | |||
| 381 | { |
||
| 382 | info->videoRam = 8192; |
||
| 383 | OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); |
||
| 384 | } |
||
| 385 | } |
||
| 386 | } |
||
| 387 | |||
| 388 | RADEONGetVRamType(info); |
||
| 389 | |||
| 390 | /* Get accessible memory */ |
||
| 391 | |||
| 392 | |||
| 393 | /* Crop it to the size of the PCI BAR */ |
||
| 394 | |||
| 395 | |||
| 396 | bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10); |
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| 397 | |||
| 398 | if (bar_size == 0) |
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| 399 | |||
| 400 | if (accessible > bar_size) |
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| 401 | accessible = bar_size; |
||
| 402 | |||
| 403 | dbgprintf("Detected total video RAM=%dK width=%dbit," |
||
| 404 | |||
| 405 | info->videoRam, info->RamWidth, |
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| 406 | (unsigned)accessible, (unsigned)bar_size); |
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| 407 | |||
| 408 | if (info->videoRam > accessible) |
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| 409 | |||
| 410 | |||
| 411 | if (!IS_AVIVO_VARIANT) |
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| 412 | |||
| 413 | info->BusCntl = INREG(RADEON_BUS_CNTL); |
||
| 414 | |||
| 415 | info->videoRam &= ~1023; |
||
| 416 | |||
| 417 | |||
| 418 | /* if the card is PCI Express reserve the last 32k for the gart table */ |
||
| 419 | |||
| 420 | // if (info->cardType == CARD_PCIE ) |
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| 421 | |||
| 422 | // info->FbSecureSize = RADEONDRIGetPciAperTableSize(info); |
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| 423 | // else |
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| 424 | // info->FbSecureSize = 0; |
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| 425 | |||
| 426 | return TRUE; |
||
| 427 | |||
| 428 | |||
| 429 | /* |
||
| 430 | |||
| 431 | #define RADEON_NB_TOM 0x15c |
||
| 432 | |||
| 808 | serge | 433 | static size_t rhdGetVideoRamSize(RHDPtr rhdPtr) |
| 434 | |||
| 877 | serge | 435 | size_t RamSize, BARSize; |
| 808 | serge | 436 | |
| 877 | serge | 437 | if (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) |
| 808 | serge | 438 | |
| 881 | serge | 439 | else |
| 808 | serge | 440 | if (rhdPtr->IsIGP) |
| 441 | { |
||
| 442 | u32_t tom = _RHDRegRead(rhdPtr, RADEON_NB_TOM); |
||
| 443 | RamSize = (((tom >> 16) - (tom & 0xffff) + 1) << 6); |
||
| 877 | serge | 444 | _RHDRegWrite(rhdPtr,R5XX_CONFIG_MEMSIZE, RamSize<<10); |
| 808 | serge | 445 | } |
| 446 | else |
||
| 447 | { |
||
| 448 | if (rhdPtr->ChipFamily < CHIP_FAMILY_R600) |
||
| 449 | { |
||
| 881 | serge | 450 | RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE)) >> 10; |
| 808 | serge | 451 | if(RamSize==0) RamSize=8192; |
| 452 | } |
||
| 453 | else |
||
| 454 | RamSize = (_RHDRegRead(rhdPtr, R6XX_CONFIG_MEMSIZE)) >> 10; |
||
| 455 | }; |
||
| 456 | |||
| 457 | BARSize = 1 << (rhdPtr->memsize[RHD_FB_BAR] - 10); |
||
| 458 | |||
| 459 | BARSize = 0x20000; |
||
| 460 | |||
| 461 | if (RamSize > BARSize) { |
||
| 462 | |||
| 463 | " exceeds the PCI BAR aperture.\n")); |
||
| 464 | DBG(dbgprintf("Using only %dkB of the total " |
||
| 465 | "%dkB.\n", (int) BARSize, (int) RamSize)); |
||
| 466 | return BARSize; |
||
| 467 | } |
||
| 468 | else return RamSize; |
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| 469 | } |
||
| 470 | */ |
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| 471 | |||
| 881 | serge | 472 | #if 0 |
| 808 | serge | 473 | |
| 881 | serge | 474 | rhdMapFB(RHDPtr rhdPtr) |
| 808 | serge | 475 | { |
| 476 | rhdPtr->FbMapSize = 1 << rhdPtr->memsize[RHD_FB_BAR]; |
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| 477 | rhdPtr->PhisBase = rhdPtr->memBase[RHD_FB_BAR]; |
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| 478 | |||
| 479 | // rhdPtr->FbBase = MapIoMem(rhdPtr->PhisBase, rhdPtr->FbMapSize,PG_SW+PG_NOCACHE); |
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| 480 | |||
| 817 | serge | 481 | // if (!rhdPtr->FbBase) |
| 808 | serge | 482 | |
| 817 | serge | 483 | |
| 484 | /* These devices have an internal address reference, which some other |
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| 808 | serge | 485 | |
| 486 | * address in the BAR */ |
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| 487 | if (rhdPtr->ChipFamily < CHIP_FAMILY_R600) |
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| 488 | rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, HDP_FB_LOCATION)<< 16; |
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| 881 | serge | 489 | else |
| 808 | serge | 490 | rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE); |
| 491 | |||
| 492 | // rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, 0x6110); |
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| 493 | |||
| 494 | |||
| 495 | if (rhdPtr->FbIntAddress != rhdPtr->PhisBase) |
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| 496 | |||
| 497 | "0x%08X while card Internal Address is 0x%08X\n", |
||
| 498 | (unsigned int) rhdPtr->PhisBase,rhdPtr->FbIntAddress); |
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| 499 | // dbgprintf("Mapped FB at %p (size 0x%08X)\n",rhdPtr->FbBase, rhdPtr->FbMapSize); |
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| 500 | return TRUE; |
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| 817 | serge | 501 | } |
| 808 | serge | 502 | #endif |
| 503 | |||
| 881 | serge | 504 | static Bool RADEONPreInitChipType(RHDPtr rhdPtr) |
| 808 | serge | 505 | |
| 881 | serge | 506 | u32_t cmd_stat; |
| 507 | |||
| 508 | rhdPtr->ChipErrata = 0; |
||
| 509 | |||
| 510 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
||
| 511 | |||
| 512 | == RADEON_CFG_ATI_REV_A11)) |
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| 513 | rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
||
| 514 | |||
| 515 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
||
| 516 | |||
| 517 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
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| 518 | |||
| 519 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
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| 520 | |||
| 521 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
||
| 522 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
||
| 523 | |||
| 524 | rhdPtr->cardType = CARD_PCI; |
||
| 525 | |||
| 526 | |||
| 527 | |||
| 528 | |||
| 529 | if (cmd_stat & RADEON_CAP_LIST) |
||
| 530 | |||
| 531 | u32_t cap_ptr, cap_id; |
||
| 532 | |||
| 533 | cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
||
| 534 | |||
| 535 | |||
| 536 | while(cap_ptr != RADEON_CAP_ID_NULL) |
||
| 537 | |||
| 538 | cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
||
| 539 | if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
||
| 540 | rhdPtr->cardType = CARD_AGP; |
||
| 541 | break; |
||
| 542 | } |
||
| 543 | if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
||
| 544 | rhdPtr->cardType = CARD_PCIE; |
||
| 545 | break; |
||
| 546 | } |
||
| 547 | cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
||
| 548 | } |
||
| 549 | } |
||
| 550 | |||
| 551 | dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
||
| 552 | |||
| 553 | |||
| 554 | /* treat PCIE IGP cards as PCI */ |
||
| 555 | |||
| 556 | rhdPtr->cardType = CARD_PCI; |
||
| 557 | |||
| 558 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
||
| 559 | |||
| 560 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
||
| 561 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
||
| 562 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
||
| 563 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) || |
||
| 564 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 565 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS740)) |
||
| 566 | rhdPtr->has_tcl = FALSE; |
||
| 567 | else { |
||
| 568 | rhdPtr->has_tcl = TRUE; |
||
| 569 | } |
||
| 570 | |||
| 571 | rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
||
| 572 | |||
| 573 | return TRUE; |
||
| 574 | |||
| 575 | |||
| 576 | Bool RHDPreInit() |
||
| 577 | |||
| 808 | serge | 578 | /* We need access to IO space already */ |
| 579 | if ( !rhdMapMMIO(&rhd) ) { |
||
| 580 | dbgprintf("Failed to map MMIO.\n"); |
||
| 881 | serge | 581 | return FALSE; |
| 582 | }; |
||
| 583 | |||
| 584 | |||
| 808 | serge | 585 | |
| 586 | |||
| 881 | serge | 587 | |
| 588 | if (!RADEONPreInitVRAM(&rhd)) |
||
| 808 | serge | 589 | |
| 881 | serge | 590 | |
| 591 | RADEONInitMemoryMap(&rhd); |
||
| 808 | serge | 592 | |
| 881 | serge | 593 | if (!rhd.videoRam) |
| 594 | |||
| 595 | dbgprintf("No Video RAM detected.\n"); |
||
| 596 | goto error1; |
||
| 597 | } |
||
| 598 | dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
||
| 599 | |||
| 600 | rhd.FbFreeStart = 0; |
||
| 601 | |||
| 602 | |||
| 603 | // if( !rhdMapFB(&rhd)) |
||
| 604 | |||
| 605 | |||
| 606 | // rhd.FbScanoutStart = 0; |
||
| 607 | |||
| 608 | |||
| 609 | rhd.FbFreeStart = 10*1024*1024; |
||
| 610 | |||
| 817 | serge | 611 | |
| 881 | serge | 612 | rhdInitHeap(&rhd); |
| 808 | serge | 613 | |
| 614 | |||
| 615 | error1: |
||
| 616 | |||
| 617 | }; |
||
| 618 | > |
||
| 619 | > |
||
| 620 |