WebSVN – Kolibri OS – Blame – /programs/system/drivers/ati2d/init.c

Rev	Author	Line No.	Line
808	serge	1
		2
881	serge	3	rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
808	serge	4	rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
881	serge	5	rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
		6	if( rhdPtr->MMIOBase==0)
		7	return 0;
		8
		9	DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
808	serge	10
881	serge	11	}
		12
808	serge	13	/* Read MC register */
		14
881	serge	15	{
		16	u32_t data;
		17
		18	if ((info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		19
		20	OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
		21	data = INREG(RS690_MC_DATA);
1002	serge	22	} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
		23	OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
881	serge	24	data = INREG(RS600_MC_DATA);
1002	serge	25	} else if (IS_AVIVO_VARIANT) {
		26	OUTREG(AVIVO_MC_INDEX, (addr & 0xff) \| 0x7f0000);
881	serge	27	(void)INREG(AVIVO_MC_INDEX);
1002	serge	28	data = INREG(AVIVO_MC_DATA);
		29
		30	OUTREG(AVIVO_MC_INDEX, 0);
881	serge	31
1002	serge	32	} else {
		33	OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
881	serge	34	(void)INREG(R300_MC_IND_INDEX);
1002	serge	35	data = INREG(R300_MC_IND_DATA);
		36
		37	OUTREG(R300_MC_IND_INDEX, 0);
881	serge	38
1002	serge	39	}
		40
881	serge	41	return data;
		42
		43
		44	/* Write MC information */
		45
883	serge	46	{
		47	if ((info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		48	(info->ChipFamily == CHIP_FAMILY_RS740)) {
1002	serge	49	OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) \| RS690_MC_INDEX_WR_EN));
		50	OUTREG(RS690_MC_DATA, data);
883	serge	51	OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
1002	serge	52	}
883	serge	53	else if (info->ChipFamily == CHIP_FAMILY_RS600) {
1002	serge	54	OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) \| RS600_MC_INDEX_WR_EN));
		55	OUTREG(RS600_MC_DATA, data);
883	serge	56	OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK);
		57	}
		58	else if (IS_AVIVO_VARIANT) {
1002	serge	59	OUTREG(AVIVO_MC_INDEX, (addr & 0xff) \| 0xff0000);
		60	(void)INREG(AVIVO_MC_INDEX);
883	serge	61	OUTREG(AVIVO_MC_DATA, data);
		62	OUTREG(AVIVO_MC_INDEX, 0);
		63	(void)INREG(AVIVO_MC_INDEX);
		64	}
		65	else {
1002	serge	66	OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) \| R300_MC_IND_WR_EN));
		67	(void)INREG(R300_MC_IND_INDEX);
883	serge	68	OUTREG(R300_MC_IND_DATA, data);
		69	OUTREG(R300_MC_IND_INDEX, 0);
		70	(void)INREG(R300_MC_IND_INDEX);
		71	}
		72	}
1002	serge	73
883	serge	74	static Bool avivo_get_mc_idle(RHDPtr info)
881	serge	75
883	serge	76
		77	if (info->ChipFamily >= CHIP_FAMILY_R600) {
		78
1002	serge	79	return TRUE;
883	serge	80	}
		81	else if (info->ChipFamily == CHIP_FAMILY_RV515) {
1002	serge	82	if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
		83	return TRUE;
883	serge	84	else
1002	serge	85	return FALSE;
883	serge	86	}
1002	serge	87	else if (info->ChipFamily == CHIP_FAMILY_RS600)
		88	{
		89	if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
		90	return TRUE;
883	serge	91	else
1002	serge	92	return FALSE;
883	serge	93	}
1002	serge	94	else if ((info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		95	(info->ChipFamily == CHIP_FAMILY_RS740)) {
		96	if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
		97	return TRUE;
883	serge	98	else
1002	serge	99	return FALSE;
883	serge	100	}
1002	serge	101	else {
883	serge	102	if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
		103	return TRUE;
1002	serge	104	else
		105	return FALSE;
		106	}
		107	}
883	serge	108
		109	#define LOC_FB 0x1
		110
881	serge	111
		112	static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
		113
		114	{
		115
		116	if (info->ChipFamily >= CHIP_FAMILY_RV770) {
		117
		118	*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
		119	if (mask & LOC_AGP) {
		120	*agp_loc = INREG(R600_MC_VM_AGP_BOT);
		121	*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
		122	}
		123	} else if (info->ChipFamily >= CHIP_FAMILY_R600) {
		124	if (mask & LOC_FB)
		125	*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
		126	if (mask & LOC_AGP) {
		127	*agp_loc = INREG(R600_MC_VM_AGP_BOT);
		128	*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
		129	}
		130	} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
		131	if (mask & LOC_FB)
		132	*fb_loc = INMC(info, RV515_MC_FB_LOCATION);
		133	if (mask & LOC_AGP) {
		134	*agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
		135	*agp_loc_hi = 0;
		136	}
		137	} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
		138	if (mask & LOC_FB)
		139	*fb_loc = INMC(info, RS600_MC_FB_LOCATION);
		140	if (mask & LOC_AGP) {
		141	*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
		142	*agp_loc_hi = 0;
		143	}
		144	} else if ((info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		145	(info->ChipFamily == CHIP_FAMILY_RS740)) {
		146	if (mask & LOC_FB)
		147	*fb_loc = INMC(info, RS690_MC_FB_LOCATION);
		148	if (mask & LOC_AGP) {
		149	*agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
		150	*agp_loc_hi = 0;
		151	}
		152	} else if (info->ChipFamily >= CHIP_FAMILY_R520) {
		153	if (mask & LOC_FB)
		154	*fb_loc = INMC(info, R520_MC_FB_LOCATION);
		155	if (mask & LOC_AGP) {
		156	*agp_loc = INMC(info, R520_MC_AGP_LOCATION);
		157	*agp_loc_hi = 0;
		158	}
		159	} else {
		160	if (mask & LOC_FB)
		161	*fb_loc = INREG(RADEON_MC_FB_LOCATION);
		162	if (mask & LOC_AGP)
		163	*agp_loc = INREG(RADEON_MC_AGP_LOCATION);
		164	}
		165	}
		166
		167	static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
		168
883	serge	169	{
		170
		171	if (info->ChipFamily >= CHIP_FAMILY_RV770) {
		172
		173	OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
		174	if (mask & LOC_AGP) {
		175	OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
		176	OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
		177	}
		178	}
		179	else if (info->ChipFamily >= CHIP_FAMILY_R600)
		180	{
		181	if (mask & LOC_FB)
		182	OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
		183	if (mask & LOC_AGP) {
		184	OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
		185	OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
		186	}
		187	}
		188	else if (info->ChipFamily == CHIP_FAMILY_RV515)
		189	{
		190	if (mask & LOC_FB)
		191	OUTMC(info, RV515_MC_FB_LOCATION, fb_loc);
		192	if (mask & LOC_AGP)
		193	OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc);
		194	(void)INMC(info, RV515_MC_AGP_LOCATION);
		195	}
		196	else if (info->ChipFamily == CHIP_FAMILY_RS600)
		197	{
		198	if (mask & LOC_FB)
		199	OUTMC(info, RS600_MC_FB_LOCATION, fb_loc);
		200	/* if (mask & LOC_AGP)
		201	OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/
		202	}
		203	else if ((info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		204	(info->ChipFamily == CHIP_FAMILY_RS740))
		205	{
		206	if (mask & LOC_FB)
		207	OUTMC(info, RS690_MC_FB_LOCATION, fb_loc);
		208	if (mask & LOC_AGP)
		209	OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc);
		210	}
		211	else if (info->ChipFamily >= CHIP_FAMILY_R520)
		212	{
		213	if (mask & LOC_FB)
		214	OUTMC(info, R520_MC_FB_LOCATION, fb_loc);
		215	if (mask & LOC_AGP)
		216	OUTMC(info, R520_MC_AGP_LOCATION, agp_loc);
		217	(void)INMC(info, R520_MC_FB_LOCATION);
		218	}
		219	else {
		220	if (mask & LOC_FB)
		221	OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
		222	if (mask & LOC_AGP)
		223	OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
		224	}
		225	}
		226
		227	#if !R300_PIO
		228
885	serge	229	static void RADEONUpdateMemMapRegisters(RHDPtr info)
883	serge	230
		231	u32_t timeout;
		232
		233	u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
		234
		235	radeon_read_mc_fb_agp_location(info, LOC_FB \| LOC_AGP, &mc_fb_loc,
		236
		237
		238	if (IS_AVIVO_VARIANT)
		239
		240
		241	if (mc_fb_loc != info->mc_fb_location \|\|
		242
		243	{
		244	u32_t d1crtc, d2crtc;
		245	u32_t tmp;
		246	// RADEONWaitForIdleMMIO(pScrn);
		247
		248	OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
		249
		250
		251	/* Stop display & memory access */
		252
		253	OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN);
		254
		255	d2crtc = INREG(AVIVO_D2CRTC_CONTROL);
		256
		257
		258	tmp = INREG(AVIVO_D2CRTC_CONTROL);
		259
		260	usleep(10000);
		261
		262	while (!(avivo_get_mc_idle(info)))
		263	{
		264	if (++timeout > 1000000)
		265	{
		266	dbgprintf("Timeout trying to update memory controller settings !\n");
		267	dbgprintf("You will probably crash now ... \n");
		268	/* Nothing we can do except maybe try to kill the server,
		269	* let's wait 2 seconds to leave the above message a chance
		270	* to maybe hit the disk and continue trying to setup despite
		271	* the MC being non-idle
		272	*/
		273	usleep(2000000);
		274	}
		275	usleep(10);
		276	}
		277
		278	radeon_write_mc_fb_agp_location(info, LOC_FB \| LOC_AGP,
		279
		280	info->mc_agp_location,
		281	info->mc_agp_location_hi);
		282
		283	if (info->ChipFamily < CHIP_FAMILY_R600) {
		284
		285	}
		286	else {
		287	OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
		288	}
		289
		290	OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc );
		291
		292	OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc );
		293
		294	tmp = INREG(AVIVO_D2CRTC_CONTROL);
		295
		296	/* Reset the engine and HDP */
		297
		298	}
		299	}
		300	else
		301	{
		302
		303	/* Write memory mapping registers only if their value change
		304
		305	* reprogrammed
		306	*/
		307	if ( mc_fb_loc != info->mc_fb_location \|\|
		308	mc_agp_loc != info->mc_agp_location)
		309	{
		310	u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
		311	u32_t old_mc_status, status_idle;
		312
		313	dbgprintf(" Map Changed ! Applying ...\n");
		314
		315	/* Make sure engine is idle. We assume the CCE is stopped
		316
		317	*/
		318	// RADEONWaitForIdleMMIO(info);
		319
		320	if (info->IsIGP)
		321
		322
		323	/* Capture MC_STATUS in case things go wrong ... */
		324
		325
		326	/* Stop display & memory access */
		327
		328	OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
		329	crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
		330	OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl \| RADEON_CRTC_DISPLAY_DIS);
		331	crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
		332	// RADEONWaitForVerticalSync(pScrn);
		333	OUTREG(RADEON_CRTC_GEN_CNTL,
		334	(crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN \| RADEON_CRTC_ICON_EN))
		335	\| RADEON_CRTC_DISP_REQ_EN_B \| RADEON_CRTC_EXT_DISP_EN);
		336
		337	if (info->HasCRTC2)
		338
		339	crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
		340	// RADEONWaitForVerticalSync2(pScrn);
		341	OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl
		342	& ~(RADEON_CRTC2_CUR_EN \| RADEON_CRTC2_ICON_EN))
		343	\| RADEON_CRTC2_DISP_REQ_EN_B);
		344	}
		345
		346	/* Make sure the chip settles down (paranoid !) */
		347
		348
		349	/* Wait for MC idle */
		350
		351	status_idle = R300_MC_IDLE;
		352	else
		353	status_idle = RADEON_MC_IDLE;
		354
		355	timeout = 0;
		356
		357	{
		358	if (++timeout > 1000000)
		359	{
		360	dbgprintf("Timeout trying to update memory controller settings !\n");
		361	dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
		362	INREG(RADEON_MC_STATUS), old_mc_status);
		363	dbgprintf("You will probably crash now ... \n");
		364	/* Nothing we can do except maybe try to kill the server,
		365	* let's wait 2 seconds to leave the above message a chance
		366	* to maybe hit the disk and continue trying to setup despite
		367	* the MC being non-idle
		368	*/
		369	usleep(20000);
		370	}
		371	usleep(10);
		372	}
		373
		374	/* Update maps, first clearing out AGP to make sure we don't get
		375
		376	*/
		377	OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
		378	OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location);
		379	radeon_write_mc_fb_agp_location(info, LOC_FB \| LOC_AGP, info->mc_fb_location,
		380	0xfffffffc, 0);
		381
		382	OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl );
		383
		384	OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl );
		385
		386
		387
		388
		389	info->mc_agp_location, 0);
		390	/* Make sure map fully reached the chip */
		391	(void)INREG(RADEON_MC_FB_LOCATION);
		392
		393	dbgprintf(" Map applied, resetting engine ...\n");
		394
		395	/* Reset the engine and HDP */
		396
		397
		398	/* Make sure we have sane offsets before re-enabling the CRTCs, disable
		399
		400	*/
		401
		402	OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
		403
		404	OUTREG(RADEON_CUR_OFFSET, 0);
		405	timeout = 0;
		406	while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
		407	{
		408	if (timeout++ > 1000000) {
		409	dbgprintf("Timeout waiting for CRTC offset to update !\n");
		410	break;
		411	}
		412	usleep(1000);
		413	}
		414	if (info->HasCRTC2)
		415	{
		416	OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
		417	OUTREG(RADEON_CRTC2_OFFSET, 0);
		418	OUTREG(RADEON_CUR2_OFFSET, 0);
		419	timeout = 0;
		420	while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET)
		421	{
		422	if (timeout++ > 1000000) {
		423	dbgprintf("Timeout waiting for CRTC2 offset to update !\n");
		424	break;
		425	}
		426	usleep(1000);
		427	}
		428	}
		429	}
		430
		431	dbgprintf("Updating display base addresses...\n");
		432
		433	OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
		434
		435	OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
		436	OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
		437	(void)INREG(RADEON_OV0_BASE_ADDR);
		438
		439	/* More paranoia delays, wait 100ms */
		440
		441
		442	dbgprintf("Memory map updated.\n");
		443
		444	};
		445
		446	#endif
		447
885	serge	448
883	serge	449
885	serge	450
881	serge	451	u32_t mem_size;
		452	u32_t aper_size;
1002	serge	453
		454	radeon_read_mc_fb_agp_location(info, LOC_FB \| LOC_AGP, &info->mc_fb_location,
881	serge	455
1002	serge	456
		457	dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
881	serge	458
1002	serge	459
		460
883	serge	461
		462
1002	serge	463	*/
		464	if (info->ChipFamily >= CHIP_FAMILY_R600){
		465	mem_size = INREG(R600_CONFIG_MEMSIZE);
		466	aper_size = INREG(R600_CONFIG_APER_SIZE);
881	serge	467	}
		468	else {
1002	serge	469	mem_size = INREG(RADEON_CONFIG_MEMSIZE);
		470	aper_size = INREG(RADEON_CONFIG_APER_SIZE);
881	serge	471	}
		472
1002	serge	473	if (mem_size == 0)
881	serge	474
1002	serge	475
881	serge	476	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
		477
1002	serge	478	if (aper_size > mem_size)
		479	mem_size = aper_size;
		480
881	serge	481
		482
		483
1002	serge	484	(info->ChipFamily != CHIP_FAMILY_RS740))
		485	{
		486	if (info->IsIGP)
		487	info->mc_fb_location = INREG(RADEON_NB_TOM);
881	serge	488	else
1002	serge	489	{
881	serge	490	u32_t aper0_base;
		491
1002	serge	492	if (info->ChipFamily >= CHIP_FAMILY_R600) {
881	serge	493
1002	serge	494	}
		495	else {
		496	aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
		497	}
		498	dbgprintf("aper0 base %x\n", aper0_base );
		499
		500	/* Recent chips have an "issue" with the memory controller, the
881	serge	501
1002	serge	502	* too bad if we walk over the top of system memory, we don't
		503	* use DMA without a remapped anyway.
		504	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		505	*/
		506	if ( info->ChipFamily == CHIP_FAMILY_RV280 \|\|
		507	info->ChipFamily == CHIP_FAMILY_R300 \|\|
		508	info->ChipFamily == CHIP_FAMILY_R350 \|\|
		509	info->ChipFamily == CHIP_FAMILY_RV350 \|\|
		510	info->ChipFamily == CHIP_FAMILY_RV380 \|\|
		511	info->ChipFamily == CHIP_FAMILY_R420 \|\|
		512	info->ChipFamily == CHIP_FAMILY_RV410)
		513	aper0_base &= ~(mem_size - 1);
		514
		515	if ( info->ChipFamily >= CHIP_FAMILY_R600) {
881	serge	516
1002	serge	517	(((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
		518	dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
		519	}
		520	else {
		521	info->mc_fb_location = (aper0_base >> 16) \|
		522	((aper0_base + mem_size - 1) & 0xffff0000U);
		523	dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
		524	}
		525	}
		526	}
881	serge	527	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1002	serge	528	info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
		529	}
881	serge	530	else {
1002	serge	531	info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
		532	}
881	serge	533	/* Just disable the damn AGP apertures for now, it may be
1002	serge	534	* re-enabled later by the DRM
		535	*/
		536
		537	// if (IS_AVIVO_VARIANT) {
881	serge	538
1002	serge	539	// OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
		540	// }
		541	// else {
		542	// OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
		543	// }
		544	// info->mc_agp_location = 0x003f0000;
		545	// }
		546	// else
		547	// info->mc_agp_location = 0xffffffc0;
		548
		549	dbgprintf("RADEONInitMemoryMap() : \n");
881	serge	550
1002	serge	551	dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
		552	dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location);
		553	dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation);
		554
		555	#if !R300_PIO
883	serge	556
885	serge	557	RADEONUpdateMemMapRegisters(info);
		558
1002	serge	559	#endif
885	serge	560
		561	}
		562
881	serge	563	static void RADEONGetVRamType(RHDPtr info)
		564
		565	u32_t tmp;
		566
		567	if (info->IsIGP \|\| (info->ChipFamily >= CHIP_FAMILY_R300))
		568
		569	else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		570	info->IsDDR = TRUE;
		571	else
		572	info->IsDDR = FALSE;
		573
		574	if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
		575
		576	{
		577	int chansize;
		578	/* r6xx */
		579	tmp = INREG(R600_RAMCFG);
		580	if (tmp & R600_CHANSIZE_OVERRIDE)
		581	chansize = 16;
		582	else if (tmp & R600_CHANSIZE)
		583	chansize = 64;
		584	else
		585	chansize = 32;
		586	if (info->ChipFamily == CHIP_FAMILY_R600)
		587	info->RamWidth = 8 * chansize;
		588	else if (info->ChipFamily == CHIP_FAMILY_RV670)
		589	info->RamWidth = 4 * chansize;
		590	else if ((info->ChipFamily == CHIP_FAMILY_RV610) \|\|
		591	(info->ChipFamily == CHIP_FAMILY_RV620))
		592	info->RamWidth = chansize;
		593	else if ((info->ChipFamily == CHIP_FAMILY_RV630) \|\|
		594	(info->ChipFamily == CHIP_FAMILY_RV635))
		595	info->RamWidth = 2 * chansize;
		596	}
		597	else if (info->ChipFamily == CHIP_FAMILY_RV515) {
		598	/* rv515/rv550 */
		599	tmp = INMC(info, RV515_MC_CNTL);
		600	tmp &= RV515_MEM_NUM_CHANNELS_MASK;
		601	switch (tmp) {
		602	case 0: info->RamWidth = 64; break;
		603	case 1: info->RamWidth = 128; break;
		604	default: info->RamWidth = 128; break;
		605	}
		606	}
		607	else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
		608	(info->ChipFamily <= CHIP_FAMILY_RV570)){
		609	/* r520/rv530/rv560/rv570/r580 */
		610	tmp = INMC(info, R520_MC_CNTL0);
		611	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
		612	case 0: info->RamWidth = 32; break;
		613	case 1: info->RamWidth = 64; break;
		614	case 2: info->RamWidth = 128; break;
		615	case 3: info->RamWidth = 256; break;
		616	default: info->RamWidth = 64; break;
		617	}
		618	if (tmp & R520_MC_CHANNEL_SIZE) {
		619	info->RamWidth *= 2;
		620	}
		621	}
		622	else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
		623	(info->ChipFamily <= CHIP_FAMILY_RV410)) {
		624	/* r3xx, r4xx */
		625	tmp = INREG(RADEON_MEM_CNTL);
		626	tmp &= R300_MEM_NUM_CHANNELS_MASK;
		627	switch (tmp) {
		628	case 0: info->RamWidth = 64; break;
		629	case 1: info->RamWidth = 128; break;
		630	case 2: info->RamWidth = 256; break;
		631	default: info->RamWidth = 128; break;
		632	}
		633	}
		634	else if ((info->ChipFamily == CHIP_FAMILY_RV100) \|\|
		635	(info->ChipFamily == CHIP_FAMILY_RS100) \|\|
		636	(info->ChipFamily == CHIP_FAMILY_RS200)){
		637	tmp = INREG(RADEON_MEM_CNTL);
		638	if (tmp & RV100_HALF_MODE)
		639	info->RamWidth = 32;
		640	else
		641	info->RamWidth = 64;
		642
		643	if (!info->HasCRTC2) {
		644
883	serge	645	info->IsDDR = TRUE;
		646	}
		647	}
881	serge	648	else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
883	serge	649	tmp = INREG(RADEON_MEM_CNTL);
881	serge	650	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
		651	info->RamWidth = 128;
		652	else
		653	info->RamWidth = 64;
		654	} else {
		655	/* newer IGPs */
		656	info->RamWidth = 128;
		657	}
		658
		659	/* This may not be correct, as some cards can have half of channel disabled
		660
		661	*/
		662	}
		663
		664	/*
		665
		666	* accessible to the CPU can vary. This function is our best shot at figuring
		667	* it out. Returns a value in KB.
		668	*/
		669	static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
		670	{
		671	u32_t aper_size;
		672	unsigned char byte;
		673
		674	if (info->ChipFamily >= CHIP_FAMILY_R600)
		675
		676	else
		677	aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
		678
		679
		680
		681
		682	*/
		683	if (info->ChipFamily == CHIP_FAMILY_RV280 \|\|
		684	info->ChipFamily == CHIP_FAMILY_RV350 \|\|
		685	info->ChipFamily == CHIP_FAMILY_RV380 \|\|
		686	info->ChipFamily == CHIP_FAMILY_R420 \|\|
		687	info->ChipFamily == CHIP_FAMILY_RV410 \|\|
		688	IS_AVIVO_VARIANT) {
		689	MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		690	~RADEON_HDP_APER_CNTL);
		691	dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
		692	return aper_size * 2;
		693	}
		694
		695	/* Older cards have all sorts of funny issues to deal with. First
		696
		697	* header type... Limit those to one aperture size
		698	*/
		699	byte = pciReadByte(info->PciTag, 0xe);
		700	if (byte & 0x80) {
883	serge	701	dbgprintf("Generation 1 PCI interface in multifunction mode, "
		702	"accessible memory limited to one aperture\n");
		703	return aper_size;
		704	}
		705
		706	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
881	serge	707
		708	* we expect the BIOS to have done the right thing (might be too optimistic...)
		709	*/
		710	if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		711	return aper_size * 2;
883	serge	712
		713	return aper_size;
881	serge	714
		715
		716	int RADEONDRIGetPciAperTableSize(RHDPtr info)
		717
883	serge	718	int ret_size;
		719	int num_pages;
		720
		721	num_pages = (info->pciAperSize * 1024 * 1024) / 4096;
881	serge	722
883	serge	723	ret_size = num_pages * sizeof(unsigned int);
		724
		725	return ret_size;
		726
		727
		728	static Bool RADEONPreInitVRAM(RHDPtr info)
		729
881	serge	730	u32_t accessible, bar_size;
		731
		732	if ((!IS_AVIVO_VARIANT) && info->IsIGP)
		733
		734	u32_t tom = INREG(RADEON_NB_TOM);
		735
		736	info->videoRam = (((tom >> 16) -
		737
		738
		739	OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
		740
		741	else
		742	{
		743	if (info->ChipFamily >= CHIP_FAMILY_R600)
		744	info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
		745	else
		746	{
		747	/* Read VRAM size from card */
		748	info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
		749
		750	/* Some production boards of m6 will return 0 if it's 8 MB */
		751
		752	{
		753	info->videoRam = 8192;
		754	OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
		755	}
		756	}
		757	}
		758
		759	RADEONGetVRamType(info);
		760
		761	/* Get accessible memory */
		762
		763
		764	/* Crop it to the size of the PCI BAR */
		765
		766
		767	bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
		768
		769	if (bar_size == 0)
		770
		771	if (accessible > bar_size)
		772	accessible = bar_size;
		773
		774	dbgprintf("Detected total video RAM=%dK width=%dbit,"
		775
		776	info->videoRam, info->RamWidth,
		777	(unsigned)accessible, (unsigned)bar_size);
		778
		779	if (info->videoRam > accessible)
		780
		781
		782	if (!IS_AVIVO_VARIANT)
		783
		784	info->BusCntl = INREG(RADEON_BUS_CNTL);
		785
		786	info->videoRam &= ~1023;
		787
		788
		789	info->gartSize = RADEON_DEFAULT_GART_SIZE;
		790
883	serge	791	info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
		792
		793	info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
881	serge	794
883	serge	795	info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
881	serge	796
883	serge	797
		798
881	serge	799
		800
808	serge	801
883	serge	802	// if (info->cardType == CARD_PCIE )
808	serge	803
883	serge	804	// info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
		805	// else
		806	// info->FbSecureSize = 0;
		807
		808	return TRUE;
808	serge	809
883	serge	810
808	serge	811
		812
		813
881	serge	814	u32_t cmd_stat;
		815
1002	serge	816	rhdPtr->ChipErrata = 0;
881	serge	817
1002	serge	818	if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
881	serge	819
1002	serge	820	== RADEON_CFG_ATI_REV_A11))
		821	rhdPtr->ChipErrata \|= CHIP_ERRATA_R300_CG;
		822
881	serge	823	if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) \|\|
		824
1002	serge	825	rhdPtr->ChipErrata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		826
881	serge	827	if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) \|\|
		828
1002	serge	829	(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
		830	rhdPtr->ChipErrata \|= CHIP_ERRATA_PLL_DELAY;
		831
881	serge	832	rhdPtr->cardType = CARD_PCI;
		833
1002	serge	834
881	serge	835
		836
1002	serge	837	if (cmd_stat & RADEON_CAP_LIST)
881	serge	838
1002	serge	839	u32_t cap_ptr, cap_id;
		840
881	serge	841	cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
		842
		843
		844	while(cap_ptr != RADEON_CAP_ID_NULL)
		845
		846	cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
		847	if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
1002	serge	848	rhdPtr->cardType = CARD_AGP;
		849	break;
		850	}
		851	if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
		852	rhdPtr->cardType = CARD_PCIE;
		853	break;
		854	}
		855	cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
		856	}
		857	}
881	serge	858
1002	serge	859	dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
881	serge	860
1002	serge	861
		862	/* treat PCIE IGP cards as PCI */
881	serge	863
		864	rhdPtr->cardType = CARD_PCI;
1002	serge	865
		866	if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) \|\|
881	serge	867
1002	serge	868	(rhdPtr->ChipFamily == CHIP_FAMILY_RS300) \|\|
		869	(rhdPtr->ChipFamily == CHIP_FAMILY_RS400) \|\|
		870	(rhdPtr->ChipFamily == CHIP_FAMILY_RS480) \|\|
		871	(rhdPtr->ChipFamily == CHIP_FAMILY_RS600) \|\|
		872	(rhdPtr->ChipFamily == CHIP_FAMILY_RS690) \|\|
		873	(rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
		874	rhdPtr->has_tcl = FALSE;
		875	else {
881	serge	876	rhdPtr->has_tcl = TRUE;
1002	serge	877	}
881	serge	878
1002	serge	879	rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
881	serge	880
1002	serge	881	return TRUE;
881	serge	882
1002	serge	883
881	serge	884	#if 0
		885
883	serge	886	{
		887	unsigned char *RADEONMMIO = info->MMIO;
		888	// unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */
		889	// unsigned int vendor = drmAgpVendorId(info->dri->drmFD);
		890	// unsigned int device = drmAgpDeviceId(info->dri->drmFD);
		891	/* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
		892	pcie-agp rialto bridge chip - use the one from bridge which must match */
		893	uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK;
		894	Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
		895	unsigned int defaultMode;
		896
		897	if (is_v3) {
		898
		899	} else {
		900	if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
		901	else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
		902	else defaultMode = 1;
		903	}
		904
		905	// agpMode = defaultMode;
		906
		907	dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf);
		908
		909	mode &= ~RADEON_AGP_MODE_MASK;
		910
		911	/* only set one mode bit for AGPv3 */
		912	switch (defaultMode) {
		913	case 8: mode \|= RADEON_AGPv3_8X_MODE; break;
		914	case 4: default: mode \|= RADEON_AGPv3_4X_MODE;
		915	}
		916	/*TODO: need to take care of other bits valid for v3 mode
		917	* currently these bits are not used in all tested cards.
		918	*/
		919	} else {
		920	switch (defaultMode) {
		921	case 4: mode \|= RADEON_AGP_4X_MODE;
		922	case 2: mode \|= RADEON_AGP_2X_MODE;
		923	case 1: default: mode \|= RADEON_AGP_1X_MODE;
		924	}
		925	}
		926
		927	/* AGP Fast Writes.
		928
		929	* writes at all */
		930	mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
		931
		932	dbgprintf("AGP Mode 0x%08lx\n", mode);
		933
		934	if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
		935
		936	drmAgpRelease(info->dri->drmFD);
		937	return FALSE;
		938	}
		939
		940	/* Workaround for some hardware bugs */
		941
		942	OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) \| 0x000e0000);
		943
		944	/* Modify the mode if the default mode
		945
		946	* particular combination of graphics
		947	* card and AGP chipset.
		948	*/
		949
		950	return TRUE;
		951
		952	#endif
		953
		954	Bool RHDPreInit()
		955
808	serge	956	RHDPtr info;
		957
883	serge	958	/* We need access to IO space already */
		959
808	serge	960	dbgprintf("Failed to map MMIO.\n");
1002	serge	961	return FALSE;
881	serge	962	};
		963
1002	serge	964
808	serge	965
		966
1002	serge	967
		968	if (!RADEONPreInitVRAM(&rhd))
808	serge	969
1002	serge	970
		971	RADEONInitMemoryMap(&rhd);
808	serge	972
1002	serge	973	if (!rhd.videoRam)
881	serge	974
1002	serge	975	dbgprintf("No Video RAM detected.\n");
		976	goto error1;
		977	}
		978	dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
		979
		980	// rhd.FbFreeStart = 0;
881	serge	981
883	serge	982
1002	serge	983	// if( !rhdMapFB(&rhd))
881	serge	984
		985
		986	// rhd.FbScanoutStart = 0;
		987
		988
		989	rhd.FbFreeStart = 1010241024;
		990
1002	serge	991
		992	rhdInitHeap(&rhd);
808	serge	993
1002	serge	994	info = &rhd;
808	serge	995
1002	serge	996	return TRUE;
883	serge	997
1002	serge	998	error1:
883	serge	999
1002	serge	1000	return FALSE;
883	serge	1001
1002	serge	1002
808	serge	1003	static void RADEONPllErrataAfterIndex()
		1004
1002	serge	1005	if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
		1006	return;
		1007
		1008	/* This workaround is necessary on rv200 and RS200 or PLL
808	serge	1009
1002	serge	1010	*/
		1011	(void)INREG(RADEON_CLOCK_CNTL_DATA);
		1012	(void)INREG(RADEON_CRTC_GEN_CNTL);
		1013	}
		1014
		1015
879	serge	1016
1002	serge	1017
		1018
		1019	/* This function is required to workaround a hardware bug in some (all?)
		1020
		1021	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1022	* may not be correct.
		1023	*/
		1024	if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
		1025	{
		1026	u32_t save, tmp;
		1027
		1028	save = INREG(RADEON_CLOCK_CNTL_INDEX);
		1029
		1030	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
		1031	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
		1032	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
		1033	}
		1034	}
		1035
		1036
		1037
		1038
		1039	{
		1040	u32_t data;
		1041
		1042	OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
		1043
		1044	data = INREG(RADEON_CLOCK_CNTL_DATA);
		1045	RADEONPllErrataAfterData();
		1046
		1047	return data;
		1048
		1049
		1050	/* Write PLL information */
		1051
		1052	{
		1053	OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) \|
		1054	RADEON_PLL_WR_EN));
		1055	RADEONPllErrataAfterIndex();
		1056	OUTREG(RADEON_CLOCK_CNTL_DATA, data);
		1057	RADEONPllErrataAfterData();
		1058	}
		1059
		1060	static void init_pipes(RHDPtr info)
		1061
		1062	u32_t gb_tile_config = 0;
		1063
		1064	if ( (info->ChipFamily == CHIP_FAMILY_RV410) \|\|
		1065
		1066	(info->ChipFamily == CHIP_FAMILY_RS600) \|\|
		1067	(info->ChipFamily == CHIP_FAMILY_RS690) \|\|
		1068	(info->ChipFamily == CHIP_FAMILY_RS740) \|\|
		1069	(info->ChipFamily == CHIP_FAMILY_RS400) \|\|
		1070	(info->ChipFamily == CHIP_FAMILY_RS480) \|\| IS_R500_3D)
		1071	{
		1072	u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
		1073
		1074	info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
		1075
		1076	OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 \| ((gb_pipe_sel >> 8) & 0xf) << 4));
		1077	}
		1078	else
		1079	{
		1080	if ((info->ChipFamily == CHIP_FAMILY_R300) \|\|
		1081	(info->ChipFamily == CHIP_FAMILY_R350))
		1082	{
		1083	/* R3xx chips */
		1084	info->num_gb_pipes = 2;
		1085	}
		1086	else {
		1087	/* RV3xx chips */
		1088	info->num_gb_pipes = 1;
		1089	}
		1090	}
		1091
		1092	if (IS_R300_3D \|\| IS_R500_3D)
		1093
		1094
		1095	dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
		1096
		1097	switch(info->num_gb_pipes) {
		1098
		1099	case 3: gb_tile_config \|= R300_PIPE_COUNT_R420_3P; break;
		1100	case 4: gb_tile_config \|= R300_PIPE_COUNT_R420; break;
		1101	default:
		1102	case 1: gb_tile_config \|= R300_PIPE_COUNT_RV350; break;
		1103	}
		1104
		1105	OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
		1106
		1107	OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) \| R300_PIPE_AUTO_CONFIG);
		1108	OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) \|
		1109	R300_DC_AUTOFLUSH_ENABLE \|
		1110	R300_DC_DC_DISABLE_IGNORE_PE));
		1111	}
		1112	else
		1113	OUTREG(RADEON_RB3D_CNTL, 0);
		1114	};
		1115

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(root)/programs/system/drivers/ati2d/init.c – Rev 1002