WebSVN – Kolibri OS – Blame – /programs/system/drivers/ati2d/blend.inc

Rev	Author	Line No.	Line
885	serge	1
		2	Bool dst_alpha;
		3	Bool src_alpha;
		4	u32_t blend_cntl;
		5	};
		6
		7
		8	/* 0 - Clear */
		9	{0, 0, RADEON_SRC_BLEND_GL_ZERO \| RADEON_DST_BLEND_GL_ZERO},
		10	/* 1 - Src */
		11	{0, 0, RADEON_SRC_BLEND_GL_ONE \| RADEON_DST_BLEND_GL_ZERO},
		12	/* 2 - Dst */
		13	{0, 0, RADEON_SRC_BLEND_GL_ZERO \| RADEON_DST_BLEND_GL_ONE},
		14	/* 3 - Over */
		15	{0, 1, RADEON_SRC_BLEND_GL_ONE \| RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
		16	/* 4 - OverReverse */
		17	{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA \| RADEON_DST_BLEND_GL_ONE},
		18	/* 5 - In */
		19	{1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA \| RADEON_DST_BLEND_GL_ZERO},
		20	/* 6 - InReverse */
		21	{0, 1, RADEON_SRC_BLEND_GL_ZERO \| RADEON_DST_BLEND_GL_SRC_ALPHA},
		22	/* 7 - Out */
		23	{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA \| RADEON_DST_BLEND_GL_ZERO},
		24	/* 8 - OutReverse */
		25	{0, 1, RADEON_SRC_BLEND_GL_ZERO \| RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
		26	/* 9 - Atop */
		27	{1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA \| RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
		28	/* 10- AtopReverse */
		29	{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA \| RADEON_DST_BLEND_GL_SRC_ALPHA},
		30	/* 11 - Xor */
		31	{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA \| RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
		32	/* 12 - Add */
		33	{0, 0, RADEON_SRC_BLEND_GL_ONE \| RADEON_DST_BLEND_GL_ONE},
		34	};
		35
		36
954	serge	37	local_pixmap_t *srcpix, int srcX, int srcY,
		38	int w, int h, int alpha)
		39	{
		40	u32_t tex_size = 0, txformat, blend_cntl;
		41	int dst_pitch;
		42
885	serge	43
954	serge	44	return FALSE;
		45
		46
		47	RADEON_TXFORMAT_ALPHA_IN_MAP \|
		48	RADEON_TXFORMAT_NON_POWER2;
		49
		50
		51	RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
		52
		53
		54	{
		55	u32_t *ring;
		56	u32_t ifl = safe_cli();
		57
		58
		59	OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
		60	OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
		61	OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size);
		62	OUT_ACCEL_REG(R200_PP_TXPITCH_0, srcpix->pitch - 32);
		63	OUT_ACCEL_REG(R200_PP_TXOFFSET_0, (u32_t)srcpix->local);
		64	OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST \|
		65	R200_MIN_FILTER_NEAREST \|
		66	R200_CLAMP_S_WRAP \|
		67	R200_CLAMP_T_WRAP);
		68
		69
		70	RADEON_ALPHA_BLEND_ENABLE);
		71	OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE \|
		72	RADEON_TEX_BLEND_0_ENABLE);
		73	OUT_ACCEL_REG(R200_PP_TFACTOR_0, alpha << 24);
		74	OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR \|
		75	R200_TXC_ARG_B_R0_ALPHA);
		76	OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,R200_TXC_OUTPUT_REG_R0);
		77	OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA \|
		78	R200_TXA_ARG_B_R0_ALPHA);
		79	OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
		80	OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
		81	OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
		82	OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
		83
		84
		85	OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, (u32_t)dstpix->local);
		86
		87
		88	safe_sti(ifl);
		89	};
		90
		91
		92	}
		93
		94
885	serge	95	{
		96	u32_t txfilter, txformat0, txformat1, txoffset, txpitch;
		97	// int w = pPict->pDrawable->width;
		98	// int h = pPict->pDrawable->height;
		99	int i, pixel_shift;
		100
		101
		102
		103	txoffset = (u32_t)srcpix->local;
		104
		105
		106	dbgprintf("Bad texture offset 0x%x\n", (int)txoffset);
		107	if ((txpitch & 0x1f) != 0)
		108	dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch);
		109
		110
		111	pixel_shift = 32 >> 4;
		112	txpitch >>= pixel_shift;
		113	txpitch -= 1;
		114
		115
		116	// txoffset \|= R300_MACRO_TILE;
		117
		118
		119	// {
		120	// if (R300TexFormats[i].fmt == pPict->format)
		121	// break;
		122	// }
		123
		124
		125
		126
954	serge	127
885	serge	128
		129	(((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
		130
		131
		132	txpitch \|= R500_TXWIDTH_11;
		133
		134
		135	txpitch \|= R500_TXHEIGHT_11;
		136
		137
		138	* omit this if there is no padding, but there is no apparent advantage
		139	* in doing so.
		140	*/
		141	txformat0 \|= R300_TXPITCH_EN;
		142
		143
		144	// info->texH[unit] = h;
		145
		146
		147	// txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
		148	// else
		149	txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
		150
		151
		152	// txfilter \|= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
		153	// else
		154	txfilter \|= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
		155
		156
		157
		158
		159	// case PictFilterNearest:
		160	txfilter \|= (R300_TX_MAG_FILTER_NEAREST \| R300_TX_MIN_FILTER_NEAREST);
		161	// break;
		162	// case PictFilterBilinear:
		163	// txfilter \|= (R300_TX_MAG_FILTER_LINEAR \| R300_TX_MIN_FILTER_LINEAR);
		164	// break;
		165	// default:
		166	// RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
		167	// }
		168
		169
		170	u32_t *ring;
		171	u32_t ifl = safe_cli();
		172
		173
		174
		175
		176	OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
		177	OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
		178	OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
		179	OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
		180	OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
		181	// if (!pPict->repeat)
		182	OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
		183
		184
		185	safe_sti(ifl);
		186	}
		187	// if (pPict->transform != 0) {
		188	// is_transform[unit] = TRUE;
		189	// transform[unit] = pPict->transform;
		190	// } else {
		191	// is_transform[unit] = FALSE;
		192	// }
		193
		194
		195	}
		196
		197
		198	{
		199	u32_t sblend, dblend;
		200
		201
		202	// dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
		203
		204
		205	* it as always 1.
		206	*/
		207	// if ( RadeonBlendOp[op].dst_alpha) {
		208	// if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
		209	// sblend = RADEON_SRC_BLEND_GL_ONE;
		210	// else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
		211	// sblend = RADEON_SRC_BLEND_GL_ZERO;
		212	// }
		213
		214
		215
		216
		217	}
		218
		219
		220
		221	local_pixmap_t *srcpix, int srcX, int srcY,
		222	int w, int h, int op)
		223	{
		224	// RINFO_FROM_SCREEN(pDst->drawable.pScreen);
		225	u32_t dst_format, dst_offset, dst_pitch;
		226	u32_t txenable, colorpitch;
		227	u32_t blendcntl;
		228	int pixel_shift;
		229	u32_t *ring;
		230
		231
		232
		233
		234
		235
		236
		237
		238
		239
		240
		241
		242
		243
		244
		245
		246	// colorpitch \|= R300_COLORTILE;
		247
		248
		249
		250
		251	dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset);
		252	if (((dst_pitch >> pixel_shift) & 0x7) != 0)
		253	dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch);
		254
		255
		256	// return FALSE;
		257
		258
		259	return FALSE;
		260
		261
		262
		263
		264
		265
		266
		267
		268
		269
		270
		271
		272	RADEON_WAIT_3D_IDLECLEAN);
		273
		274
		275	* to the PVS unit of GA input (when PVS is disabled)
		276	* DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
		277	* enabled. This memory provides the imputs to the vertex shader program
		278	* and ordering is not important. When PVS/TCL is disabled, this field maps
		279	* directly to the GA input memory and the order is signifigant. In
		280	* PVS_BYPASS mode the order is as follows:
		281	* 0 Position
		282	* 1 Point Size
		283	* 2 Color 0
		284	* 3 Color 1
		285	* 4 Color 2
		286	* 5 Color 3
		287	* 6 Textures 0
		288	* 7 Textures 1
		289	* 8 Textures 2
		290	* 9 Textures 3 - 7
		291	* 14 Fog
		292	*/
		293
		294
		295	((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) \|
		296	(0 << R300_SKIP_DWORDS_0_SHIFT) \|
		297	(0 << R300_DST_VEC_LOC_0_SHIFT) \|
		298	R300_SIGNED_0 \|
		299	(R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) \|
		300	(0 << R300_SKIP_DWORDS_1_SHIFT) \|
		301	(6 << R300_DST_VEC_LOC_1_SHIFT) \|
		302	R300_LAST_VEC_1 \|
		303	R300_SIGNED_1));
		304
		305
		306	* We pre-load vertex programs in RADEONInit3DEngine():
		307	* - exa no mask
		308	* - exa mask
		309	* - Xv
		310	* Here we select the offset of the vertex program we want to use
		311	*/
		312	if (info->has_tcl) {
954	serge	313	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
885	serge	314	((3 << R300_PVS_FIRST_INST_SHIFT) \|
954	serge	315	(4 << R300_PVS_XYZW_VALID_INST_SHIFT) \|
		316	(4 << R300_PVS_LAST_INST_SHIFT)));
		317	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
885	serge	318	(4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
954	serge	319	}
		320
885	serge	321
		322	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); //VTX_COLOR_0_PRESENT
		323	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
		324
		325
		326	OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
		327	FINISH_ACCEL();
		328
		329
		330
		331
		332
		333	if (IS_R300_3D)
		334	{
		335	u32_t output_fmt;
954	serge	336	int src_color, src_alpha;
		337	int mask_color, mask_alpha;
		338
		339
		340
		341
		342
		343
		344	mask_alpha = R300_ALU_ALPHA_1_0;
		345
		346
		347	output_fmt = (R300_OUT_FMT_C4_8 \|
		348	R300_OUT_FMT_C0_SEL_BLUE \|
		349	R300_OUT_FMT_C1_SEL_GREEN \|
		350	R300_OUT_FMT_C2_SEL_RED \|
		351	R300_OUT_FMT_C3_SEL_ALPHA);
		352
		353
		354
		355	BEGIN_ACCEL(10);
		356	/* 2 components: 2 for tex0 */
		357	OUT_ACCEL_REG(R300_RS_COUNT,
		358	((2 << R300_RS_COUNT_IT_COUNT_SHIFT) \|
		359	R300_RS_COUNT_HIRES_EN));
		360
		361
		362
		363
		364	R300_ALU_CODE_SIZE(0) \|
		365	R300_TEX_CODE_OFFSET(0) \|
		366	R300_TEX_CODE_SIZE(0)));
		367
		368
		369	(R300_ALU_START(0) \|
		370	R300_ALU_SIZE(0) \|
		371	R300_TEX_START(0) \|
		372	R300_TEX_SIZE(0) \|
		373	R300_RGBA_OUT));
		374
		375
		376	/* shader output swizzling */
		377	OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
		378
		379
		380	/* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */
		381
		382
		383	* temp addresses for texture inputs
		384	* ALU_RGB_ADDR0 is src tex (temp 0)
		385	* ALU_RGB_ADDR1 is mask tex (temp 1)
		386	* R300_ALU_RGB_OMASK - output components to write
		387	* R300_ALU_RGB_TARGET_A - render target
		388	*/
		389	OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0),
		390	(R300_ALU_RGB_ADDR0(0) \|
		391	R300_ALU_RGB_ADDR1(1) \|
		392	R300_ALU_RGB_ADDR2(0) \|
		393	R300_ALU_RGB_ADDRD(0) \|
		394	R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R \|
		395	R300_ALU_RGB_MASK_G \|
		396	R300_ALU_RGB_MASK_B)) \|
		397	R300_ALU_RGB_TARGET_A));
		398	/* RGB inst
		399	* ALU operation
		400	*/
		401	OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0),
		402	(R300_ALU_RGB_SEL_A(src_color) \|
		403	R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) \|
		404	R300_ALU_RGB_SEL_B(mask_color) \|
		405	R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) \|
		406	R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) \|
		407	R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) \|
		408	R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) \|
		409	R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) \|
		410	R300_ALU_RGB_CLAMP));
		411	/* Alpha inst
		412	* temp addresses for texture inputs
		413	* ALU_ALPHA_ADDR0 is src tex (0)
		414	* ALU_ALPHA_ADDR1 is mask tex (1)
		415	* R300_ALU_ALPHA_OMASK - output components to write
		416	* R300_ALU_ALPHA_TARGET_A - render target
		417	*/
		418	OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0),
		419	(R300_ALU_ALPHA_ADDR0(0) \|
		420	R300_ALU_ALPHA_ADDR1(1) \|
		421	R300_ALU_ALPHA_ADDR2(0) \|
		422	R300_ALU_ALPHA_ADDRD(0) \|
		423	R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) \|
		424	R300_ALU_ALPHA_TARGET_A \|
		425	R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
		426	/* Alpha inst
		427	* ALU operation
		428	*/
		429	OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0),
		430	(R300_ALU_ALPHA_SEL_A(src_alpha) \|
		431	R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) \|
		432	R300_ALU_ALPHA_SEL_B(mask_alpha) \|
		433	R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) \|
		434	R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) \|
		435	R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) \|
		436	R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) \|
		437	R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) \|
		438	R300_ALU_ALPHA_CLAMP));
		439	FINISH_ACCEL();
		440	}
885	serge	441	else
		442	{
		443	u32_t output_fmt;
		444	u32_t src_color, src_alpha;
		445	u32_t mask_color, mask_alpha;
		446
		447
		448	// src_color = (R500_ALU_RGB_R_SWIZ_A_0 \|
		449	// R500_ALU_RGB_G_SWIZ_A_0 \|
		450	// R500_ALU_RGB_B_SWIZ_A_0);
		451	// else
		452	src_color = (R500_ALU_RGB_R_SWIZ_A_R \|
		453	R500_ALU_RGB_G_SWIZ_A_G \|
954	serge	454	R500_ALU_RGB_B_SWIZ_A_B);
		455
885	serge	456
		457	// src_alpha = R500_ALPHA_SWIZ_A_1;
		458	// else
		459	src_alpha = R500_ALPHA_SWIZ_A_A;
		460
		461
		462	R500_ALU_RGB_G_SWIZ_B_1 \|
		463	R500_ALU_RGB_B_SWIZ_B_1);
		464	mask_alpha = R500_ALPHA_SWIZ_B_1;
		465
		466
		467	output_fmt = (R300_OUT_FMT_C4_8 \|
		468	R300_OUT_FMT_C0_SEL_BLUE \|
		469	R300_OUT_FMT_C1_SEL_GREEN \|
		470	R300_OUT_FMT_C2_SEL_RED \|
		471	R300_OUT_FMT_C3_SEL_ALPHA);
		472
		473
		474	OUT_ACCEL_REG(R300_RS_COUNT,
		475	((2 << R300_RS_COUNT_IT_COUNT_SHIFT) \|
		476	R300_RS_COUNT_HIRES_EN));
		477
		478
		479
		480
		481	R500_US_CODE_END_ADDR(1)));
		482	OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) \|
		483	R500_US_CODE_RANGE_SIZE(1)));
		484	OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
		485
		486
		487	COMMIT_RING();
		488
		489
		490	OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
		491	/* tex inst for src texture */
		492	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX \|
		493	R500_INST_TEX_SEM_WAIT \|
		494	R500_INST_RGB_WMASK_R \|
		495	R500_INST_RGB_WMASK_G \|
		496	R500_INST_RGB_WMASK_B \|
		497	R500_INST_ALPHA_WMASK \|
		498	R500_INST_RGB_CLAMP \|
		499	R500_INST_ALPHA_CLAMP));
		500
		501
		502	R500_TEX_INST_LD \|
		503	R500_TEX_SEM_ACQUIRE \|
		504	R500_TEX_IGNORE_UNCOVERED));
		505
		506
		507	R500_TEX_SRC_S_SWIZ_R \|
		508	R500_TEX_SRC_T_SWIZ_G \|
		509	R500_TEX_DST_ADDR(0) \|
		510	R500_TEX_DST_R_SWIZ_R \|
		511	R500_TEX_DST_G_SWIZ_G \|
		512	R500_TEX_DST_B_SWIZ_B \|
		513	R500_TEX_DST_A_SWIZ_A));
		514	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) \|
		515	R500_DX_S_SWIZ_R \|
		516	R500_DX_T_SWIZ_R \|
		517	R500_DX_R_SWIZ_R \|
		518	R500_DX_Q_SWIZ_R \|
		519	R500_DY_ADDR(0) \|
		520	R500_DY_S_SWIZ_R \|
		521	R500_DY_T_SWIZ_R \|
		522	R500_DY_R_SWIZ_R \|
		523	R500_DY_Q_SWIZ_R));
		524	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
		525	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
		526
		527
		528	/* _OMASK - output component write mask */
		529	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT \|
		530	R500_INST_TEX_SEM_WAIT \|
		531	R500_INST_LAST \|
		532	R500_INST_RGB_OMASK_R \|
		533	R500_INST_RGB_OMASK_G \|
		534	R500_INST_RGB_OMASK_B \|
		535	R500_INST_ALPHA_OMASK \|
		536	R500_INST_RGB_CLAMP \|
		537	R500_INST_ALPHA_CLAMP));
		538	/* ALU inst
		539	* temp addresses for texture inputs
		540	* RGB_ADDR0 is src tex (temp 0)
		541	* RGB_ADDR1 is mask tex (temp 1)
		542	*/
		543	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) \|
		544	R500_RGB_ADDR1(1) \|
		545	R500_RGB_ADDR2(0)));
		546	/* ALU inst
		547	* temp addresses for texture inputs
		548	* ALPHA_ADDR0 is src tex (temp 0)
		549	* ALPHA_ADDR1 is mask tex (temp 1)
		550	*/
		551	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) \|
		552	R500_ALPHA_ADDR1(1) \|
		553	R500_ALPHA_ADDR2(0)));
		554
		555
		556	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 \|
		557	src_color \|
		558	R500_ALU_RGB_SEL_B_SRC1 \|
		559	mask_color \|
		560	R500_ALU_RGB_TARGET(0)));
		561
		562
		563	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD \|
		564	R500_ALPHA_ADDRD(0) \|
		565	R500_ALPHA_SEL_A_SRC0 \|
		566	src_alpha \|
		567	R500_ALPHA_SEL_B_SRC1 \|
		568	mask_alpha \|
		569	R500_ALPHA_TARGET(0)));
		570
		571
		572	R500_ALU_RGBA_ADDRD(0) \|
		573	R500_ALU_RGBA_R_SWIZ_0 \|
		574	R500_ALU_RGBA_G_SWIZ_0 \|
		575	R500_ALU_RGBA_B_SWIZ_0 \|
		576	R500_ALU_RGBA_A_SWIZ_0));
		577	FINISH_ACCEL();
		578	}
		579
		580
		581	OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
		582	OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
		583
		584
		585	OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl \| R300_ALPHA_BLEND_ENABLE \|
		586	R300_READ_ENABLE);
		587
		588
		589
		590
		591
		592
		593	}
		594
		595
		596
		597
		598
		599	{
		600	union {
		601	float f;
		602	u32_t l;
		603	} tmp;
		604	tmp.f = val;
		605	return tmp.l;
		606	}
		607
		608
		609
		610
		611	do { \
954	serge	612	OUT_RING_F(_dstX); \
		613	OUT_RING_F(_dstY); \
		614	OUT_RING_F(_srcX); \
		615	OUT_RING_F(_srcY); \
		616	} while (0)
885	serge	617
		618
		619
		620
954	serge	621	int dstX, int dstY,
885	serge	622	int w, int h)
		623	{
		624	// RINFO_FROM_SCREEN(pDst->drawable.pScreen);
		625	int vtx_count;
		626	xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
		627	xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
		628
		629
		630
		631
		632
		633
		634
		635
		636
		637
		638	srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
		639
		640
		641	srcTopLeft.y = IntToxFixed(srcY);
		642	srcTopRight.x = IntToxFixed(srcX + w);
		643	srcTopRight.y = IntToxFixed(srcY);
		644	srcBottomLeft.x = IntToxFixed(srcX);
		645	srcBottomLeft.y = IntToxFixed(srcY + h);
		646	srcBottomRight.x = IntToxFixed(srcX + w);
		647	srcBottomRight.y = IntToxFixed(srcY + h);
		648
		649
		650	if (is_transform[0]) {
		651	transformPoint(transform[0], &srcTopLeft);
		652	transformPoint(transform[0], &srcTopRight);
		653	transformPoint(transform[0], &srcBottomLeft);
		654	transformPoint(transform[0], &srcBottomRight);
		655	}
		656	if (is_transform[1]) {
		657	transformPoint(transform[1], &maskTopLeft);
		658	transformPoint(transform[1], &maskTopRight);
		659	transformPoint(transform[1], &maskBottomLeft);
		660	transformPoint(transform[1], &maskBottomRight);
		661	}
		662	*/
		663	vtx_count = VTX_COUNT;
		664
		665
		666
		667
		668
		669
		670
		671
		672
		673	4 * vtx_count));
		674	OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN \|
		675	RADEON_CP_VC_CNTL_PRIM_WALK_RING \|
		676	(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
		677
		678
		679
		680	xFixedToFloat(srcTopLeft.x) / w, // info->texW[0],
		681	xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]);
		682
		683
		684	xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0],
		685	xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]);
		686
		687
		688	xFixedToFloat(srcBottomRight.x) / w, // info->texW[0],
		689	xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
		690
		691
		692	xFixedToFloat(srcTopRight.x) / w, // info->texW[0],
		693	xFixedToFloat(srcTopRight.y) / h); // info->texH[0]);
		694
		695
		696	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
		697
		698
954	serge	699
885	serge	700
		701
		702
		703
		704
		705	}
		706
954	serge	707
		708
		709	int dstX, int dstY,
		710	int w, int h)
		711	{
		712	xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
		713	xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
		714
		715
		716	srcTopLeft.y = IntToxFixed(srcY);
		717	srcTopRight.x = IntToxFixed(srcX + w);
		718	srcTopRight.y = IntToxFixed(srcY);
		719	srcBottomLeft.x = IntToxFixed(srcX);
		720	srcBottomLeft.y = IntToxFixed(srcY + h);
		721	srcBottomRight.x = IntToxFixed(srcX + w);
		722	srcBottomRight.y = IntToxFixed(srcY + h);
		723
		724
		725	u32_t *ring;
		726	u32_t ifl = safe_cli();
		727
		728
		729
		730
		731	OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN \|
		732	RADEON_CP_VC_CNTL_PRIM_WALK_RING \|
		733	(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
		734
		735
		736
		737	xFixedToFloat(srcTopLeft.x) / w, // info->texW[0],
		738	xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]);
		739
		740
		741	xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0],
		742	xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]);
		743
		744
		745	xFixedToFloat(srcBottomRight.x) / w, // info->texW[0],
		746	xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
		747
		748
		749	xFixedToFloat(srcTopRight.x) / w, // info->texW[0],
		750	xFixedToFloat(srcTopRight.y) / h); // info->texH[0]);
		751
		752
		753
		754
		755	safe_sti(ifl);
		756	};
		757	};
		758
		759
885	serge	760	#undef VTX_OUT_MASK
		761
		762
		763
		764	{
		765	int tileSrcY, tileMaskY, tileDstY;
		766	int remainingHeight;
		767
		768
		769	local_pixmap_t *dstpixmap;
		770
		771
		772
		773
		774	srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
		775
		776
		777	u32_t *ring;
		778	u32_t ifl = safe_cli();
		779
		780
		781
		782
		783
		784
		785
		786
		787	RADEON_GMC_BRUSH_SOLID_COLOR \|
		788	RADEON_GMC_DST_32BPP \|
		789	RADEON_GMC_SRC_DATATYPE_COLOR \|
		790	R5XX_GMC_CLR_CMP_CNTL_DIS \|
		791	R5XX_ROP3_P
		792	);
		793
		794
		795	OUT_RING(blit->alpha<<24);
954	serge	796	OUT_RING( 0 );
885	serge	797	OUT_RING((srcpixmap->width<<16)\|srcpixmap->height);
		798
		799
		800
		801
954	serge	802
		803
		804	{
		805	R300PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y,
		806	srcpixmap, blit->src_x, blit->src_y,
		807	blit->w, blit->h, 3);
		808
		809
		810	R300CompositeTile( blit->src_x, blit->src_y,
		811	blit->dst_x, blit->dst_y,
		812	blit->w, blit->h);
		813	}
		814	else if ((info->ChipFamily == CHIP_FAMILY_RV250) \|\|
		815	(info->ChipFamily == CHIP_FAMILY_RV280) \|\|
		816	(info->ChipFamily == CHIP_FAMILY_RS300) \|\|
		817	(info->ChipFamily == CHIP_FAMILY_R200))
		818	{
		819	R200PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y,
		820	srcpixmap, blit->src_x, blit->src_y,
		821	blit->w, blit->h, blit->alpha);
		822	R200CompositeTile( blit->src_x, blit->src_y,
		823	blit->dst_x, blit->dst_y,
		824	blit->w, blit->h);
		825	};
		826
		827
		828
885	serge	829	};
		830
		831
		832
954	serge	833
		834	// }
885	serge	835
		836
		837
		838
		839	modulus(srcY, src_tile_height, tileSrcY);
		840	tileMaskY = maskY;
		841	tileDstY = dstY;
		842
		843
		844	while (remainingHeight > 0) {
		845	int remainingWidth = width;
		846	int tileSrcX, tileMaskX, tileDstX;
		847	int h = src_tile_height - tileSrcY;
		848
		849
		850	h = remainingHeight;
		851	remainingHeight -= h;
		852
		853
		854	tileMaskX = maskX;
		855	tileDstX = dstX;
		856
		857
		858	int w = src_tile_width - tileSrcX;
		859	if (w > remainingWidth)
		860	w = remainingWidth;
		861	remainingWidth -= w;
		862
		863
		864	tileSrcX, tileSrcY,
		865	tileMaskX, tileMaskY,
		866	tileDstX, tileDstY,
		867	w, h);
		868
		869
		870	tileMaskX += w;
		871	tileDstX += w;
		872	}
		873	tileSrcY = 0;
		874	tileMaskY += h;
		875	tileDstY += h;
		876	}
		877	#endif
		878
		879
		880	>

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(root)/programs/system/drivers/ati2d/blend.inc – Rev 954