Rev 883 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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813 | serge | 1 | |
877 | serge | 2 | |
3 | |||
4 | |||
5 | |||
6 | |||
7 | |||
8 | |||
9 | |||
808 | serge | 10 | |
881 | serge | 11 | |
813 | serge | 12 | |
881 | serge | 13 | { |
14 | CHIP_FAMILY_UNKNOW, |
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15 | CHIP_FAMILY_LEGACY, |
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16 | CHIP_FAMILY_RADEON, |
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17 | CHIP_FAMILY_RV100, |
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18 | CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
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19 | CHIP_FAMILY_RV200, |
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20 | CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
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21 | CHIP_FAMILY_R200, |
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22 | CHIP_FAMILY_RV250, |
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23 | CHIP_FAMILY_RS300, /* RS300/RS350 */ |
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24 | CHIP_FAMILY_RV280, |
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25 | CHIP_FAMILY_R300, |
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26 | CHIP_FAMILY_R350, |
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27 | CHIP_FAMILY_RV350, |
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28 | CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
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29 | CHIP_FAMILY_R420, /* R420/R423/M18 */ |
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30 | CHIP_FAMILY_RV410, /* RV410, M26 */ |
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31 | CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ |
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32 | CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ |
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33 | CHIP_FAMILY_RV515, /* rv515 */ |
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34 | CHIP_FAMILY_R520, /* r520 */ |
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35 | CHIP_FAMILY_RV530, /* rv530 */ |
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36 | CHIP_FAMILY_R580, /* r580 */ |
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37 | CHIP_FAMILY_RV560, /* rv560 */ |
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38 | CHIP_FAMILY_RV570, /* rv570 */ |
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39 | CHIP_FAMILY_RS600, |
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40 | CHIP_FAMILY_RS690, |
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41 | CHIP_FAMILY_RS740, |
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42 | CHIP_FAMILY_R600, /* r600 */ |
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43 | CHIP_FAMILY_R630, |
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44 | CHIP_FAMILY_RV610, |
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45 | CHIP_FAMILY_RV630, |
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46 | CHIP_FAMILY_RV670, |
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47 | CHIP_FAMILY_RV620, |
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48 | CHIP_FAMILY_RV635, |
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49 | CHIP_FAMILY_RS780, |
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50 | CHIP_FAMILY_RV770, |
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51 | CHIP_FAMILY_LAST |
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52 | } RADEONChipFamily; |
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53 | |||
813 | serge | 54 | |
881 | serge | 55 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \ |
56 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \ |
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57 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \ |
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58 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \ |
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59 | (rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \ |
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60 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300)) |
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61 | |||
808 | serge | 62 | |
812 | serge | 63 | |
881 | serge | 64 | (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
65 | (info->ChipFamily == CHIP_FAMILY_R350) || \ |
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66 | (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
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67 | (info->ChipFamily == CHIP_FAMILY_R420) || \ |
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68 | (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
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69 | (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
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70 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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71 | |||
812 | serge | 72 | |
881 | serge | 73 | |
812 | serge | 74 | |
881 | serge | 75 | |
812 | serge | 76 | |
881 | serge | 77 | (info->ChipFamily == CHIP_FAMILY_R520) || \ |
78 | (info->ChipFamily == CHIP_FAMILY_RV530) || \ |
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79 | (info->ChipFamily == CHIP_FAMILY_R580) || \ |
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80 | (info->ChipFamily == CHIP_FAMILY_RV560) || \ |
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81 | (info->ChipFamily == CHIP_FAMILY_RV570)) |
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82 | |||
808 | serge | 83 | |
881 | serge | 84 | (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
85 | (info->ChipFamily == CHIP_FAMILY_R350) || \ |
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86 | (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
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87 | (info->ChipFamily == CHIP_FAMILY_R420) || \ |
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88 | (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
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89 | (info->ChipFamily == CHIP_FAMILY_RS690) || \ |
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90 | (info->ChipFamily == CHIP_FAMILY_RS600) || \ |
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91 | (info->ChipFamily == CHIP_FAMILY_RS740) || \ |
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92 | (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
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93 | (info->ChipFamily == CHIP_FAMILY_RS480)) |
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94 | |||
95 | |||
96 | |||
97 | |||
98 | CARD_PCI, |
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99 | CARD_AGP, |
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100 | CARD_PCIE |
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101 | } RADEONCardType; |
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102 | |||
103 | |||
104 | * Errata workarounds |
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105 | */ |
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106 | typedef enum { |
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107 | CHIP_ERRATA_R300_CG = 0x00000001, |
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108 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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109 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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110 | } RADEONErrata; |
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111 | |||
112 | |||
113 | { |
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114 | u32_t pci_device_id; |
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115 | RADEONChipFamily chip_family; |
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116 | int mobility; |
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117 | int igp; |
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118 | int nocrtc2; |
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119 | int nointtvout; |
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120 | int singledac; |
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121 | } RADEONCardInfo; |
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122 | |||
123 | |||
124 | |||
808 | serge | 125 | #define RHD_MMIO_BAR 2 |
126 | |||
127 | |||
128 | #define RHD_MEM_FB 2 |
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129 | |||
130 | |||
883 | serge | 131 | #define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ |
132 | #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ |
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133 | #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ |
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134 | #define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ |
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135 | |||
136 | |||
137 | |||
138 | |||
139 | |||
140 | |||
141 | |||
808 | serge | 142 | { |
143 | u32_t MMIOBase; |
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877 | serge | 144 | u32_t MMIOMapSize; |
145 | |||
808 | serge | 146 | |
817 | serge | 147 | // u32_t PhisBase; |
881 | serge | 148 | // u32_t FbIntAddress; /* card internal address of FB */ |
149 | // u32_t FbMapSize; |
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150 | |||
808 | serge | 151 | |
877 | serge | 152 | u32_t FbFreeSize; |
153 | |||
808 | serge | 154 | |
155 | // unsigned int FbScanoutStart; |
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881 | serge | 156 | // unsigned int FbScanoutSize; |
157 | |||
808 | serge | 158 | |
881 | serge | 159 | |
812 | serge | 160 | |
881 | serge | 161 | u32_t mc_fb_location; |
162 | u32_t mc_agp_location; |
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163 | u32_t mc_agp_location_hi; |
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164 | |||
808 | serge | 165 | |
881 | serge | 166 | |
808 | serge | 167 | |
881 | serge | 168 | u32_t BusCntl; |
169 | unsigned long FbMapSize; /* Size of frame buffer, in bytes */ |
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170 | unsigned long FbSecureSize; /* Size of secured fb area at end of |
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171 | framebuffer */ |
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172 | |||
173 | |||
174 | |||
175 | RADEONErrata ChipErrata; |
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176 | |||
177 | |||
178 | |||
179 | |||
883 | serge | 180 | Bool IsMobility; |
181 | Bool HasCRTC2; |
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182 | |||
881 | serge | 183 | |
877 | serge | 184 | u32_t devfn; |
185 | |||
808 | serge | 186 | |
881 | serge | 187 | u16_t PciDeviceID; |
877 | serge | 188 | |
808 | serge | 189 | |
877 | serge | 190 | u16_t subdevice_id; |
191 | |||
808 | serge | 192 | |
881 | serge | 193 | |
194 | |||
877 | serge | 195 | u32_t ioBase[6]; |
196 | u32_t memtype[6]; |
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197 | u32_t memsize[6]; |
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198 | |||
808 | serge | 199 | |
200 | struct mem_block *gart_heap; |
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201 | |||
202 | |||
877 | serge | 203 | u32_t displayHeight; |
204 | |||
808 | serge | 205 | |
883 | serge | 206 | |
207 | |||
208 | u32_t ring_rp; |
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209 | u32_t ring_wp; |
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210 | u32_t ringSize; |
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211 | u32_t ring_avail; |
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212 | |||
213 | |||
214 | u32_t gartTexSize; |
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215 | u32_t pciAperSize; |
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216 | u32_t CPusecTimeout; |
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217 | |||
218 | |||
881 | serge | 219 | int __ymin; |
220 | int __xmax; |
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221 | int __ymax; |
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222 | |||
808 | serge | 223 | |
877 | serge | 224 | u32_t dst_pitch_offset; |
225 | u32_t surface_cntl; |
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226 | |||
808 | serge | 227 | |
228 | |||
883 | serge | 229 | |
230 | |||
231 | volatile u32_t scratch1; |
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232 | volatile u32_t scratch2; |
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233 | volatile u32_t scratch3; |
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234 | volatile u32_t scratch4; |
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235 | volatile u32_t scratch5; |
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236 | volatile u32_t scratch6; |
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237 | volatile u32_t scratch7; |
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238 | |||
239 | |||
240 | Bool IsDDR; |
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881 | serge | 241 | |
242 | |||
243 | int has_tcl; |
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244 | |||
883 | serge | 245 | |
808 | serge | 246 | |
247 | |||
248 | |||
249 | |||
250 | |||
815 | serge | 251 | |
876 | serge | 252 | #define R5XX_DP_BRUSH_FRGD_CLR 0x147c |
253 | #define R5XX_BRUSH_DATA0 0x1480 |
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254 | #define R5XX_BRUSH_DATA1 0x1484 |
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255 | |||
815 | serge | 256 | |
876 | serge | 257 | # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
258 | # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
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259 | # define RADEON_GMC_BRUSH_NONE (15 << 4) |
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260 | # define RADEON_GMC_DST_16BPP (4 << 8) |
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261 | # define RADEON_GMC_DST_24BPP (5 << 8) |
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262 | # define RADEON_GMC_DST_32BPP (6 << 8) |
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263 | # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
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264 | # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
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265 | # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
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266 | # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
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267 | # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
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268 | # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
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269 | # define RADEON_ROP3_S 0x00cc0000 |
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270 | # define RADEON_ROP3_P 0x00f00000 |
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271 | |||
815 | serge | 272 | |
876 | serge | 273 | #define RADEON_CP_PACKET1 0x40000000 |
274 | #define RADEON_CP_PACKET2 0x80000000 |
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275 | #define RADEON_CP_PACKET3 0xC0000000 |
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276 | |||
277 | |||
278 | # define RADEON_CNTL_BITBLT 0x00009200 |
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279 | # define RADEON_CNTL_TRANBLT 0x00009C00 |
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280 | |||
281 | |||
282 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
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283 | |||
284 | |||
285 | (RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2)) |
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883 | serge | 286 | |
876 | serge | 287 | |
288 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
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289 | |||
290 | |||
883 | serge | 291 | (RADEON_CP_PACKET2) |
876 | serge | 292 | |
293 | |||
883 | serge | 294 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
876 | serge | 295 | |
296 | |||
297 | |||
883 | serge | 298 | int avail = rhd.ring_rp-rhd.ring_wp; \ |
299 | if (avail <=0 ) avail+= 0x4000; \ |
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885 | serge | 300 | if( (req)+128 > avail) \ |
883 | serge | 301 | { \ |
302 | rhd.ring_rp = INREG(RADEON_CP_RB_RPTR); \ |
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303 | avail = rhd.ring_rp-rhd.ring_wp; \ |
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304 | if (avail <= 0) avail+= 0x4000; \ |
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885 | serge | 305 | if( (req)+128 > avail){ \ |
883 | serge | 306 | safe_sti(ifl); \ |
307 | return 0; \ |
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308 | }; \ |
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309 | } \ |
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310 | ring = &rhd.ringBase[rhd.ring_wp]; \ |
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311 | }while(0); |
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312 | |||
313 | |||
876 | serge | 314 | |
315 | |||
883 | serge | 316 | |
876 | serge | 317 | |
883 | serge | 318 | do { \ |
319 | ring[0] = CP_PACKET0((reg), 1); \ |
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320 | ring[1] = (val); \ |
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321 | ring+= 2; \ |
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322 | } while (0) |
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876 | serge | 323 | |
324 | |||
885 | serge | 325 | |
876 | serge | 326 | |
883 | serge | 327 | rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
328 | /* Flush writes to ring */ \ |
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329 | DRM_MEMORYBARRIER(); \ |
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330 | /*GET_RING_HEAD( dev_priv ); */ \ |
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331 | OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
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332 | /* read from PCI bus to ensure correct posting */ \ |
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333 | /* INREG( RADEON_CP_RB_RPTR ); */ \ |
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334 | } while (0) |
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876 | serge | 335 | |
336 | |||
885 | serge | 337 | #define FINISH_ACCEL() COMMIT_RING() |
338 | |||
876 | serge | 339 | |
885 | serge | 340 | |
876 | serge | 341 | |
885 | serge | 342 | |
808 | serge | 343 | int token; /* id of the token */ |
344 | const char * name; /* token name */ |
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345 | } SymTabRec, *SymTabPtr; |
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346 | |||
347 | |||
813 | serge | 348 | |
349 | |||
350 | OUTREG8(u16_t offset, u8_t value) |
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877 | serge | 351 | { |
813 | serge | 352 | *(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
877 | serge | 353 | } |
813 | serge | 354 | |
355 | |||
356 | |||
877 | serge | 357 | { |
808 | serge | 358 | return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset)); |
877 | serge | 359 | } |
808 | serge | 360 | |
361 | |||
362 | |||
881 | serge | 363 | { |
808 | serge | 364 | *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
877 | serge | 365 | } |
808 | serge | 366 | |
367 | |||
883 | serge | 368 | // *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + (u32_t)(offset))) = (u32_t)value |
369 | |||
881 | serge | 370 | |
883 | serge | 371 | |
877 | serge | 372 | { |
808 | serge | 373 | return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset)); |
877 | serge | 374 | } |
808 | serge | 375 | |
376 | |||
377 | MASKREG(u16_t offset, u32_t value, u32_t mask) |
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877 | serge | 378 | { |
808 | serge | 379 | u32_t tmp; |
877 | serge | 380 | |
808 | serge | 381 | |
382 | tmp &= ~mask; |
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383 | tmp |= (value & mask); |
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384 | OUTREG(offset, tmp); |
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385 | }; |
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386 | |||
387 | |||
883 | serge | 388 | |
389 | |||
390 | |||
391 | |||
392 | |||
393 | |||
808 | serge | 394 | _RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value) |
877 | serge | 395 | { |
808 | serge | 396 | *(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value; |
877 | serge | 397 | } |
808 | serge | 398 | |
399 | |||
400 | _RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask) |
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877 | serge | 401 | { |
808 | serge | 402 | u32_t tmp; |
877 | serge | 403 | |
808 | serge | 404 | |
405 | tmp &= ~mask; |
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406 | tmp |= (value & mask); |
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407 | _RHDRegWrite(rhdPtr, offset, tmp); |
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408 | }; |
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409 | |||
410 | |||
411 | #define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value)) |
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412 | #define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask)) |
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413 | |||
414 | |||
415 | |||
416 | |||
417 | |||
418 | int rhdInitHeap(RHDPtr rhdPtr); |
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419 | |||
420 | |||
421 | |||
422 | |||
423 | // #define DBG(x) |
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424 | |||
425 | |||
426 | typedef struct s_cursor |
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427 | { |
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428 | u32_t magic; // 'CURS' |
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877 | serge | 429 | void (*destroy)(struct s_cursor*); // destructor |
808 | serge | 430 | u32_t fd; // next object in list |
877 | serge | 431 | u32_t bk; // prev object in list |
432 | u32_t pid; // owner id |
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433 | |||
808 | serge | 434 | |
435 | u32_t hot_x; // hotspot coords |
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877 | serge | 436 | u32_t hot_y; |
437 | }cursor_t; |
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808 | serge | 438 | #pragma pack (pop) |
439 | |||
440 | |||
441 | #define LOAD_FROM_MEM 1 |
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442 | #define LOAD_INDIRECT 2 |
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443 | |||
444 | |||
877 | serge | 445 | void __stdcall copy_cursor(void *img, void *src); |
808 | serge | 446 | void destroy_cursor(cursor_t *cursor); |
447 | void __destroy_cursor(cursor_t *cursor); // wrap |
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448 | |||
449 | |||
450 | void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y); |
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451 | void __stdcall r500_CursorRestore(int x, int y); |
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452 | |||
453 | |||
454 | |||
813 | serge | 455 | |
456 | |||
457 | u32_t x ; |
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458 | u32_t y ; |
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459 | } xPointFixed; |
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460 | |||
461 | |||
462 | |||
463 | |||
464 | |||
465 | |||
466 | |||
467 | |||
468 | #define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) |
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469 | |||
470 | |||
471 | |||
472 | |||
473 | ((type) << 16) | \ |
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474 | ((a) << 12) | \ |
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475 | ((r) << 8) | \ |
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476 | ((g) << 4) | \ |
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477 | ((b))) |
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478 | |||
479 | |||
480 | #define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) |
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481 | |||
482 | |||
483 | #define PICT_TYPE_A 1 |
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484 | #define PICT_TYPE_ARGB 2 |
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485 | #define PICT_TYPE_ABGR 3 |
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486 | #define PICT_TYPE_COLOR 4 |
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487 | #define PICT_TYPE_GRAY 5 |
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488 | |||
489 | |||
490 | PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8), |
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491 | PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8), |
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492 | PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8), |
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493 | PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8), |
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494 | |||
495 | |||
496 | PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8), |
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497 | PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8), |
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498 | |||
499 | |||
500 | PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5), |
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501 | PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5), |
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502 | |||
503 | |||
504 | PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5), |
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505 | PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5), |
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506 | PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5), |
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507 | PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4), |
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508 | PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4), |
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509 | PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4), |
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510 | PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4), |
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511 | |||
512 | |||
513 | PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0), |
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514 | PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2), |
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515 | PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2), |
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516 | PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2), |
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517 | PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2), |
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518 | |||
519 | |||
520 | PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
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521 | |||
522 | |||
523 | |||
524 | |||
525 | PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
||
526 | |||
527 | |||
528 | PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0), |
||
529 | PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1), |
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530 | PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1), |
||
531 | PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1), |
||
532 | PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1), |
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533 | |||
534 | |||
535 | PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0), |
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536 | |||
537 | |||
538 | PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0), |
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539 | |||
540 | |||
541 | } PictFormatShort; |
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542 | |||
543 | |||
829 | serge | 544 |