Subversion Repositories Kolibri OS

Rev

Rev 877 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
813 serge 1
 
877 serge 2
3
 
4
 
5
6
 
7
8
 
9
 
881 serge 10
808 serge 11
 
881 serge 12
813 serge 13
 
881 serge 14
{
15
    CHIP_FAMILY_UNKNOW,
16
    CHIP_FAMILY_LEGACY,
17
    CHIP_FAMILY_RADEON,
18
    CHIP_FAMILY_RV100,
19
    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
20
    CHIP_FAMILY_RV200,
21
    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
22
    CHIP_FAMILY_R200,
23
    CHIP_FAMILY_RV250,
24
    CHIP_FAMILY_RS300,    /* RS300/RS350 */
25
    CHIP_FAMILY_RV280,
26
    CHIP_FAMILY_R300,
27
    CHIP_FAMILY_R350,
28
    CHIP_FAMILY_RV350,
29
    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
30
    CHIP_FAMILY_R420,     /* R420/R423/M18 */
31
    CHIP_FAMILY_RV410,    /* RV410, M26 */
32
    CHIP_FAMILY_RS400,    /* xpress 200, 200m (RS400) Intel */
33
    CHIP_FAMILY_RS480,    /* xpress 200, 200m (RS410/480/482/485) AMD */
34
    CHIP_FAMILY_RV515,    /* rv515 */
35
    CHIP_FAMILY_R520,     /* r520 */
36
    CHIP_FAMILY_RV530,    /* rv530 */
37
    CHIP_FAMILY_R580,     /* r580 */
38
    CHIP_FAMILY_RV560,    /* rv560 */
39
    CHIP_FAMILY_RV570,    /* rv570 */
40
    CHIP_FAMILY_RS600,
41
    CHIP_FAMILY_RS690,
42
    CHIP_FAMILY_RS740,
43
    CHIP_FAMILY_R600,     /* r600 */
44
    CHIP_FAMILY_R630,
45
    CHIP_FAMILY_RV610,
46
    CHIP_FAMILY_RV630,
47
    CHIP_FAMILY_RV670,
48
    CHIP_FAMILY_RV620,
49
    CHIP_FAMILY_RV635,
50
    CHIP_FAMILY_RS780,
51
    CHIP_FAMILY_RV770,
52
    CHIP_FAMILY_LAST
53
} RADEONChipFamily;
54
813 serge 55
 
881 serge 56
        (rhdPtr->ChipFamily == CHIP_FAMILY_RV200)  ||  \
57
        (rhdPtr->ChipFamily == CHIP_FAMILY_RS100)  ||  \
58
        (rhdPtr->ChipFamily == CHIP_FAMILY_RS200)  ||  \
59
        (rhdPtr->ChipFamily == CHIP_FAMILY_RV250)  ||  \
60
        (rhdPtr->ChipFamily == CHIP_FAMILY_RV280)  ||  \
61
        (rhdPtr->ChipFamily == CHIP_FAMILY_RS300))
62
808 serge 63
 
812 serge 64
 
881 serge 65
        (info->ChipFamily == CHIP_FAMILY_RV350) ||  \
66
        (info->ChipFamily == CHIP_FAMILY_R350)  ||  \
67
        (info->ChipFamily == CHIP_FAMILY_RV380) ||  \
68
        (info->ChipFamily == CHIP_FAMILY_R420)  ||  \
69
        (info->ChipFamily == CHIP_FAMILY_RV410) ||  \
70
        (info->ChipFamily == CHIP_FAMILY_RS400) ||  \
71
        (info->ChipFamily == CHIP_FAMILY_RS480))
72
812 serge 73
 
881 serge 74
812 serge 75
 
881 serge 76
812 serge 77
 
881 serge 78
	(info->ChipFamily == CHIP_FAMILY_R520)   ||  \
79
	(info->ChipFamily == CHIP_FAMILY_RV530)  ||  \
80
	(info->ChipFamily == CHIP_FAMILY_R580)   ||  \
81
	(info->ChipFamily == CHIP_FAMILY_RV560)  ||  \
82
	(info->ChipFamily == CHIP_FAMILY_RV570))
83
808 serge 84
 
881 serge 85
	(info->ChipFamily == CHIP_FAMILY_RV350) ||  \
86
	(info->ChipFamily == CHIP_FAMILY_R350)  ||  \
87
	(info->ChipFamily == CHIP_FAMILY_RV380) ||  \
88
	(info->ChipFamily == CHIP_FAMILY_R420)  ||  \
89
	(info->ChipFamily == CHIP_FAMILY_RV410) ||  \
90
	(info->ChipFamily == CHIP_FAMILY_RS690) ||  \
91
	(info->ChipFamily == CHIP_FAMILY_RS600) ||  \
92
	(info->ChipFamily == CHIP_FAMILY_RS740) ||  \
93
	(info->ChipFamily == CHIP_FAMILY_RS400) ||  \
94
	(info->ChipFamily == CHIP_FAMILY_RS480))
95
96
 
97
 
98
 
99
	CARD_PCI,
100
	CARD_AGP,
101
	CARD_PCIE
102
} RADEONCardType;
103
104
 
105
 * Errata workarounds
106
 */
107
typedef enum {
108
       CHIP_ERRATA_R300_CG             = 0x00000001,
109
       CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
110
       CHIP_ERRATA_PLL_DELAY           = 0x00000004
111
} RADEONErrata;
112
113
 
114
{
115
    u32_t pci_device_id;
116
    RADEONChipFamily chip_family;
117
    int mobility;
118
    int igp;
119
    int nocrtc2;
120
    int nointtvout;
121
    int singledac;
122
} RADEONCardInfo;
123
124
 
125
 
126
 
808 serge 127
#define RHD_MMIO_BAR       2
128
129
 
130
#define RHD_MEM_FB         2
131
132
 
133
{
134
  u32_t            MMIOBase;
877 serge 135
  u32_t            MMIOMapSize;
136
808 serge 137
 
817 serge 138
 // u32_t            PhisBase;
881 serge 139
 // u32_t            FbIntAddress;       /* card internal address of FB */
140
 // u32_t            FbMapSize;
141
808 serge 142
 
877 serge 143
  u32_t            FbFreeSize;
144
808 serge 145
 
146
//  unsigned int      FbScanoutStart;
881 serge 147
//  unsigned int      FbScanoutSize;
148
808 serge 149
 
881 serge 150
812 serge 151
 
881 serge 152
  u32_t            mc_fb_location;
153
  u32_t            mc_agp_location;
154
  u32_t            mc_agp_location_hi;
155
808 serge 156
 
881 serge 157
808 serge 158
 
881 serge 159
  u32_t            BusCntl;
160
  unsigned long    FbMapSize;            /* Size of frame buffer, in bytes    */
161
  unsigned long    FbSecureSize;         /* Size of secured fb area at end of
162
                                            framebuffer */
163
164
 
165
 
166
  RADEONErrata     ChipErrata;
167
168
 
169
170
 
171
  int              IsMobility;
172
173
 
877 serge 174
  u32_t            devfn;
175
808 serge 176
 
881 serge 177
  u16_t            PciDeviceID;
877 serge 178
808 serge 179
 
877 serge 180
  u16_t            subdevice_id;
181
808 serge 182
 
881 serge 183
184
 
877 serge 185
  u32_t            ioBase[6];
186
  u32_t            memtype[6];
187
  u32_t            memsize[6];
188
808 serge 189
 
190
  struct mem_block  *gart_heap;
191
192
 
877 serge 193
  u32_t            displayHeight;
194
808 serge 195
 
881 serge 196
  int              __ymin;
197
  int              __xmax;
198
  int              __ymax;
199
808 serge 200
 
877 serge 201
  u32_t            dst_pitch_offset;
202
  u32_t            surface_cntl;
203
808 serge 204
 
881 serge 205
  u32_t            ring_rp;
206
  u32_t            ring_wp;
207
808 serge 208
 
881 serge 209
  Bool             IsDDR;
210
211
 
212
  int              has_tcl;
213
}RHD_t, *RHDPtr;
808 serge 214
215
 
216
217
 
218
 
815 serge 219
 
876 serge 220
#define R5XX_DP_BRUSH_FRGD_CLR            0x147c
221
#define R5XX_BRUSH_DATA0                  0x1480
222
#define R5XX_BRUSH_DATA1                  0x1484
223
815 serge 224
 
876 serge 225
#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
226
# define RADEON_GMC_BRUSH_SOLID_COLOR     (13 << 4)
227
# define RADEON_GMC_BRUSH_NONE            (15 << 4)
228
# define RADEON_GMC_DST_16BPP             (4 << 8)
229
# define RADEON_GMC_DST_24BPP             (5 << 8)
230
# define RADEON_GMC_DST_32BPP             (6 << 8)
231
# define RADEON_GMC_DST_DATATYPE_SHIFT     8
232
# define RADEON_GMC_SRC_DATATYPE_COLOR    (3 << 12)
233
# define RADEON_DP_SRC_SOURCE_MEMORY      (2 << 24)
234
# define RADEON_DP_SRC_SOURCE_HOST_DATA   (3 << 24)
235
# define RADEON_GMC_CLR_CMP_CNTL_DIS      (1 << 28)
236
# define RADEON_GMC_WR_MSK_DIS            (1 << 30)
237
# define RADEON_ROP3_S                 0x00cc0000
238
# define RADEON_ROP3_P                 0x00f00000
239
815 serge 240
 
876 serge 241
#define RADEON_CP_PACKET1              0x40000000
242
#define RADEON_CP_PACKET2              0x80000000
243
#define RADEON_CP_PACKET3              0xC0000000
244
245
 
246
# define RADEON_CNTL_BITBLT            0x00009200
247
# define RADEON_CNTL_TRANBLT           0x00009C00
248
249
 
250
# define RADEON_CNTL_PAINT_MULTI       0x00009A00
251
252
 
253
	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
254
255
 
256
	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
257
258
 
259
  (RADEON_CP_PACKET2)
260
261
 
262
	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
263
264
 
265
  ring = rhd.ring_base;                 \
266
  write = rhd.ring_wp;                  \
267
} while (0)
268
269
 
270
271
 
272
	ring[write++] = (x);						\
273
} while (0)
274
275
 
276
do {									\
277
    OUT_RING(CP_PACKET0(reg, 0));					\
278
    OUT_RING(val);							\
279
} while (0)
280
281
 
282
283
 
284
  rhd.ring_wp = write & 0x1FFF;                       \
285
  /* Flush writes to ring */                          \
286
  DRM_MEMORYBARRIER();                                \
287
  /*GET_RING_HEAD( dev_priv );          */            \
288
  OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp);            \
289
	/* read from PCI bus to ensure correct posting */		\
290
  INREG( RADEON_CP_RB_RPTR );                         \
291
} while (0)
292
293
 
294
 
295
 
808 serge 296
    int			token;		/* id of the token */
297
    const char *	name;		/* token name */
298
} SymTabRec, *SymTabPtr;
299
300
 
813 serge 301
 
302
 
303
OUTREG8(u16_t offset, u8_t value)
877 serge 304
{
813 serge 305
  *(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
877 serge 306
}
813 serge 307
308
 
309
 
877 serge 310
{
808 serge 311
  return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset));
877 serge 312
}
808 serge 313
314
 
315
 
881 serge 316
{
808 serge 317
  *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
877 serge 318
}
808 serge 319
320
 
881 serge 321
 
877 serge 322
{
808 serge 323
  return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset));
877 serge 324
}
808 serge 325
326
 
327
MASKREG(u16_t offset, u32_t value, u32_t mask)
877 serge 328
{
808 serge 329
  u32_t tmp;
877 serge 330
808 serge 331
 
332
  tmp &= ~mask;
333
  tmp |= (value & mask);
334
  OUTREG(offset, tmp);
335
};
336
337
 
338
_RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value)
877 serge 339
{
808 serge 340
  *(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value;
877 serge 341
}
808 serge 342
343
 
344
_RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask)
877 serge 345
{
808 serge 346
  u32_t tmp;
877 serge 347
808 serge 348
 
349
  tmp &= ~mask;
350
  tmp |= (value & mask);
351
  _RHDRegWrite(rhdPtr, offset, tmp);
352
};
353
354
 
355
#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value))
356
#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))
357
358
 
359
 
360
361
 
362
int rhdInitHeap(RHDPtr rhdPtr);
363
364
 
365
366
 
367
//  #define DBG(x)
368
369
 
370
typedef struct s_cursor
371
{
372
   u32_t   magic;                           // 'CURS'
877 serge 373
   void  (*destroy)(struct s_cursor*);    // destructor
808 serge 374
   u32_t   fd;                              // next object in list
877 serge 375
   u32_t   bk;                              // prev object in list
376
   u32_t   pid;                             // owner id
377
808 serge 378
 
379
   u32_t   hot_x;                           // hotspot coords
877 serge 380
   u32_t   hot_y;
381
}cursor_t;
808 serge 382
#pragma pack (pop)
383
384
 
385
#define LOAD_FROM_MEM    1
386
#define LOAD_INDIRECT    2
387
388
 
877 serge 389
void __stdcall copy_cursor(void *img, void *src);
808 serge 390
void destroy_cursor(cursor_t *cursor);
391
void __destroy_cursor(cursor_t *cursor);                // wrap
392
393
 
394
void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y);
395
void __stdcall r500_CursorRestore(int x, int y);
396
397
 
398
813 serge 399
 
400
 
401
    u32_t x ;
402
    u32_t y ;
403
} xPointFixed;
404
405
 
406
407
 
408
409
 
410
411
 
412
#define IntToxFixed(i)  ((xFixed) (i) << XFIXED_BITS)
413
414
 
415
416
 
417
					 ((type) << 16) | \
418
					 ((a) << 12) | \
419
					 ((r) << 8) | \
420
					 ((g) << 4) | \
421
					 ((b)))
422
423
 
424
#define PICT_FORMAT_RGB(f)  (((f)      ) & 0xfff)
425
426
 
427
#define PICT_TYPE_A     1
428
#define PICT_TYPE_ARGB	2
429
#define PICT_TYPE_ABGR	3
430
#define PICT_TYPE_COLOR	4
431
#define PICT_TYPE_GRAY	5
432
433
 
434
   PICT_a8r8g8b8 =	PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8),
435
   PICT_x8r8g8b8 =	PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8),
436
   PICT_a8b8g8r8 =	PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8),
437
   PICT_x8b8g8r8 =	PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8),
438
439
 
440
   PICT_r8g8b8 =	PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8),
441
   PICT_b8g8r8 =	PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8),
442
443
 
444
   PICT_r5g6b5 =	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5),
445
   PICT_b5g6r5 =	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5),
446
447
 
448
   PICT_x1r5g5b5 =	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5),
449
   PICT_a1b5g5r5 =	PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5),
450
   PICT_x1b5g5r5 =	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5),
451
   PICT_a4r4g4b4 =	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4),
452
   PICT_x4r4g4b4 =	PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4),
453
   PICT_a4b4g4r4 =	PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4),
454
   PICT_x4b4g4r4 =	PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4),
455
456
 
457
   PICT_a8 =		PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0),
458
   PICT_r3g3b2 =	PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2),
459
   PICT_b2g3r3 =	PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2),
460
   PICT_a2r2g2b2 =	PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2),
461
   PICT_a2b2g2r2 =	PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2),
462
463
 
464
   PICT_g8 =		PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
465
466
 
467
468
 
469
   PICT_x4g4 =		PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
470
471
 
472
   PICT_a4 =		PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0),
473
   PICT_r1g2b1 =	PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1),
474
   PICT_b1g2r1 =	PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1),
475
   PICT_a1r1g1b1 =	PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1),
476
   PICT_a1b1g1r1 =	PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1),
477
478
 
479
   PICT_g4 =		PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0),
480
481
 
482
   PICT_a1 =		PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0),
483
484
 
485
} PictFormatShort;
486
487
 
829 serge 488