Rev 881 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 811 | serge | 1 | |
| 2 | |||
| 3 | #define FINISH_ACCEL() COMMIT_RING() |
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| 4 | |||
| 5 | #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
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| 6 | |||
| 7 | #define RADEON_SWITCH_TO_3D() \ |
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| 8 | |||
| 813 | serge | 9 | u32_t wait_until = 0; \ |
| 10 | BEGIN_ACCEL(1); \ |
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| 11 | wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
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| 12 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
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| 13 | FINISH_ACCEL(); \ |
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| 14 | } while (0); |
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| 15 | |||
| 16 | |||
| 811 | serge | 17 | |
| 18 | |||
| 813 | serge | 19 | Bool src_alpha; |
| 20 | u32_t blend_cntl; |
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| 21 | }; |
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| 22 | |||
| 23 | static struct blendinfo RadeonBlendOp[] = { |
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| 24 | |||
| 25 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
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| 26 | /* 1 - Src */ |
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| 27 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
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| 28 | /* 2 - Dst */ |
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| 29 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
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| 30 | /* 3 - Over */ |
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| 31 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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| 32 | /* 4 - OverReverse */ |
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| 33 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
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| 34 | /* 5 - In */ |
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| 35 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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| 36 | /* 6 - InReverse */ |
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| 37 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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| 38 | /* 7 - Out */ |
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| 39 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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| 40 | /* 8 - OutReverse */ |
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| 41 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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| 42 | /* 9 - Atop */ |
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| 43 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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| 44 | /* 10- AtopReverse */ |
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| 45 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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| 46 | /* 11 - Xor */ |
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| 47 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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| 48 | /* 12 - Add */ |
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| 49 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
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| 50 | }; |
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| 51 | |||
| 52 | |||
| 53 | |||
| 54 | |||
| 811 | serge | 55 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
| 56 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
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| 57 | // ACCEL_PREAMBLE(); |
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| 58 | |||
| 59 | u32_t *ring, write; |
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| 60 | |||
| 877 | serge | 61 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
| 811 | serge | 62 | |
| 63 | if (IS_R300_3D || IS_R500_3D) |
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| 64 | |||
| 813 | serge | 65 | |
| 66 | BEGIN_ACCEL(3); |
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| 811 | serge | 67 | |
| 68 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 69 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 70 | FINISH_ACCEL(); |
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| 71 | |||
| 72 | if ( IS_R500_3D) |
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| 73 | |||
| 813 | serge | 74 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
| 75 | |||
| 76 | rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
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| 77 | |||
| 78 | } |
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| 79 | |||
| 80 | dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes ); |
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| 81 | |||
| 82 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
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| 83 | |||
| 811 | serge | 84 | switch(rhdPtr->num_gb_pipes) { |
| 85 | |||
| 86 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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| 87 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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| 88 | default: |
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| 89 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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| 90 | } |
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| 91 | |||
| 92 | BEGIN_ACCEL(5); |
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| 93 | |||
| 94 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 95 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
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| 96 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
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| 97 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
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| 98 | FINISH_ACCEL(); |
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| 99 | |||
| 100 | if (IS_R500_3D) { |
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| 101 | |||
| 102 | BEGIN_ACCEL(2); |
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| 103 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
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| 104 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
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| 105 | FINISH_ACCEL(); |
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| 106 | } |
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| 107 | |||
| 108 | BEGIN_ACCEL(3); |
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| 109 | |||
| 110 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 111 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 112 | FINISH_ACCEL(); |
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| 113 | |||
| 114 | BEGIN_ACCEL(5); |
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| 115 | |||
| 116 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 117 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 118 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
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| 119 | (8 << R300_MS_Y0_SHIFT) | |
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| 120 | (8 << R300_MS_X1_SHIFT) | |
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| 121 | (8 << R300_MS_Y1_SHIFT) | |
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| 122 | (8 << R300_MS_X2_SHIFT) | |
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| 123 | (8 << R300_MS_Y2_SHIFT) | |
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| 124 | (8 << R300_MSBD0_Y_SHIFT) | |
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| 125 | (7 << R300_MSBD0_X_SHIFT))); |
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| 126 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
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| 127 | (8 << R300_MS_Y3_SHIFT) | |
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| 128 | (8 << R300_MS_X4_SHIFT) | |
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| 129 | (8 << R300_MS_Y4_SHIFT) | |
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| 130 | (8 << R300_MS_X5_SHIFT) | |
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| 131 | (8 << R300_MS_Y5_SHIFT) | |
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| 132 | (8 << R300_MSBD1_SHIFT))); |
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| 133 | FINISH_ACCEL(); |
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| 134 | |||
| 135 | BEGIN_ACCEL(5); |
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| 136 | |||
| 137 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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| 138 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
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| 139 | R300_COLOR_ROUND_NEAREST)); |
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| 140 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
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| 141 | R300_ALPHA0_SHADING_GOURAUD | |
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| 142 | R300_RGB1_SHADING_GOURAUD | |
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| 143 | R300_ALPHA1_SHADING_GOURAUD | |
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| 144 | R300_RGB2_SHADING_GOURAUD | |
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| 145 | R300_ALPHA2_SHADING_GOURAUD | |
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| 146 | R300_RGB3_SHADING_GOURAUD | |
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| 147 | R300_ALPHA3_SHADING_GOURAUD)); |
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| 148 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
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| 149 | FINISH_ACCEL(); |
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| 150 | |||
| 151 | BEGIN_ACCEL(5); |
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| 152 | |||
| 153 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
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| 154 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
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| 155 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
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| 156 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
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| 157 | FINISH_ACCEL(); |
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| 158 | |||
| 159 | /* setup the VAP */ |
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| 160 | |||
| 161 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 162 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 163 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 164 | else |
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| 165 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 166 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 167 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 168 | |||
| 169 | if (rhdPtr->ChipSet == RHD_FAMILY_RV515) |
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| 170 | |||
| 812 | serge | 171 | else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
| 811 | serge | 172 | (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
| 812 | serge | 173 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
| 174 | else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
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| 811 | serge | 175 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
| 812 | serge | 176 | else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
| 811 | serge | 177 | (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
| 812 | serge | 178 | (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
| 179 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
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| 180 | else |
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| 811 | serge | 181 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
| 182 | |||
| 183 | if (rhdPtr->has_tcl) |
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| 184 | |||
| 185 | else |
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| 186 | BEGIN_ACCEL(9); |
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| 187 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
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| 188 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 189 | |||
| 190 | if (rhdPtr->has_tcl) |
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| 191 | |||
| 192 | else |
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| 193 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
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| 194 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
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| 195 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 196 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
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| 197 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
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| 198 | |||
| 199 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
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| 200 | |||
| 201 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
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| 202 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
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| 203 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
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| 204 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 205 | << R300_WRITE_ENA_0_SHIFT) | |
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| 206 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
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| 207 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
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| 208 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
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| 209 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
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| 210 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 211 | << R300_WRITE_ENA_1_SHIFT))); |
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| 212 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
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| 213 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
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| 214 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
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| 215 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
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| 216 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
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| 217 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 218 | << R300_WRITE_ENA_2_SHIFT))); |
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| 219 | |||
| 220 | if (rhdPtr->has_tcl) { |
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| 221 | |||
| 222 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
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| 223 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
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| 224 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
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| 225 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
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| 226 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
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| 227 | } |
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| 228 | FINISH_ACCEL(); |
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| 229 | |||
| 230 | /* pre-load the vertex shaders */ |
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| 231 | |||
| 232 | /* exa mask shader program */ |
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| 233 | BEGIN_ACCEL(13); |
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| 234 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
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| 235 | /* PVS inst 0 */ |
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| 236 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 237 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 238 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 239 | R300_PVS_DST_OFFSET(0) | |
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| 240 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 241 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 242 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 243 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 244 | R300_PVS_SRC_OFFSET(0) | |
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| 245 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 246 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 247 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 248 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 249 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 250 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 251 | R300_PVS_SRC_OFFSET(0) | |
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| 252 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 253 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 254 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 255 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 256 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 257 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 258 | R300_PVS_SRC_OFFSET(0) | |
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| 259 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 260 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 261 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 262 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 263 | |||
| 264 | /* PVS inst 1 */ |
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| 265 | |||
| 266 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 267 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 268 | R300_PVS_DST_OFFSET(1) | |
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| 269 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 270 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 271 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 272 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 273 | R300_PVS_SRC_OFFSET(6) | |
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| 274 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 275 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 276 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 277 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 278 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 279 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 280 | R300_PVS_SRC_OFFSET(6) | |
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| 281 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 282 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 283 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 284 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 285 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 286 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 287 | R300_PVS_SRC_OFFSET(6) | |
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| 288 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 289 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 290 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 291 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 292 | |||
| 293 | /* PVS inst 2 */ |
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| 294 | |||
| 295 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 296 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 297 | R300_PVS_DST_OFFSET(2) | |
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| 298 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 299 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 300 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 301 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 302 | R300_PVS_SRC_OFFSET(7) | |
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| 303 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 304 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 305 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 306 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 307 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 308 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 309 | R300_PVS_SRC_OFFSET(7) | |
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| 310 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 311 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 312 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 313 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 314 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 315 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 316 | R300_PVS_SRC_OFFSET(7) | |
||
| 317 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 318 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 319 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 320 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 321 | FINISH_ACCEL(); |
||
| 322 | |||
| 323 | BEGIN_ACCEL(9); |
||
| 324 | |||
| 325 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
||
| 326 | /* PVS inst 0 */ |
||
| 327 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 328 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 329 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 330 | R300_PVS_DST_OFFSET(0) | |
||
| 331 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 332 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 333 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 334 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 335 | R300_PVS_SRC_OFFSET(0) | |
||
| 336 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 337 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 338 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 339 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 340 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 341 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 342 | R300_PVS_SRC_OFFSET(0) | |
||
| 343 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 344 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 345 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 346 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 347 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 348 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 349 | R300_PVS_SRC_OFFSET(0) | |
||
| 350 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 351 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 352 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 353 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 354 | |||
| 355 | /* PVS inst 1 */ |
||
| 356 | |||
| 357 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 358 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 359 | R300_PVS_DST_OFFSET(1) | |
||
| 360 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 361 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 362 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 363 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 364 | R300_PVS_SRC_OFFSET(6) | |
||
| 365 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 366 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 367 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 368 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 369 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 370 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 371 | R300_PVS_SRC_OFFSET(6) | |
||
| 372 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 373 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 374 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 375 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 376 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 377 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 378 | R300_PVS_SRC_OFFSET(6) | |
||
| 379 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 380 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 381 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 382 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 383 | FINISH_ACCEL(); |
||
| 384 | |||
| 385 | /* Xv shader program */ |
||
| 386 | |||
| 387 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
||
| 388 | |||
| 389 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 390 | |||
| 391 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 392 | R300_PVS_DST_OFFSET(0) | |
||
| 393 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 394 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 395 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 396 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 397 | R300_PVS_SRC_OFFSET(0) | |
||
| 398 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 399 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 400 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 401 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 402 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 403 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 404 | R300_PVS_SRC_OFFSET(0) | |
||
| 405 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 406 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 407 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 408 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 409 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 410 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 411 | R300_PVS_SRC_OFFSET(0) | |
||
| 412 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 413 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 414 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 415 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 416 | |||
| 417 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 418 | |||
| 419 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 420 | R300_PVS_DST_OFFSET(1) | |
||
| 421 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 422 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 423 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 424 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 425 | R300_PVS_SRC_OFFSET(6) | |
||
| 426 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 427 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 428 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 429 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 430 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 431 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 432 | R300_PVS_SRC_OFFSET(6) | |
||
| 433 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 434 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 435 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 436 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 437 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 438 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 439 | R300_PVS_SRC_OFFSET(6) | |
||
| 440 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 441 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 442 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 443 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 444 | FINISH_ACCEL(); |
||
| 445 | } |
||
| 446 | |||
| 447 | /* pre-load the RS instructions */ |
||
| 448 | |||
| 449 | if (IS_R300_3D) { |
||
| 450 | /* rasterizer source table |
||
| 451 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 452 | * 0,1 are tex0 |
||
| 453 | * 2,3 are tex1 |
||
| 454 | */ |
||
| 455 | OUT_ACCEL_REG(R300_RS_IP_0, |
||
| 456 | (R300_RS_TEX_PTR(0) | |
||
| 457 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 458 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 459 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 460 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 461 | OUT_ACCEL_REG(R300_RS_IP_1, |
||
| 462 | (R300_RS_TEX_PTR(2) | |
||
| 463 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 464 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 465 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 466 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 467 | /* src tex */ |
||
| 468 | /* R300_INST_TEX_ID - select the RS source table entry |
||
| 469 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
||
| 470 | */ |
||
| 471 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
||
| 472 | R300_RS_INST_TEX_CN_WRITE | |
||
| 473 | R300_INST_TEX_ADDR(0))); |
||
| 474 | /* mask tex */ |
||
| 475 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
||
| 476 | R300_RS_INST_TEX_CN_WRITE | |
||
| 477 | R300_INST_TEX_ADDR(1))); |
||
| 478 | |||
| 479 | } else { |
||
| 480 | |||
| 481 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 482 | * 0,1 are tex0 |
||
| 483 | * 2,3 are tex1 |
||
| 484 | */ |
||
| 485 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
| 486 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
| 487 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 488 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 489 | |||
| 490 | OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
| 491 | |||
| 492 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 493 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 494 | /* src tex */ |
||
| 495 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
||
| 496 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
||
| 497 | */ |
||
| 498 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 499 | R500_RS_INST_TEX_CN_WRITE | |
||
| 500 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 501 | /* mask tex */ |
||
| 502 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 503 | R500_RS_INST_TEX_CN_WRITE | |
||
| 504 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 505 | } |
||
| 506 | FINISH_ACCEL(); |
||
| 507 | |||
| 508 | /* pre-load FS tex instructions */ |
||
| 509 | |||
| 510 | BEGIN_ACCEL(2); |
||
| 511 | /* tex inst for src texture */ |
||
| 512 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
||
| 513 | (R300_TEX_SRC_ADDR(0) | |
||
| 514 | R300_TEX_DST_ADDR(0) | |
||
| 515 | R300_TEX_ID(0) | |
||
| 516 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 517 | |||
| 518 | /* tex inst for mask texture */ |
||
| 519 | |||
| 520 | (R300_TEX_SRC_ADDR(1) | |
||
| 521 | R300_TEX_DST_ADDR(1) | |
||
| 522 | R300_TEX_ID(1) | |
||
| 523 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 524 | FINISH_ACCEL(); |
||
| 525 | } |
||
| 526 | |||
| 527 | if (IS_R300_3D) { |
||
| 528 | |||
| 529 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
||
| 530 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 531 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
||
| 532 | (R300_ALU_START(0) | |
||
| 533 | R300_ALU_SIZE(0) | |
||
| 534 | R300_TEX_START(0) | |
||
| 535 | R300_TEX_SIZE(0))); |
||
| 536 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
||
| 537 | (R300_ALU_START(0) | |
||
| 538 | R300_ALU_SIZE(0) | |
||
| 539 | R300_TEX_START(0) | |
||
| 540 | R300_TEX_SIZE(0))); |
||
| 541 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
||
| 542 | (R300_ALU_START(0) | |
||
| 543 | R300_ALU_SIZE(0) | |
||
| 544 | R300_TEX_START(0) | |
||
| 545 | R300_TEX_SIZE(0))); |
||
| 546 | } else { |
||
| 547 | BEGIN_ACCEL(7); |
||
| 548 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
||
| 549 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 550 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
||
| 551 | } |
||
| 552 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
||
| 553 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
||
| 554 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 555 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 556 | R300_OUT_FMT_C2_SEL_RED | |
||
| 557 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 558 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
||
| 559 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 560 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 561 | R300_OUT_FMT_C2_SEL_RED | |
||
| 562 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 563 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
||
| 564 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 565 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 566 | R300_OUT_FMT_C2_SEL_RED | |
||
| 567 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 568 | FINISH_ACCEL(); |
||
| 569 | |||
| 570 | |||
| 571 | |||
| 572 | |||
| 573 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
||
| 574 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
||
| 575 | FINISH_ACCEL(); |
||
| 576 | |||
| 577 | BEGIN_ACCEL(13); |
||
| 578 | |||
| 579 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
||
| 580 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
||
| 581 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
||
| 582 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
||
| 583 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
||
| 584 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
||
| 585 | |||
| 586 | OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
||
| 587 | |||
| 588 | R300_GREEN_MASK_EN | |
||
| 589 | R300_RED_MASK_EN | |
||
| 590 | R300_ALPHA_MASK_EN)); |
||
| 591 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 592 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
||
| 593 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
||
| 594 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 595 | FINISH_ACCEL(); |
||
| 596 | |||
| 597 | BEGIN_ACCEL(7); |
||
| 598 | |||
| 599 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
||
| 600 | (0 << R300_SCISSOR_Y_SHIFT))); |
||
| 601 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
||
| 602 | (8191 << R300_SCISSOR_Y_SHIFT))); |
||
| 603 | |||
| 604 | if (IS_R300_3D) { |
||
| 605 | |||
| 606 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
||
| 607 | (1088 << R300_CLIP_Y_SHIFT))); |
||
| 608 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
||
| 609 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
||
| 610 | } else { |
||
| 611 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
||
| 612 | (0 << R300_CLIP_Y_SHIFT))); |
||
| 613 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
||
| 614 | (4080 << R300_CLIP_Y_SHIFT))); |
||
| 615 | } |
||
| 616 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
| 617 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
||
| 618 | FINISH_ACCEL(); |
||
| 619 | } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
||
| 620 | (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
||
| 812 | serge | 621 | (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
| 622 | (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
||
| 623 | |||
| 624 | BEGIN_ACCEL(7); |
||
| 811 | serge | 625 | |
| 626 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
| 812 | serge | 627 | } else { |
| 811 | serge | 628 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
| 629 | } |
||
| 630 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
||
| 631 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
||
| 632 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
||
| 633 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
||
| 634 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
||
| 635 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
||
| 636 | R200_VAP_VF_MAX_VTX_NUM); |
||
| 637 | FINISH_ACCEL(); |
||
| 638 | |||
| 639 | BEGIN_ACCEL(5); |
||
| 640 | |||
| 641 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 642 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 643 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 644 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 645 | RADEON_BFACE_SOLID | |
||
| 646 | RADEON_FFACE_SOLID | |
||
| 647 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 648 | RADEON_ROUND_MODE_ROUND | |
||
| 649 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 650 | FINISH_ACCEL(); |
||
| 651 | } else { |
||
| 652 | BEGIN_ACCEL(2); |
||
| 653 | if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
||
| 654 | (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
||
| 812 | serge | 655 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
| 656 | else |
||
| 811 | serge | 657 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
| 658 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
||
| 659 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
||
| 660 | RADEON_VTX_ST0_NONPARAMETRIC | |
||
| 661 | RADEON_VTX_ST1_NONPARAMETRIC | |
||
| 662 | RADEON_TEX1_W_ROUTING_USE_W0); |
||
| 663 | FINISH_ACCEL(); |
||
| 664 | |||
| 665 | BEGIN_ACCEL(5); |
||
| 666 | |||
| 667 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 668 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 669 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 670 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 671 | RADEON_BFACE_SOLID | |
||
| 672 | RADEON_FFACE_SOLID | |
||
| 673 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 674 | RADEON_ROUND_MODE_ROUND | |
||
| 675 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 676 | FINISH_ACCEL(); |
||
| 677 | } |
||
| 678 | |||
| 679 | } |
||
| 680 | |||
| 681 | static Bool R300TextureSetup(int w, int h, int unit) |
||
| 682 | |||
| 813 | serge | 683 | //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
| 684 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
||
| 685 | // int w = pPict->pDrawable->width; |
||
| 686 | // int h = pPict->pDrawable->height; |
||
| 687 | int i, pixel_shift; |
||
| 688 | |||
| 689 | //ACCEL_PREAMBLE(); |
||
| 811 | serge | 690 | |
| 813 | serge | 691 | //TRACE; |
| 811 | serge | 692 | |
| 813 | serge | 693 | //txpitch = exaGetPixmapPitch(pPix); |
| 694 | |||
| 695 | |||
| 696 | // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; |
||
| 697 | |||
| 698 | |||
| 699 | if ((txoffset & 0x1f) != 0) |
||
| 700 | |||
| 701 | if ((txpitch & 0x1f) != 0) |
||
| 702 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
||
| 703 | |||
| 704 | /* TXPITCH = pixels (texels) per line - 1 */ |
||
| 705 | |||
| 706 | txpitch >>= pixel_shift; |
||
| 707 | txpitch -= 1; |
||
| 708 | |||
| 709 | // if (RADEONPixmapIsColortiled(pPix)) |
||
| 710 | |||
| 711 | |||
| 712 | // for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) |
||
| 713 | |||
| 714 | // if (R300TexFormats[i].fmt == pPict->format) |
||
| 715 | // break; |
||
| 716 | // } |
||
| 717 | |||
| 718 | //txformat1 = R300TexFormats[i].card_fmt; |
||
| 719 | |||
| 720 | |||
| 721 | txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
||
| 722 | |||
| 723 | |||
| 724 | if (IS_R500_3D && ((w - 1) & 0x800)) |
||
| 725 | |||
| 726 | |||
| 727 | if (IS_R500_3D && ((h - 1) & 0x800)) |
||
| 728 | |||
| 729 | |||
| 730 | /* Use TXPITCH instead of TXWIDTH for address computations: we could |
||
| 731 | |||
| 732 | * in doing so. |
||
| 733 | */ |
||
| 734 | txformat0 |= R300_TXPITCH_EN; |
||
| 735 | |||
| 736 | // info->texW[unit] = w; |
||
| 737 | |||
| 738 | |||
| 739 | // if (pPict->repeat && !(unit == 0 && need_src_tile_x)) |
||
| 740 | |||
| 741 | // else |
||
| 742 | txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
||
| 743 | |||
| 744 | // if (pPict->repeat && !(unit == 0 && need_src_tile_y)) |
||
| 745 | |||
| 746 | // else |
||
| 747 | txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
||
| 748 | |||
| 749 | txfilter |= (unit << R300_TX_ID_SHIFT); |
||
| 750 | |||
| 751 | // switch (pPict->filter) { |
||
| 752 | |||
| 753 | txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
||
| 754 | // break; |
||
| 755 | // case PictFilterBilinear: |
||
| 756 | // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
||
| 757 | // break; |
||
| 758 | // default: |
||
| 759 | // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
||
| 760 | // } |
||
| 761 | |||
| 762 | { |
||
| 763 | |||
| 764 | |||
| 765 | BEGIN_ACCEL(7); |
||
| 766 | |||
| 767 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
||
| 768 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
||
| 769 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
||
| 770 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
||
| 771 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
||
| 772 | // if (!pPict->repeat) |
||
| 773 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
||
| 774 | FINISH_ACCEL(); |
||
| 775 | } |
||
| 776 | // if (pPict->transform != 0) { |
||
| 777 | // is_transform[unit] = TRUE; |
||
| 778 | // transform[unit] = pPict->transform; |
||
| 779 | // } else { |
||
| 780 | // is_transform[unit] = FALSE; |
||
| 781 | // } |
||
| 782 | |||
| 783 | return TRUE; |
||
| 784 | |||
| 785 | |||
| 786 | static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
||
| 787 | |||
| 788 | u32_t sblend, dblend; |
||
| 789 | |||
| 790 | sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; |
||
| 791 | |||
| 792 | |||
| 793 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
||
| 794 | |||
| 795 | */ |
||
| 796 | if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
||
| 797 | if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
||
| 798 | sblend = RADEON_SRC_BLEND_GL_ONE; |
||
| 799 | else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
||
| 800 | sblend = RADEON_SRC_BLEND_GL_ZERO; |
||
| 801 | } |
||
| 802 | |||
| 803 | return sblend | dblend; |
||
| 804 | |||
| 805 | |||
| 806 | |||
| 807 | |||
| 885 | serge | 808 | |
| 813 | serge | 809 | int w, int h) |
| 810 | { |
||
| 811 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
||
| 812 | u32_t dst_format, dst_offset, dst_pitch; |
||
| 813 | u32_t txenable, colorpitch; |
||
| 814 | u32_t blendcntl; |
||
| 815 | int pixel_shift; |
||
| 816 | u32_t *ring, write; |
||
| 817 | |||
| 818 | //ACCEL_PREAMBLE(); |
||
| 819 | |||
| 820 | //TRACE; |
||
| 821 | |||
| 822 | //if (!info->XInited3D) |
||
| 823 | |||
| 824 | |||
| 825 | //if (!R300GetDestFormat(pDstPicture, &dst_format)) |
||
| 826 | |||
| 827 | dst_format = R300_COLORFORMAT_ARGB8888; |
||
| 828 | |||
| 829 | pixel_shift = 32 >> 4; |
||
| 830 | |||
| 831 | //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; |
||
| 832 | |||
| 833 | |||
| 834 | //dst_pitch = exaGetPixmapPitch(pDst); |
||
| 835 | |||
| 836 | colorpitch = dst_pitch >> pixel_shift; |
||
| 837 | |||
| 838 | // if (RADEONPixmapIsColortiled(pDst)) |
||
| 839 | |||
| 840 | |||
| 841 | colorpitch |= dst_format; |
||
| 842 | |||
| 843 | if ((dst_offset & 0x0f) != 0) |
||
| 844 | |||
| 845 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
||
| 846 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
||
| 847 | |||
| 848 | // if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) |
||
| 849 | |||
| 850 | |||
| 851 | if (!R300TextureSetup(w, h, 0)) |
||
| 852 | |||
| 853 | |||
| 854 | txenable = R300_TEX_0_ENABLE; |
||
| 855 | |||
| 856 | // RADEON_SWITCH_TO_3D(); |
||
| 857 | |||
| 858 | /* setup the VAP */ |
||
| 859 | |||
| 860 | |||
| 861 | /* These registers define the number, type, and location of data submitted |
||
| 862 | |||
| 863 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
||
| 864 | * enabled. This memory provides the imputs to the vertex shader program |
||
| 865 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
||
| 866 | * directly to the GA input memory and the order is signifigant. In |
||
| 867 | * PVS_BYPASS mode the order is as follows: |
||
| 868 | * Position |
||
| 869 | * Point Size |
||
| 870 | * Color 0-3 |
||
| 871 | * Textures 0-7 |
||
| 872 | * Fog |
||
| 873 | */ |
||
| 874 | |||
| 875 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
||
| 876 | |||
| 877 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
||
| 878 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
||
| 879 | R300_SIGNED_0 | |
||
| 880 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
||
| 881 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
||
| 882 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
||
| 883 | R300_LAST_VEC_1 | |
||
| 884 | R300_SIGNED_1)); |
||
| 885 | |||
| 886 | /* load the vertex shader |
||
| 887 | |||
| 888 | * - exa no mask |
||
| 889 | * - exa mask |
||
| 890 | * - Xv |
||
| 891 | * Here we select the offset of the vertex program we want to use |
||
| 892 | */ |
||
| 893 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
||
| 894 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
||
| 895 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
||
| 896 | (4 << R300_PVS_LAST_INST_SHIFT))); |
||
| 897 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
||
| 898 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
||
| 899 | |||
| 900 | /* Position and one or two sets of 2 texture coordinates */ |
||
| 901 | |||
| 902 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
||
| 903 | |||
| 904 | OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
||
| 905 | |||
| 906 | FINISH_ACCEL(); |
||
| 907 | |||
| 908 | /* setup pixel shader */ |
||
| 909 | |||
| 910 | } else { |
||
| 911 | u32_t output_fmt; |
||
| 912 | u32_t src_color, src_alpha; |
||
| 913 | u32_t mask_color, mask_alpha; |
||
| 914 | |||
| 915 | if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0) |
||
| 916 | |||
| 917 | R500_ALU_RGB_G_SWIZ_A_0 | |
||
| 918 | R500_ALU_RGB_B_SWIZ_A_0); |
||
| 919 | else |
||
| 920 | src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
||
| 921 | R500_ALU_RGB_G_SWIZ_A_G | |
||
| 922 | R500_ALU_RGB_B_SWIZ_A_B); |
||
| 923 | |||
| 924 | if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0) |
||
| 925 | |||
| 926 | else |
||
| 927 | src_alpha = R500_ALPHA_SWIZ_A_A; |
||
| 928 | |||
| 929 | mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
||
| 930 | |||
| 931 | R500_ALU_RGB_B_SWIZ_B_1); |
||
| 932 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
||
| 933 | |||
| 934 | /* shader output swizzling */ |
||
| 935 | |||
| 936 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 937 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 938 | R300_OUT_FMT_C2_SEL_RED | |
||
| 939 | R300_OUT_FMT_C3_SEL_ALPHA); |
||
| 940 | |||
| 941 | BEGIN_ACCEL(6); |
||
| 942 | |||
| 943 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
||
| 944 | R300_RS_COUNT_HIRES_EN)); |
||
| 945 | |||
| 946 | OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
||
| 947 | |||
| 948 | OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
||
| 949 | |||
| 950 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
||
| 951 | R500_US_CODE_RANGE_SIZE(1))); |
||
| 952 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
||
| 953 | |||
| 954 | OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
||
| 955 | |||
| 956 | |||
| 957 | BEGIN_ACCEL(13); |
||
| 958 | |||
| 959 | /* tex inst for src texture */ |
||
| 960 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
||
| 961 | R500_INST_TEX_SEM_WAIT | |
||
| 962 | R500_INST_RGB_WMASK_R | |
||
| 963 | R500_INST_RGB_WMASK_G | |
||
| 964 | R500_INST_RGB_WMASK_B | |
||
| 965 | R500_INST_ALPHA_WMASK | |
||
| 966 | R500_INST_RGB_CLAMP | |
||
| 967 | R500_INST_ALPHA_CLAMP)); |
||
| 968 | |||
| 969 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
||
| 970 | |||
| 971 | R500_TEX_SEM_ACQUIRE | |
||
| 972 | R500_TEX_IGNORE_UNCOVERED)); |
||
| 973 | |||
| 974 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
||
| 975 | |||
| 976 | R500_TEX_SRC_T_SWIZ_G | |
||
| 977 | R500_TEX_DST_ADDR(0) | |
||
| 978 | R500_TEX_DST_R_SWIZ_R | |
||
| 979 | R500_TEX_DST_G_SWIZ_G | |
||
| 980 | R500_TEX_DST_B_SWIZ_B | |
||
| 981 | R500_TEX_DST_A_SWIZ_A)); |
||
| 982 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
||
| 983 | R500_DX_S_SWIZ_R | |
||
| 984 | R500_DX_T_SWIZ_R | |
||
| 985 | R500_DX_R_SWIZ_R | |
||
| 986 | R500_DX_Q_SWIZ_R | |
||
| 987 | R500_DY_ADDR(0) | |
||
| 988 | R500_DY_S_SWIZ_R | |
||
| 989 | R500_DY_T_SWIZ_R | |
||
| 990 | R500_DY_R_SWIZ_R | |
||
| 991 | R500_DY_Q_SWIZ_R)); |
||
| 992 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
||
| 993 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
||
| 994 | |||
| 995 | /* ALU inst */ |
||
| 996 | |||
| 997 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
||
| 998 | R500_INST_TEX_SEM_WAIT | |
||
| 999 | R500_INST_LAST | |
||
| 1000 | R500_INST_RGB_OMASK_R | |
||
| 1001 | R500_INST_RGB_OMASK_G | |
||
| 1002 | R500_INST_RGB_OMASK_B | |
||
| 1003 | R500_INST_ALPHA_OMASK | |
||
| 1004 | R500_INST_RGB_CLAMP | |
||
| 1005 | R500_INST_ALPHA_CLAMP)); |
||
| 1006 | /* ALU inst |
||
| 1007 | * temp addresses for texture inputs |
||
| 1008 | * RGB_ADDR0 is src tex (temp 0) |
||
| 1009 | * RGB_ADDR1 is mask tex (temp 1) |
||
| 1010 | */ |
||
| 1011 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
||
| 1012 | R500_RGB_ADDR1(1) | |
||
| 1013 | R500_RGB_ADDR2(0))); |
||
| 1014 | /* ALU inst |
||
| 1015 | * temp addresses for texture inputs |
||
| 1016 | * ALPHA_ADDR0 is src tex (temp 0) |
||
| 1017 | * ALPHA_ADDR1 is mask tex (temp 1) |
||
| 1018 | */ |
||
| 1019 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
||
| 1020 | R500_ALPHA_ADDR1(1) | |
||
| 1021 | R500_ALPHA_ADDR2(0))); |
||
| 1022 | |||
| 1023 | /* R500_ALU_RGB_TARGET - RGB render target */ |
||
| 1024 | |||
| 1025 | src_color | |
||
| 1026 | R500_ALU_RGB_SEL_B_SRC1 | |
||
| 1027 | mask_color | |
||
| 1028 | R500_ALU_RGB_TARGET(0))); |
||
| 1029 | |||
| 1030 | /* R500_ALPHA_RGB_TARGET - alpha render target */ |
||
| 1031 | |||
| 1032 | R500_ALPHA_ADDRD(0) | |
||
| 1033 | R500_ALPHA_SEL_A_SRC0 | |
||
| 1034 | src_alpha | |
||
| 1035 | R500_ALPHA_SEL_B_SRC1 | |
||
| 1036 | mask_alpha | |
||
| 1037 | R500_ALPHA_TARGET(0))); |
||
| 1038 | |||
| 1039 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
||
| 1040 | |||
| 1041 | R500_ALU_RGBA_R_SWIZ_0 | |
||
| 1042 | R500_ALU_RGBA_G_SWIZ_0 | |
||
| 1043 | R500_ALU_RGBA_B_SWIZ_0 | |
||
| 1044 | R500_ALU_RGBA_A_SWIZ_0)); |
||
| 1045 | FINISH_ACCEL(); |
||
| 1046 | } |
||
| 1047 | |||
| 1048 | BEGIN_ACCEL(3); |
||
| 1049 | |||
| 1050 | OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
||
| 1051 | |||
| 1052 | |||
| 1053 | blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
||
| 1054 | |||
| 1055 | |||
| 1056 | FINISH_ACCEL(); |
||
| 1057 | |||
| 1058 | return TRUE; |
||
| 1059 | |||
| 1060 | |||
| 1061 | |||
| 1062 | |||
| 1063 | |||
| 1064 | |||
| 1065 | |||
| 1066 | |||
| 1067 | |||
| 1068 | |||
| 1069 | |||
| 1070 | |||
| 1071 | int w, int h) |
||
| 1072 | { |
||
| 1073 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
||
| 1074 | int vtx_count; |
||
| 1075 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
||
| 1076 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
||
| 1077 | |||
| 1078 | u32_t *ring, write; |
||
| 1079 | |||
| 877 | serge | 1080 | |
| 813 | serge | 1081 | |
| 1082 | |||
| 1083 | // ENTER_DRAW(0); |
||
| 1084 | |||
| 1085 | /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", |
||
| 1086 | |||
| 1087 | |||
| 1088 | srcTopLeft.x = IntToxFixed(srcX); |
||
| 1089 | |||
| 1090 | srcTopRight.x = IntToxFixed(srcX + w); |
||
| 1091 | srcTopRight.y = IntToxFixed(srcY); |
||
| 1092 | srcBottomLeft.x = IntToxFixed(srcX); |
||
| 1093 | srcBottomLeft.y = IntToxFixed(srcY + h); |
||
| 1094 | srcBottomRight.x = IntToxFixed(srcX + w); |
||
| 1095 | srcBottomRight.y = IntToxFixed(srcY + h); |
||
| 1096 | |||
| 1097 | /* |
||
| 1098 | |||
| 1099 | transformPoint(transform[0], &srcTopLeft); |
||
| 1100 | transformPoint(transform[0], &srcTopRight); |
||
| 1101 | transformPoint(transform[0], &srcBottomLeft); |
||
| 1102 | transformPoint(transform[0], &srcBottomRight); |
||
| 1103 | } |
||
| 1104 | if (is_transform[1]) { |
||
| 1105 | transformPoint(transform[1], &maskTopLeft); |
||
| 1106 | transformPoint(transform[1], &maskTopRight); |
||
| 1107 | transformPoint(transform[1], &maskBottomLeft); |
||
| 1108 | transformPoint(transform[1], &maskBottomRight); |
||
| 1109 | } |
||
| 1110 | */ |
||
| 1111 | vtx_count = VTX_COUNT; |
||
| 1112 | |||
| 1113 | BEGIN_ACCEL(1); |
||
| 1114 | |||
| 1115 | FINISH_ACCEL(); |
||
| 1116 | |||
| 1117 | BEGIN_RING(4 * vtx_count + 4); |
||
| 1118 | |||
| 1119 | OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
||
| 1120 | |||
| 1121 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
||
| 1122 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
||
| 1123 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
||
| 1124 | |||
| 1125 | |||
| 1126 | |||
| 1127 | |||
| 1128 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
||
| 1129 | |||
| 1130 | VTX_OUT((float)dstX, (float)(dstY + h), |
||
| 1131 | |||
| 1132 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
||
| 1133 | |||
| 1134 | VTX_OUT((float)(dstX + w), (float)(dstY + h), |
||
| 1135 | |||
| 1136 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
||
| 1137 | |||
| 1138 | VTX_OUT((float)(dstX + w), (float)dstY, |
||
| 1139 | |||
| 1140 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
||
| 1141 | |||
| 1142 | /* flushing is pipelined, free/finish is not */ |
||
| 1143 | |||
| 1144 | |||
| 1145 | // OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
||
| 1146 | |||
| 1147 | COMMIT_RING(); |
||
| 1148 | |||
| 1149 | // LEAVE_DRAW(0); |
||
| 1150 | |||
| 1151 | #undef VTX_OUT |
||
| 1152 | #undef VTX_OUT_MASK |
||
| 1153 | |||
| 1154 | #if 0 |
||
| 1155 | |||
| 879 | serge | 1156 | int RadeonComposite( blit_t *blit) |
| 813 | serge | 1157 | |
| 1158 | int tileSrcY, tileMaskY, tileDstY; |
||
| 1159 | int remainingHeight; |
||
| 1160 | |||
| 1161 | R300PrepareComposite(3, blit->src_x, blit->src_y, |
||
| 1162 | |||
| 1163 | blit->w, blit->h); |
||
| 1164 | |||
| 1165 | // if (!need_src_tile_x && !need_src_tile_y) { |
||
| 1166 | |||
| 1167 | blit->dst_x, blit->dst_y, |
||
| 1168 | blit->w, blit->h); |
||
| 1169 | return 0; |
||
| 1170 | // } |
||
| 1171 | |||
| 1172 | /* Tiling logic borrowed from exaFillRegionTiled */ |
||
| 1173 | |||
| 1174 | #if 0 |
||
| 1175 | |||
| 1176 | tileMaskY = maskY; |
||
| 1177 | tileDstY = dstY; |
||
| 1178 | |||
| 1179 | remainingHeight = height; |
||
| 1180 | |||
| 1181 | int remainingWidth = width; |
||
| 1182 | int tileSrcX, tileMaskX, tileDstX; |
||
| 1183 | int h = src_tile_height - tileSrcY; |
||
| 1184 | |||
| 1185 | if (h > remainingHeight) |
||
| 1186 | |||
| 1187 | remainingHeight -= h; |
||
| 1188 | |||
| 1189 | modulus(srcX, src_tile_width, tileSrcX); |
||
| 1190 | |||
| 1191 | tileDstX = dstX; |
||
| 1192 | |||
| 1193 | while (remainingWidth > 0) { |
||
| 1194 | |||
| 1195 | if (w > remainingWidth) |
||
| 1196 | w = remainingWidth; |
||
| 1197 | remainingWidth -= w; |
||
| 1198 | |||
| 1199 | FUNC_NAME(RadeonCompositeTile)(pDst, |
||
| 1200 | |||
| 1201 | tileMaskX, tileMaskY, |
||
| 1202 | tileDstX, tileDstY, |
||
| 1203 | w, h); |
||
| 1204 | |||
| 1205 | tileSrcX = 0; |
||
| 1206 | |||
| 1207 | tileDstX += w; |
||
| 1208 | } |
||
| 1209 | tileSrcY = 0; |
||
| 1210 | tileMaskY += h; |
||
| 1211 | tileDstY += h; |
||
| 1212 | } |
||
| 1213 | #endif |
||
| 1214 | } |
||
| 1215 | |||
| 1216 | #endif |
||
| 1217 |