Rev 811 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 811 | serge | 1 | |
| 2 | |||
| 3 | |||
| 4 | //#define FINISH_ACCEL() ADVANCE_RING() |
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| 5 | #define FINISH_ACCEL() COMMIT_RING() |
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| 6 | |||
| 7 | |||
| 8 | |||
| 9 | |||
| 10 | #define IS_R500_3D 1 |
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| 11 | |||
| 12 | |||
| 13 | |||
| 14 | { |
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| 15 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
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| 16 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
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| 17 | // ACCEL_PREAMBLE(); |
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| 18 | |||
| 19 | |||
| 20 | |||
| 21 | |||
| 22 | |||
| 23 | |||
| 24 | |||
| 25 | |||
| 26 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 27 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 28 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 29 | FINISH_ACCEL(); |
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| 30 | |||
| 31 | |||
| 32 | |||
| 33 | |||
| 34 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
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| 35 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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| 36 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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| 37 | default: |
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| 38 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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| 39 | } |
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| 40 | |||
| 41 | |||
| 42 | OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
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| 43 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 44 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
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| 45 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
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| 46 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
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| 47 | FINISH_ACCEL(); |
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| 48 | |||
| 49 | |||
| 50 | su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
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| 51 | BEGIN_ACCEL(2); |
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| 52 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
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| 53 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
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| 54 | FINISH_ACCEL(); |
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| 55 | } |
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| 56 | |||
| 57 | |||
| 58 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 59 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 60 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 61 | FINISH_ACCEL(); |
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| 62 | |||
| 63 | |||
| 64 | OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
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| 65 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 66 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 67 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
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| 68 | (8 << R300_MS_Y0_SHIFT) | |
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| 69 | (8 << R300_MS_X1_SHIFT) | |
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| 70 | (8 << R300_MS_Y1_SHIFT) | |
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| 71 | (8 << R300_MS_X2_SHIFT) | |
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| 72 | (8 << R300_MS_Y2_SHIFT) | |
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| 73 | (8 << R300_MSBD0_Y_SHIFT) | |
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| 74 | (7 << R300_MSBD0_X_SHIFT))); |
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| 75 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
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| 76 | (8 << R300_MS_Y3_SHIFT) | |
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| 77 | (8 << R300_MS_X4_SHIFT) | |
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| 78 | (8 << R300_MS_Y4_SHIFT) | |
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| 79 | (8 << R300_MS_X5_SHIFT) | |
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| 80 | (8 << R300_MS_Y5_SHIFT) | |
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| 81 | (8 << R300_MSBD1_SHIFT))); |
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| 82 | FINISH_ACCEL(); |
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| 83 | |||
| 84 | |||
| 85 | OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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| 86 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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| 87 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
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| 88 | R300_COLOR_ROUND_NEAREST)); |
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| 89 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
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| 90 | R300_ALPHA0_SHADING_GOURAUD | |
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| 91 | R300_RGB1_SHADING_GOURAUD | |
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| 92 | R300_ALPHA1_SHADING_GOURAUD | |
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| 93 | R300_RGB2_SHADING_GOURAUD | |
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| 94 | R300_ALPHA2_SHADING_GOURAUD | |
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| 95 | R300_RGB3_SHADING_GOURAUD | |
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| 96 | R300_ALPHA3_SHADING_GOURAUD)); |
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| 97 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
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| 98 | FINISH_ACCEL(); |
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| 99 | |||
| 100 | |||
| 101 | OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
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| 102 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
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| 103 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
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| 104 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
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| 105 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
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| 106 | FINISH_ACCEL(); |
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| 107 | |||
| 108 | |||
| 109 | if (rhdPtr->has_tcl) |
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| 110 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 111 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 112 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 113 | else |
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| 114 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 115 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 116 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 117 | |||
| 118 | |||
| 812 | serge | 119 | vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
| 811 | serge | 120 | else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
| 812 | serge | 121 | (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
| 122 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
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| 811 | serge | 123 | else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
| 812 | serge | 124 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
| 811 | serge | 125 | else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
| 812 | serge | 126 | (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
| 127 | (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
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| 128 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
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| 811 | serge | 129 | else |
| 130 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
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| 131 | |||
| 132 | |||
| 133 | BEGIN_ACCEL(15); |
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| 134 | else |
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| 135 | BEGIN_ACCEL(9); |
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| 136 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
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| 137 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 138 | |||
| 139 | |||
| 140 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
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| 141 | else |
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| 142 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
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| 143 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
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| 144 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 145 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
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| 146 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
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| 147 | |||
| 148 | |||
| 149 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
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| 150 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
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| 151 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
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| 152 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
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| 153 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 154 | << R300_WRITE_ENA_0_SHIFT) | |
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| 155 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
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| 156 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
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| 157 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
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| 158 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
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| 159 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 160 | << R300_WRITE_ENA_1_SHIFT))); |
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| 161 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
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| 162 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
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| 163 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
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| 164 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
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| 165 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
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| 166 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 167 | << R300_WRITE_ENA_2_SHIFT))); |
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| 168 | |||
| 169 | |||
| 170 | OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
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| 171 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
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| 172 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
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| 173 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
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| 174 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
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| 175 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
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| 176 | } |
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| 177 | FINISH_ACCEL(); |
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| 178 | |||
| 179 | |||
| 180 | if (rhdPtr->has_tcl) { |
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| 181 | /* exa mask shader program */ |
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| 182 | BEGIN_ACCEL(13); |
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| 183 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
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| 184 | /* PVS inst 0 */ |
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| 185 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 186 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 187 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 188 | R300_PVS_DST_OFFSET(0) | |
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| 189 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 190 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 191 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 192 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 193 | R300_PVS_SRC_OFFSET(0) | |
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| 194 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 195 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 196 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 197 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 198 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 199 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 200 | R300_PVS_SRC_OFFSET(0) | |
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| 201 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 202 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 203 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 204 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 205 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 206 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 207 | R300_PVS_SRC_OFFSET(0) | |
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| 208 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 209 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 210 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 211 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 212 | |||
| 213 | |||
| 214 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 215 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 216 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 217 | R300_PVS_DST_OFFSET(1) | |
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| 218 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 219 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 220 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 221 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 222 | R300_PVS_SRC_OFFSET(6) | |
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| 223 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 224 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 225 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 226 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 227 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 228 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 229 | R300_PVS_SRC_OFFSET(6) | |
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| 230 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 231 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 232 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 233 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 234 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 235 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 236 | R300_PVS_SRC_OFFSET(6) | |
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| 237 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 238 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 239 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 240 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 241 | |||
| 242 | |||
| 243 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 244 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 245 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 246 | R300_PVS_DST_OFFSET(2) | |
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| 247 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 248 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 249 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 250 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 251 | R300_PVS_SRC_OFFSET(7) | |
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| 252 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 253 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 254 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 255 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 256 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 257 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 258 | R300_PVS_SRC_OFFSET(7) | |
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| 259 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 260 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 261 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 262 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 263 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 264 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 265 | R300_PVS_SRC_OFFSET(7) | |
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| 266 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 267 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 268 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 269 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 270 | FINISH_ACCEL(); |
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| 271 | |||
| 272 | |||
| 273 | /* exa no mask instruction */ |
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| 274 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
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| 275 | /* PVS inst 0 */ |
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| 276 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 277 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 278 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 279 | R300_PVS_DST_OFFSET(0) | |
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| 280 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 281 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 282 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 283 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 284 | R300_PVS_SRC_OFFSET(0) | |
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| 285 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 286 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 287 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 288 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 289 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 290 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 291 | R300_PVS_SRC_OFFSET(0) | |
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| 292 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 293 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 294 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 295 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 296 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 297 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 298 | R300_PVS_SRC_OFFSET(0) | |
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| 299 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 300 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 301 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 302 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 303 | |||
| 304 | |||
| 305 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 306 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 307 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 308 | R300_PVS_DST_OFFSET(1) | |
||
| 309 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 310 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 311 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 312 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 313 | R300_PVS_SRC_OFFSET(6) | |
||
| 314 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 315 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 316 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 317 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 318 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 319 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 320 | R300_PVS_SRC_OFFSET(6) | |
||
| 321 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 322 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 323 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 324 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 325 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 326 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 327 | R300_PVS_SRC_OFFSET(6) | |
||
| 328 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 329 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 330 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 331 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 332 | FINISH_ACCEL(); |
||
| 333 | |||
| 334 | |||
| 335 | BEGIN_ACCEL(9); |
||
| 336 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
||
| 337 | |||
| 338 | |||
| 339 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 340 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 341 | R300_PVS_DST_OFFSET(0) | |
||
| 342 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 343 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 344 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 345 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 346 | R300_PVS_SRC_OFFSET(0) | |
||
| 347 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 348 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 349 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 350 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 351 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 352 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 353 | R300_PVS_SRC_OFFSET(0) | |
||
| 354 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 355 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 356 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 357 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 358 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 359 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 360 | R300_PVS_SRC_OFFSET(0) | |
||
| 361 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 362 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 363 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 364 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 365 | |||
| 366 | |||
| 367 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 368 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 369 | R300_PVS_DST_OFFSET(1) | |
||
| 370 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 371 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 372 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 373 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 374 | R300_PVS_SRC_OFFSET(6) | |
||
| 375 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 376 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 377 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 378 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 379 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 380 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 381 | R300_PVS_SRC_OFFSET(6) | |
||
| 382 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 383 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 384 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 385 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 386 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 387 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 388 | R300_PVS_SRC_OFFSET(6) | |
||
| 389 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 390 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 391 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 392 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 393 | FINISH_ACCEL(); |
||
| 394 | } |
||
| 395 | |||
| 396 | |||
| 397 | BEGIN_ACCEL(4); |
||
| 398 | if (IS_R300_3D) { |
||
| 399 | /* rasterizer source table |
||
| 400 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 401 | * 0,1 are tex0 |
||
| 402 | * 2,3 are tex1 |
||
| 403 | */ |
||
| 404 | OUT_ACCEL_REG(R300_RS_IP_0, |
||
| 405 | (R300_RS_TEX_PTR(0) | |
||
| 406 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 407 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 408 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 409 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 410 | OUT_ACCEL_REG(R300_RS_IP_1, |
||
| 411 | (R300_RS_TEX_PTR(2) | |
||
| 412 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 413 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 414 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 415 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 416 | /* src tex */ |
||
| 417 | /* R300_INST_TEX_ID - select the RS source table entry |
||
| 418 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
||
| 419 | */ |
||
| 420 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
||
| 421 | R300_RS_INST_TEX_CN_WRITE | |
||
| 422 | R300_INST_TEX_ADDR(0))); |
||
| 423 | /* mask tex */ |
||
| 424 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
||
| 425 | R300_RS_INST_TEX_CN_WRITE | |
||
| 426 | R300_INST_TEX_ADDR(1))); |
||
| 427 | |||
| 428 | |||
| 429 | /* rasterizer source table |
||
| 430 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 431 | * 0,1 are tex0 |
||
| 432 | * 2,3 are tex1 |
||
| 433 | */ |
||
| 434 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
| 435 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
| 436 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 437 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 438 | |||
| 439 | |||
| 440 | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
| 441 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 442 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 443 | /* src tex */ |
||
| 444 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
||
| 445 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
||
| 446 | */ |
||
| 447 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 448 | R500_RS_INST_TEX_CN_WRITE | |
||
| 449 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 450 | /* mask tex */ |
||
| 451 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 452 | R500_RS_INST_TEX_CN_WRITE | |
||
| 453 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 454 | } |
||
| 455 | FINISH_ACCEL(); |
||
| 456 | |||
| 457 | |||
| 458 | if (IS_R300_3D) { |
||
| 459 | BEGIN_ACCEL(2); |
||
| 460 | /* tex inst for src texture */ |
||
| 461 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
||
| 462 | (R300_TEX_SRC_ADDR(0) | |
||
| 463 | R300_TEX_DST_ADDR(0) | |
||
| 464 | R300_TEX_ID(0) | |
||
| 465 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 466 | |||
| 467 | |||
| 468 | OUT_ACCEL_REG(R300_US_TEX_INST_1, |
||
| 469 | (R300_TEX_SRC_ADDR(1) | |
||
| 470 | R300_TEX_DST_ADDR(1) | |
||
| 471 | R300_TEX_ID(1) | |
||
| 472 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 473 | FINISH_ACCEL(); |
||
| 474 | } |
||
| 475 | |||
| 476 | |||
| 477 | BEGIN_ACCEL(9); |
||
| 478 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
||
| 479 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 480 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
||
| 481 | (R300_ALU_START(0) | |
||
| 482 | R300_ALU_SIZE(0) | |
||
| 483 | R300_TEX_START(0) | |
||
| 484 | R300_TEX_SIZE(0))); |
||
| 485 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
||
| 486 | (R300_ALU_START(0) | |
||
| 487 | R300_ALU_SIZE(0) | |
||
| 488 | R300_TEX_START(0) | |
||
| 489 | R300_TEX_SIZE(0))); |
||
| 490 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
||
| 491 | (R300_ALU_START(0) | |
||
| 492 | R300_ALU_SIZE(0) | |
||
| 493 | R300_TEX_START(0) | |
||
| 494 | R300_TEX_SIZE(0))); |
||
| 495 | } else { |
||
| 496 | BEGIN_ACCEL(7); |
||
| 497 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
||
| 498 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 499 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
||
| 500 | } |
||
| 501 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
||
| 502 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
||
| 503 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 504 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 505 | R300_OUT_FMT_C2_SEL_RED | |
||
| 506 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 507 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
||
| 508 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 509 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 510 | R300_OUT_FMT_C2_SEL_RED | |
||
| 511 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 512 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
||
| 513 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 514 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 515 | R300_OUT_FMT_C2_SEL_RED | |
||
| 516 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 517 | FINISH_ACCEL(); |
||
| 518 | |||
| 519 | |||
| 520 | |||
| 521 | OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
||
| 522 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
||
| 523 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
||
| 524 | FINISH_ACCEL(); |
||
| 525 | |||
| 526 | |||
| 527 | OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
||
| 528 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
||
| 529 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
||
| 530 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
||
| 531 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
||
| 532 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
||
| 533 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
||
| 534 | |||
| 535 | |||
| 536 | OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
||
| 537 | R300_GREEN_MASK_EN | |
||
| 538 | R300_RED_MASK_EN | |
||
| 539 | R300_ALPHA_MASK_EN)); |
||
| 540 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 541 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
||
| 542 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
||
| 543 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 544 | FINISH_ACCEL(); |
||
| 545 | |||
| 546 | |||
| 547 | OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
||
| 548 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
||
| 549 | (0 << R300_SCISSOR_Y_SHIFT))); |
||
| 550 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
||
| 551 | (8191 << R300_SCISSOR_Y_SHIFT))); |
||
| 552 | |||
| 553 | |||
| 554 | /* clip has offset 1440 */ |
||
| 555 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
||
| 556 | (1088 << R300_CLIP_Y_SHIFT))); |
||
| 557 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
||
| 558 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
||
| 559 | } else { |
||
| 560 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
||
| 561 | (0 << R300_CLIP_Y_SHIFT))); |
||
| 562 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
||
| 563 | (4080 << R300_CLIP_Y_SHIFT))); |
||
| 564 | } |
||
| 565 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
| 566 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
||
| 567 | FINISH_ACCEL(); |
||
| 568 | } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
||
| 812 | serge | 569 | (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
| 570 | (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
||
| 571 | (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
||
| 572 | |||
| 811 | serge | 573 | |
| 574 | if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { |
||
| 812 | serge | 575 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
| 811 | serge | 576 | } else { |
| 577 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
||
| 578 | } |
||
| 579 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
||
| 580 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
||
| 581 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
||
| 582 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
||
| 583 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
||
| 584 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
||
| 585 | R200_VAP_VF_MAX_VTX_NUM); |
||
| 586 | FINISH_ACCEL(); |
||
| 587 | |||
| 588 | |||
| 589 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
| 590 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 591 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 592 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 593 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 594 | RADEON_BFACE_SOLID | |
||
| 595 | RADEON_FFACE_SOLID | |
||
| 596 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 597 | RADEON_ROUND_MODE_ROUND | |
||
| 598 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 599 | FINISH_ACCEL(); |
||
| 600 | } else { |
||
| 601 | BEGIN_ACCEL(2); |
||
| 602 | if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
||
| 812 | serge | 603 | (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
| 604 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
||
| 811 | serge | 605 | else |
| 606 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
| 607 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
||
| 608 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
||
| 609 | RADEON_VTX_ST0_NONPARAMETRIC | |
||
| 610 | RADEON_VTX_ST1_NONPARAMETRIC | |
||
| 611 | RADEON_TEX1_W_ROUTING_USE_W0); |
||
| 612 | FINISH_ACCEL(); |
||
| 613 | |||
| 614 | |||
| 615 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
| 616 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 617 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 618 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 619 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 620 | RADEON_BFACE_SOLID | |
||
| 621 | RADEON_FFACE_SOLID | |
||
| 622 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 623 | RADEON_ROUND_MODE_ROUND | |
||
| 624 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 625 | FINISH_ACCEL(); |
||
| 626 | } |
||
| 627 | |||
| 628 | |||
| 629 |