Rev 815 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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808 | serge | 1 | |
2 | #define DRAW_RECT 2 |
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3 | #define LINE_2P 3 |
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4 | #define BLIT 4 |
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810 | serge | 5 | #define COMPIZ 5 |
813 | serge | 6 | #define PIXMAP 6 |
815 | serge | 7 | #define PIXBLIT 7 |
8 | #define PIXLOCK 8 |
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817 | serge | 9 | |
808 | serge | 10 | |
817 | serge | 11 | |
808 | serge | 12 | |
13 | |||
14 | { |
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15 | pixmap_t *dstpix; |
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817 | serge | 16 | |
17 | |||
18 | int y; |
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19 | u32_t w; |
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20 | u32_t h; |
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21 | color_t color; |
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22 | }draw_t; |
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808 | serge | 23 | |
24 | |||
25 | { |
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26 | pixmap_t *dstpix; |
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817 | serge | 27 | |
28 | |||
808 | serge | 29 | int y; |
30 | int w; |
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31 | int h; |
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32 | |||
33 | |||
34 | color_t fcolor; |
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35 | |||
36 | |||
37 | u32_t bmp1; |
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38 | }fill_t; |
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39 | |||
40 | |||
41 | { |
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42 | int src_x; |
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810 | serge | 43 | int src_y; |
44 | int dst_x; |
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45 | int dst_y; |
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46 | int w; |
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47 | int h; |
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48 | }blit_t; |
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49 | |||
50 | |||
51 | { |
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52 | int x0; |
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808 | serge | 53 | int y0; |
54 | int x1; |
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55 | int y1; |
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56 | u32 color; |
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57 | }line2p_t; |
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58 | |||
59 | |||
815 | serge | 60 | { |
61 | pixmap_t *pixmap; |
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817 | serge | 62 | void *usermap; |
63 | u32_t format; |
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64 | u32_t pitch; |
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65 | |||
815 | serge | 66 | |
817 | serge | 67 | u32_t height; |
68 | }userpixmap_t; |
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69 | |||
70 | |||
815 | serge | 71 | { |
72 | pixmap_t *dstpix; |
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73 | int dst_x; |
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817 | serge | 74 | int dst_y; |
75 | |||
815 | serge | 76 | |
77 | int src_x; |
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817 | serge | 78 | int src_y; |
79 | int w; |
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80 | int h; |
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81 | }pixblit_t; |
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815 | serge | 82 | |
83 | |||
84 | |||
808 | serge | 85 | int BlockClip( int *x1, int *y1, int *x2, int* y2); |
86 | |||
87 | |||
88 | int FillRect(fill_t * fill); |
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89 | |||
90 | |||
91 | |||
92 | |||
810 | serge | 93 | |
808 | serge | 94 | |
813 | serge | 95 | |
96 | |||
817 | serge | 97 | |
813 | serge | 98 | |
815 | serge | 99 | |
100 | |||
817 | serge | 101 | |
102 | |||
808 | serge | 103 | # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
104 | # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
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811 | serge | 105 | # define RADEON_GMC_BRUSH_NONE (15 << 4) |
106 | # define RADEON_GMC_DST_16BPP (4 << 8) |
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107 | # define RADEON_GMC_DST_24BPP (5 << 8) |
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108 | # define RADEON_GMC_DST_32BPP (6 << 8) |
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109 | # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
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110 | # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
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111 | # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
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112 | # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
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113 | # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
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114 | # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
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115 | # define RADEON_ROP3_S 0x00cc0000 |
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116 | # define RADEON_ROP3_P 0x00f00000 |
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117 | |||
808 | serge | 118 | |
811 | serge | 119 | #define RADEON_CP_PACKET1 0x40000000 |
120 | #define RADEON_CP_PACKET2 0x80000000 |
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121 | #define RADEON_CP_PACKET3 0xC0000000 |
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808 | serge | 122 | |
123 | |||
124 | # define RADEON_CNTL_BITBLT 0x00009200 |
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810 | serge | 125 | |
126 | |||
808 | serge | 127 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
128 | |||
129 | |||
811 | serge | 130 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
131 | |||
132 | |||
133 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
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134 | |||
135 | |||
136 | (RADEON_CP_PACKET2) |
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137 | |||
138 | |||
808 | serge | 139 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
140 | |||
141 | |||
142 | ring = rhd.ring_base; \ |
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143 | write = rhd.ring_wp; \ |
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144 | } while (0) |
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145 | |||
146 | |||
811 | serge | 147 | |
148 | |||
808 | serge | 149 | ring[write++] = (x); \ |
150 | } while (0) |
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151 | |||
152 | |||
811 | serge | 153 | do { \ |
154 | OUT_RING(CP_PACKET0(reg, 0)); \ |
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155 | OUT_RING(val); \ |
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156 | } while (0) |
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157 | |||
158 | |||
808 | serge | 159 | |
160 | |||
161 | rhd.ring_wp = write & 0x1FFF; \ |
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162 | /* Flush writes to ring */ \ |
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163 | DRM_MEMORYBARRIER(); \ |
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164 | /*GET_RING_HEAD( dev_priv ); */ \ |
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165 | OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
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166 | /* read from PCI bus to ensure correct posting */ \ |
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167 | INREG( RADEON_CP_RB_RPTR ); \ |
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168 | } while (0)><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
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169 |