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Rev | Author | Line No. | Line |
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808 | serge | 1 | |
2 | #define DRAW_RECT 2 |
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3 | #define LINE_2P 3 |
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4 | #define BLIT 4 |
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810 | serge | 5 | |
808 | serge | 6 | |
810 | serge | 7 | |
808 | serge | 8 | typedef unsigned int u32_t; |
9 | |||
10 | |||
11 | { |
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12 | int x; |
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13 | int y; |
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14 | int w; |
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15 | int h; |
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16 | u32 color; |
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17 | }draw_t; |
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18 | |||
19 | |||
20 | { |
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21 | int x; |
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22 | int y; |
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23 | int w; |
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24 | int h; |
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25 | |||
26 | |||
27 | color_t fcolor; |
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28 | |||
29 | |||
30 | u32_t bmp1; |
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31 | }fill_t; |
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32 | |||
33 | |||
34 | { |
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35 | int src_x; |
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810 | serge | 36 | int src_y; |
37 | int dst_x; |
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38 | int dst_y; |
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39 | int w; |
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40 | int h; |
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41 | }blit_t; |
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42 | |||
43 | |||
44 | { |
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45 | int x0; |
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808 | serge | 46 | int y0; |
47 | int x1; |
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48 | int y1; |
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49 | u32 color; |
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50 | }line2p_t; |
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51 | |||
52 | |||
53 | int BlockClip( int *x1, int *y1, int *x2, int* y2); |
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54 | |||
55 | |||
56 | int FillRect(fill_t * fill); |
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57 | |||
58 | |||
59 | |||
60 | |||
810 | serge | 61 | |
808 | serge | 62 | |
63 | # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
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64 | # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
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811 | serge | 65 | # define RADEON_GMC_BRUSH_NONE (15 << 4) |
66 | # define RADEON_GMC_DST_16BPP (4 << 8) |
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67 | # define RADEON_GMC_DST_24BPP (5 << 8) |
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68 | # define RADEON_GMC_DST_32BPP (6 << 8) |
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69 | # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
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70 | # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
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71 | # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
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72 | # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
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73 | # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
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74 | # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
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75 | # define RADEON_ROP3_S 0x00cc0000 |
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76 | # define RADEON_ROP3_P 0x00f00000 |
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77 | |||
808 | serge | 78 | |
811 | serge | 79 | #define RADEON_CP_PACKET1 0x40000000 |
80 | #define RADEON_CP_PACKET2 0x80000000 |
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81 | #define RADEON_CP_PACKET3 0xC0000000 |
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808 | serge | 82 | |
83 | |||
84 | # define RADEON_CNTL_BITBLT 0x00009200 |
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810 | serge | 85 | |
86 | |||
808 | serge | 87 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
88 | |||
89 | |||
811 | serge | 90 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
91 | |||
92 | |||
93 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
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94 | |||
95 | |||
96 | (RADEON_CP_PACKET2) |
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97 | |||
98 | |||
808 | serge | 99 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
100 | |||
101 | |||
102 | ring = rhd.ring_base; \ |
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103 | write = rhd.ring_wp; \ |
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104 | } while (0) |
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105 | |||
106 | |||
811 | serge | 107 | |
108 | |||
808 | serge | 109 | ring[write++] = (x); \ |
110 | } while (0) |
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111 | |||
112 | |||
811 | serge | 113 | do { \ |
114 | OUT_RING(CP_PACKET0(reg, 0)); \ |
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115 | OUT_RING(val); \ |
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116 | } while (0) |
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117 | |||
118 | |||
808 | serge | 119 | |
120 | |||
121 | rhd.ring_wp = write & 0x1FFF; \ |
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122 | /* Flush writes to ring */ \ |
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123 | DRM_MEMORYBARRIER(); \ |
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124 | /*GET_RING_HEAD( dev_priv ); */ \ |
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125 | OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
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126 | /* read from PCI bus to ensure correct posting */ \ |
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127 | INREG( RADEON_CP_RB_RPTR ); \ |
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128 | } while (0)><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
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129 |