Rev 948 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
948 | serge | 1 | |
2 | |||
3 | { |
||
4 | u16_t device; |
||
5 | u16_t ChipSet; |
||
6 | }PciChipset_t; |
||
7 | #pragma pack(pop) |
||
8 | |||
9 | #define VENDOR_ATI 0x1002 |
||
10 | |||
11 | |||
12 | |||
13 | |||
951 | serge | 14 | * Under PCI, each device has 256 bytes of configuration address space, |
15 | * of which the first 64 bytes are standardized as follows: |
||
16 | */ |
||
17 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
||
18 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
||
19 | #define PCI_COMMAND 0x04 /* 16 bits */ |
||
20 | #define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */ |
||
21 | #define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */ |
||
22 | #define PCI_COMMAND_MASTER 0x04 /* Enable bus mastering */ |
||
23 | #define PCI_COMMAND_SPECIAL 0x08 /* Enable response to special cycles */ |
||
24 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
||
25 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
||
26 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
||
27 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
||
28 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
||
29 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
||
30 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
||
31 | |||
32 | #define PCI_STATUS 0x06 /* 16 bits */ |
||
33 | |||
34 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
||
35 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
||
36 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
||
37 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
||
38 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
||
39 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
||
40 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
||
41 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
||
42 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
||
43 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
||
44 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
||
45 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
||
46 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
||
47 | |||
48 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
||
49 | |||
50 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
||
51 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
||
52 | |||
53 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
||
54 | |||
55 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
||
56 | #define PCI_HEADER_TYPE_NORMAL 0 |
||
57 | #define PCI_HEADER_TYPE_BRIDGE 1 |
||
58 | #define PCI_HEADER_TYPE_CARDBUS 2 |
||
59 | |||
60 | #define PCI_BIST 0x0f /* 8 bits */ |
||
61 | |||
62 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
||
63 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
||
64 | |||
65 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
||
66 | |||
67 | /* Capability lists */ |
||
68 | |||
69 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
||
70 | |||
71 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
||
72 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
||
73 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
||
74 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
||
75 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
||
76 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
||
77 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
||
78 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
||
79 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
||
80 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
||
81 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
||
82 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
||
83 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
||
84 | #define PCI_CAP_SIZEOF 4 |
||
85 | |||
86 | |||
87 | |||
88 | |||
89 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
||
90 | |||
91 | #define PCI_AGP_STATUS 4 /* Status register */ |
||
92 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
||
93 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
||
94 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
||
95 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
||
96 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
||
97 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
||
98 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
||
99 | #define PCI_AGP_COMMAND 8 /* Control register */ |
||
100 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
||
101 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
||
102 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
||
103 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
||
104 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
||
105 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
||
106 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
||
107 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
||
108 | #define PCI_AGP_SIZEOF 12 |
||
109 | |||
110 | |||
111 | |||
112 | |||
948 | serge | 113 | #define PCI_MAP_ROM_REG 0x30 |
114 | |||
115 | #define PCI_MAP_MEMORY 0x00000000 |
||
116 | |||
117 | |||
118 | #define PCI_MAP_MEMORY_TYPE 0x00000007 |
||
119 | |||
120 | |||
121 | #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
||
122 | |||
123 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
||
124 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
||
125 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
||
126 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
||
127 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
||
128 | |||
129 | #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
||
130 | |||
131 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
||
132 | |||
133 | |||
134 | #define PCI_MAP_IS64BITMEM(b) \ |
||
135 | |||
136 | |||
137 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
||
138 | |||
139 | #define PCIGETMEMORY64(b) \ |
||
140 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
||
141 | |||
142 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
||
143 | |||
144 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
||
145 | |||
146 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
||
147 | |||
148 | |||
149 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
||
150 | |||
151 | |||
152 | |||
153 | |||
154 | #endif |
||
155 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
||
156 | |||
157 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
||
158 | |||
159 | (((f) & 0x000007u) << 8)) |
||
160 | |||
161 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
||
162 | |||
163 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
||
164 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
||
165 | |||
166 | |||
167 | |||
168 | |||
169 | extern inline PCITAG |
||
170 | |||
171 | { |
||
172 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
||
173 | } |
||
174 | |||
175 | const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list); |
||
176 | |||
177 | |||
178 | #define PCI_ANY_ID (~0) |
||
951 | serge | 179 | |
180 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)><>><>><>><>><> |
||
181 |