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1814 yogev_ezra 1 
/*====================================================================/*
2 
  opcodes_ddfdcb.c -> This file executes the DD/FD CB PREFIX opcodes.
3 
 
4 
  Those are the double prefix opcodes. We found the DD prefix, which
5 
  means that we must treat HL as IX, and then we found the CB prefix,
6 
  so we must apply this rule to the CB PREFIX list of opcodes. A
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  signed byte displacement is also added, and it's located BEFORE
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  the DD CB opcode:
9 
 
10 
     ie:     CB 2E        =  SRA (HL)
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             DD CB xx 2E  =  SRA (IX+xx)
12 
 
13 
  (or...)
14 
 
15 
  Those are the double prefix opcodes. We found the FD prefix, which
16 
  means that we must treat HL as IY, and then we found the CB prefix,
17 
  so we must apply this rule to the CB PREFIX list of opcodes. A
18 
  signed byte displacement is also added, and it's located BEFORE
19 
  the FD CB opcode:
20 
 
21 
     ie:     CB 2E        =  SRA (HL)
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             FD CB xx 2E  =  SRA (IY+xx)
23 
 
24 
 Call here using something like #define REGISTER regs->IX
25 
 
26 
 This program is free software; you can redistribute it and/or modify
27 
 it under the terms of the GNU General Public License as published by
28 
 the Free Software Foundation; either version 2 of the License, or
29 
 (at your option) any later version.
30 
 
31 
 This program is distributed in the hope that it will be useful,
32 
 but WITHOUT ANY WARRANTY; without even the implied warranty of
33 
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34 
 GNU General Public License for more details.
35 
 
36 
 You should have received a copy of the GNU General Public License
37 
 along with this program; if not, write to the Free Software
38 
 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
39 
 
40 
 Copyright (c) 2000 Santiago Romero Iglesias.
41 
 Email: sromero@escomposlinux.org
42 
 =====================================================================*/
43 
 
44 
/* 15 clock cycles minimum = FD/DD CB xx opcode = 4 + 4 + 3 + 4 */
45 
 
46 
tmpreg.W = REGISTER.W + (offset) Z80ReadMem( r_PC );
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r_PC++;
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r_meml = Z80ReadMem( tmpreg.W );
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opcode = Z80ReadMem( r_PC );
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r_PC++;
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52 
switch(opcode)
53 
{
54 
 
55 
  case  RLC_xIXY    :  RLC(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  RRC_xIXY    :  RRC(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  RL_xIXY     :  RL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  RR_xIXY     :  RR(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  SLA_xIXY    :  SLA(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  SRA_xIXY    :  SRA(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  SLL_xIXY    :  SLL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
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  case  SRL_xIXY    :  SRL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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                       AddCycles( 23 ); break;
71 
  case  0x40:
72 
  case  0x41:
73 
  case  0x42:
74 
  case  0x43:
75 
  case  0x44:
76 
  case  0x45:
77 
  case  0x47:
78 
  case  BIT_0_xIXY  :  BIT_BIT(0, r_meml); AddCycles( 15+5 ); break;
79 
 
80 
  case  0x48:
81 
  case  0x49:
82 
  case  0x4a:
83 
  case  0x4b:
84 
  case  0x4c:
85 
  case  0x4d:
86 
  case  0x4f:
87 
  case  BIT_1_xIXY  :
88 
                       BIT_BIT(1, r_meml); AddCycles( 15+5 ); break;
89 
 
90 
  case  0x50:
91 
  case  0x51:
92 
  case  0x52:
93 
  case  0x53:
94 
  case  0x54:
95 
  case  0x55:
96 
  case  0x57:
97 
  case  BIT_2_xIXY  :  BIT_BIT(2, r_meml); AddCycles( 15+5 ); break;
98 
 
99 
  case  0x58:
100 
  case  0x59:
101 
  case  0x5a:
102 
  case  0x5b:
103 
  case  0x5c:
104 
  case  0x5d:
105 
  case  0x5f:
106 
  case  BIT_3_xIXY  :  BIT_BIT(3, r_meml); AddCycles( 15+5 ); break;
107 
 
108 
  case  0x60:
109 
  case  0x61:
110 
  case  0x62:
111 
  case  0x63:
112 
  case  0x64:
113 
  case  0x65:
114 
  case  0x67:
115 
  case  BIT_4_xIXY  :  BIT_BIT(4, r_meml); AddCycles( 15+5 ); break;
116 
 
117 
  case  0x68:
118 
  case  0x69:
119 
  case  0x6a:
120 
  case  0x6b:
121 
  case  0x6c:
122 
  case  0x6d:
123 
  case  0x6f:
124 
  case  BIT_5_xIXY  :  BIT_BIT(5, r_meml); AddCycles( 15+5 ); break;
125 
 
126 
  case  0x70:
127 
  case  0x71:
128 
  case  0x72:
129 
  case  0x73:
130 
  case  0x74:
131 
  case  0x75:
132 
  case  0x77:
133 
  case  BIT_6_xIXY  :  BIT_BIT(6, r_meml); AddCycles( 15+5 ); break;
134 
  case  0x78:
135 
  case  0x79:
136 
  case  0x7a:
137 
  case  0x7b:
138 
  case  0x7c:
139 
  case  0x7d:
140 
  case  0x7f:
141 
  case  BIT_7_xIXY  :  BIT_BIT7(r_meml); AddCycles( 15+5 ); break;
142 
 
143 
  case  RES_0_xIXY  :  BIT_RES_mem(0, tmpreg.W, r_meml );
144 
                       AddCycles( 15+5+3 ); break;
145 
  case  RES_1_xIXY  :  BIT_RES_mem(1, tmpreg.W, r_meml );
146 
                       AddCycles( 15+5+3 ); break;
147 
  case  RES_2_xIXY  :  BIT_RES_mem(2, tmpreg.W, r_meml );
148 
                       AddCycles( 15+5+3 ); break;
149 
  case  RES_3_xIXY  :  BIT_RES_mem(3, tmpreg.W, r_meml );
150 
                       AddCycles( 15+5+3 ); break;
151 
  case  RES_4_xIXY  :  BIT_RES_mem(4, tmpreg.W, r_meml );
152 
                       AddCycles( 15+5+3 ); break;
153 
  case  RES_5_xIXY  :  BIT_RES_mem(5, tmpreg.W, r_meml );
154 
                       AddCycles( 15+5+3 ); break;
155 
  case  RES_6_xIXY  :  BIT_RES_mem(6, tmpreg.W, r_meml );
156 
                       AddCycles( 15+5+3 ); break;
157 
  case  RES_7_xIXY  :  BIT_RES_mem(7, tmpreg.W, r_meml );
158 
                       AddCycles( 15+5+3 ); break;
159 
  case  SET_0_xIXY  :  BIT_SET_mem(0, tmpreg.W, r_meml );
160 
                       AddCycles( 15+5+3 ); break;
161 
  case  SET_1_xIXY  :  BIT_SET_mem(1, tmpreg.W, r_meml );
162 
                       AddCycles( 15+5+3 ); break;
163 
  case  SET_2_xIXY  :  BIT_SET_mem(2, tmpreg.W, r_meml );
164 
                       AddCycles( 15+5+3 ); break;
165 
  case  SET_3_xIXY  :  BIT_SET_mem(3, tmpreg.W, r_meml );
166 
                       AddCycles( 15+5+3 ); break;
167 
  case  SET_4_xIXY  :  BIT_SET_mem(4, tmpreg.W, r_meml );
168 
                       AddCycles( 15+5+3 ); break;
169 
  case  SET_5_xIXY  :  BIT_SET_mem(5, tmpreg.W, r_meml );
170 
                       AddCycles( 15+5+3 ); break;
171 
  case  SET_6_xIXY  :  BIT_SET_mem(6, tmpreg.W, r_meml );
172 
                       AddCycles( 15+5+3 ); break;
173 
  case  SET_7_xIXY  :  BIT_SET_mem(7, tmpreg.W, r_meml );
174 
                       AddCycles( 15+5+3 ); break;
175 
 
176 
 
177 
/*
178 
 I must still include the undocumented opcodes such as:
179 
 LD B, RLC(REGISTER+dd)       and so on ...
180 
 
181 
*/
182 
  default:
183 
    AddCycles( 15 );
184 
//    exit(1);
185 
///!!!    if(regs->DecodingErrors)
186 
///!!!    {
187 
///!!!      printf("z80 core: Unknown instruction: ");
188 
///!!!      if( regs->we_are_on_ddfd == WE_ARE_ON_DD )
189 
///!!!         printf("DD");
190 
///!!!      else
191 
///!!!         printf("FD");
192 
///!!!      printf("CB %02Xh %02Xh at PC=%04Xh.\n",
193 
///!!!              Z80ReadMem(r_PC-2), Z80ReadMem(r_PC-1), r_PC-4 );
194 
///!!!    }
195 
    break;
196 
}