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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1814 | yogev_ezra | 1 | /*====================================================================/* |
| 2 | opcodes_dd_fd.c -> This file executes the DD/FD PREFIX opcodes. |
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| 3 | |||
| 4 | The DD prefix "creates" some new instructions by changing HL to IX |
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| 5 | on the opcode defined by the next byte on memory. |
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| 6 | |||
| 7 | The FD prefix "creates" some new instructions by changing HL to IY |
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| 8 | on the opcode defined by the next byte on memory. |
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| 9 | |||
| 10 | Change the REGISTER variable to IX or HY before including this file. |
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| 11 | Something like: |
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| 12 | |||
| 13 | #define REGISTER regs->IX |
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| 14 | #include "op_dd_fd.c" |
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| 15 | #undef REGISTER |
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| 16 | |||
| 17 | On this code, this REGISTER variable is used as REGISTER.W or |
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| 18 | REGISTER.B.h and REGISTER.B.l ... |
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| 19 | |||
| 20 | This program is free software; you can redistribute it and/or modify |
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| 21 | it under the terms of the GNU General Public License as published by |
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| 22 | the Free Software Foundation; either version 2 of the License, or |
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| 23 | (at your option) any later version. |
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| 24 | |||
| 25 | This program is distributed in the hope that it will be useful, |
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| 26 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 27 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 28 | GNU General Public License for more details. |
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| 29 | |||
| 30 | You should have received a copy of the GNU General Public License |
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| 31 | along with this program; if not, write to the Free Software |
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| 32 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 33 | |||
| 34 | Copyright (c) 2000 Santiago Romero Iglesias. |
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| 35 | Email: sromero@escomposlinux.org |
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| 36 | =====================================================================*/ |
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| 37 | |||
| 38 | /* 8 clock cycles minimum = DD opcode = FD opcode = 4 + 4 */ |
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| 39 | |||
| 40 | #define REG REGISTER.W |
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| 41 | #define REGL REGISTER.B.l |
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| 42 | #define REGH REGISTER.B.h |
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| 43 | |||
| 44 | opcode = Z80ReadMem( r_PC ); |
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| 45 | r_PC++; |
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| 46 | |||
| 47 | switch(opcode) |
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| 48 | { |
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| 49 | case ADD_IXY_BC : ADD_WORD(REG, r_BC); AddCycles( 4+4+7 ); break; |
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| 50 | case ADD_IXY_DE : ADD_WORD(REG, r_DE); AddCycles( 4+4+7 ); break; |
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| 51 | case ADD_IXY_SP : ADD_WORD(REG, r_SP); AddCycles( 4+4+7 ); break; |
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| 52 | case ADD_IXY_IXY : ADD_WORD(REG, REG); AddCycles( 4+4+7 ); break; |
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| 53 | case DEC_IXY : REG--; AddCycles( 4+4+2 ); break; |
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| 54 | case INC_IXY : REG++; AddCycles( 4+4 ); break; |
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| 55 | |||
| 56 | case JP_IXY : r_PC = REG; AddCycles( 4+4 );break; |
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| 57 | case LD_SP_IXY : r_SP = REG; AddCycles( 4+4+2 ); break; |
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| 58 | |||
| 59 | case PUSH_IXY : PUSH_IXYr(); AddCycles( 4+4+3+3+1 ); break; |
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| 60 | case POP_IXY : POP_IXYr(); AddCycles( 4+4+3+3 ); break; |
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| 61 | |||
| 62 | case EX_IXY_xSP : r_meml = Z80ReadMem(r_SP); |
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| 63 | r_memh = Z80ReadMem(r_SP+1); |
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| 64 | Z80WriteMem( r_SP, REGL, regs ); |
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| 65 | Z80WriteMem( r_SP+1, REGH, regs ); |
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| 66 | REGL=r_meml; REGH=r_memh; |
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| 67 | AddCycles( 4+4+3+3+3+3+3 ); break; |
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| 68 | |||
| 69 | case LD_A_xIXY : r_A = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) ); |
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| 70 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 71 | case LD_B_xIXY : r_B = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) ); |
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| 72 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 73 | case LD_C_xIXY : r_C = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) ); |
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| 74 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 75 | case LD_D_xIXY : r_D = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) ); |
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| 76 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 77 | case LD_E_xIXY : r_E = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) ); |
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| 78 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 79 | |||
| 80 | case LD_xIXY_A : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_A, regs ); |
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| 81 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 82 | case LD_xIXY_B : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_B, regs ); |
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| 83 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 84 | case LD_xIXY_C : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_C, regs ); |
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| 85 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 86 | case LD_xIXY_D : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_D, regs ); |
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| 87 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 88 | case LD_xIXY_E : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_E, regs ); |
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| 89 | r_PC++; AddCycles( 4+3+3+3+3+3 ); break; |
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| 90 | |||
| 91 | case INC_xIXY : r_mem = REG+(offset)Z80ReadMem(r_PC); |
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| 92 | r_PC++; |
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| 93 | tmpreg.B.l = Z80ReadMem(r_mem); |
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| 94 | INC(tmpreg.B.l); |
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| 95 | Z80WriteMem(r_mem, tmpreg.B.l, regs ); |
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| 96 | AddCycles( 4+3+3 + 3+3+3+ 3+1); break; |
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| 97 | case DEC_xIXY : r_mem = REG+(offset)Z80ReadMem(r_PC); |
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| 98 | r_PC++; |
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| 99 | tmpreg.B.l = Z80ReadMem(r_mem); |
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| 100 | DEC(tmpreg.B.l); |
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| 101 | Z80WriteMem(r_mem, tmpreg.B.l, regs ); |
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| 102 | AddCycles( 4+3+3 + 3+3+3+ 3+1); break; |
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| 103 | |||
| 104 | case ADC_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); r_PC++; |
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| 105 | ADC(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 106 | case SBC_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 107 | r_PC++; |
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| 108 | SBC(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 109 | case ADD_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 110 | r_PC++; |
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| 111 | ADD(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 112 | case SUB_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 113 | r_PC++; |
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| 114 | SUB(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 115 | case AND_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 116 | r_PC++; |
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| 117 | AND(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 118 | case OR_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 119 | r_PC++; |
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| 120 | OR(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 121 | case XOR_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 122 | r_PC++; |
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| 123 | XOR(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 124 | |||
| 125 | case CP_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); |
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| 126 | r_PC++; |
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| 127 | CP(r_meml); AddCycles( 4+3+3+3+3+3 ); break; |
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| 128 | |||
| 129 | case LD_IXY_NN : REGL = Z80ReadMem(r_PC); r_PC++; |
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| 130 | REGH = Z80ReadMem(r_PC); r_PC++; |
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| 131 | AddCycles( 4+1+3+3+3 ); break; |
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| 132 | |||
| 133 | case LD_xIXY_N : r_mem = REG + (offset) Z80ReadMem(r_PC); r_PC++; |
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| 134 | Z80WriteMem( r_mem, Z80ReadMem(r_PC), regs ); r_PC++; |
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| 135 | AddCycles( 4+3+3+3+3+3 ); break; |
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| 136 | |||
| 137 | case LD_IXY_xNN : LOAD_rr_nn(REG); |
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| 138 | AddCycles( 4+3+3+3+3+3+1 ); break; |
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| 139 | |||
| 140 | case LD_xNN_IXY : STORE_nn_rr(REG); |
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| 141 | AddCycles( 4+3+3+ 3+3+3+1 ); break; |
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| 142 | |||
| 143 | |||
| 144 | /* some undocumented opcodes: may be wrong: */ |
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| 145 | case LD_A_IXYh : r_A = REGH; AddCycles(4+4); break; |
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| 146 | case LD_A_IXYl : r_A = REGL; AddCycles(4+4); break; |
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| 147 | case LD_B_IXYh : r_B = REGH; AddCycles(4+4); break; |
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| 148 | case LD_B_IXYl : r_B = REGL; AddCycles(4+4); break; |
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| 149 | case LD_C_IXYh : r_C = REGH; AddCycles(4+4); break; |
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| 150 | case LD_C_IXYl : r_C = REGL; AddCycles(4+4); break; |
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| 151 | case LD_D_IXYh : r_D = REGH; AddCycles(4+4); break; |
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| 152 | case LD_D_IXYl : r_D = REGL; AddCycles(4+4); break; |
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| 153 | case LD_E_IXYh : r_E = REGH; AddCycles(4+4); break; |
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| 154 | case LD_E_IXYl : r_E = REGL; AddCycles(4+4); break; |
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| 155 | case LD_IXYh_A : REGH = r_A; AddCycles(4+4); break; |
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| 156 | case LD_IXYh_B : REGH = r_B; AddCycles(4+4); break; |
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| 157 | case LD_IXYh_C : REGH = r_C; AddCycles(4+4); break; |
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| 158 | case LD_IXYh_D : REGH = r_D; AddCycles(4+4); break; |
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| 159 | case LD_IXYh_E : REGH = r_E; AddCycles(4+4); break; |
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| 160 | case LD_IXYh_IXYh : AddCycles(4+4); break; |
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| 161 | case LD_IXYh_IXYl : REGH = REGL; AddCycles(4+4); break; |
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| 162 | case LD_IXYl_A : REGL = r_A; AddCycles(4+4); break; |
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| 163 | case LD_IXYl_B : REGL = r_B; AddCycles(4+4); break; |
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| 164 | case LD_IXYl_C : REGL = r_C; AddCycles(4+4); break; |
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| 165 | case LD_IXYl_D : REGL = r_D; AddCycles(4+4); break; |
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| 166 | case LD_IXYl_E : REGL = r_E; AddCycles(4+4); break; |
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| 167 | case LD_IXYl_IXYh : REGL = REGH; AddCycles(4+4); break; |
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| 168 | case LD_IXYl_IXYl : AddCycles(4+4); break; |
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| 169 | case LD_IXYh_N : REGH = Z80ReadMem(r_PC); r_PC++; |
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| 170 | AddCycles(4+4+3); break; |
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| 171 | case LD_IXYl_N : REGL = Z80ReadMem(r_PC); r_PC++; |
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| 172 | AddCycles(4+4+3); break; |
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| 173 | |||
| 174 | |||
| 175 | case ADD_IXYh : ADD(REGH); AddCycles(4+4); break; |
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| 176 | case ADD_IXYl : ADD(REGL); AddCycles(4+4); break; |
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| 177 | case ADC_IXYh : ADC(REGH); AddCycles(4+4); break; |
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| 178 | case ADC_IXYl : ADC(REGL); AddCycles(4+4); break; |
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| 179 | case SUB_IXYh : SUB(REGH); AddCycles(4+4); break; |
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| 180 | case SUB_IXYl : SUB(REGL); AddCycles(4+4); break; |
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| 181 | case SBC_IXYh : SBC(REGH); AddCycles(4+4); break; |
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| 182 | case SBC_IXYl : SBC(REGL); AddCycles(4+4); break; |
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| 183 | case AND_IXYh : AND(REGH); AddCycles(4+4); break; |
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| 184 | case AND_IXYl : AND(REGL); AddCycles(4+4); break; |
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| 185 | case XOR_IXYh : XOR(REGH); AddCycles(4+4); break; |
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| 186 | case XOR_IXYl : XOR(REGL); AddCycles(4+4); break; |
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| 187 | case OR_IXYh : OR(REGH); AddCycles(4+4); break; |
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| 188 | case OR_IXYl : OR(REGL); AddCycles(4+4); break; |
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| 189 | case CP_IXYh : CP(REGH); AddCycles(4+4); break; |
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| 190 | case CP_IXYl : CP(REGL); AddCycles(4+4); break; |
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| 191 | case INC_IXYh : INC(REGH); AddCycles(4+4); break; |
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| 192 | case INC_IXYl : INC(REGL); AddCycles(4+4); break; |
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| 193 | case DEC_IXYh : DEC(REGH); AddCycles(4+4); break; |
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| 194 | case DEC_IXYl : DEC(REGL); AddCycles(4+4); break; |
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| 195 | |||
| 196 | case LD_xIXY_H : r_meml =Z80ReadMem(r_PC); r_PC++; |
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| 197 | Z80WriteMem( REG+(offset)(r_meml), r_H, regs ); |
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| 198 | AddCycles( 4+3+3+3+3+3 ); break; |
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| 199 | case LD_xIXY_L : r_meml =Z80ReadMem(r_PC); r_PC++; |
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| 200 | Z80WriteMem( REG+(offset)(r_meml), r_L, regs ); |
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| 201 | AddCycles( 4+3+3+3+3+3 ); break; |
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| 202 | case LD_H_xIXY : r_meml =Z80ReadMem(r_PC); r_PC++; |
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| 203 | r_H = Z80ReadMem( REG+(offset)(r_meml)); |
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| 204 | AddCycles( 4+3+3+3+3+3 ); break; |
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| 205 | case LD_L_xIXY : r_meml =Z80ReadMem(r_PC); r_PC++; |
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| 206 | r_L = Z80ReadMem( REG+(offset)(r_meml)); |
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| 207 | AddCycles( 4+3+3+3+3+3 ); break; |
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| 208 | |||
| 209 | case PREFIX_CB: |
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| 210 | #include "opddfdcb.c" |
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| 211 | break; |
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| 212 | |||
| 213 | /* |
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| 214 | case PREFIX_DD: |
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| 215 | case PREFIX_FD: AddCycles( 4 ); |
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| 216 | r_PC--; // decode it the next time :) |
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| 217 | break; |
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| 218 | */ |
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| 219 | |||
| 220 | default: AddCycles( 4 ); |
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| 221 | r_PC--; /* decode it the next time :) */ |
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| 222 | SubR(1); |
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| 223 | |||
| 224 | // exit(1); |
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| 225 | // if( regs->DecodingErrors ) |
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| 226 | // { |
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| 227 | // printf("z80 core: Unknown instruction: "); |
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| 228 | // if ( regs->we_are_on_ddfd == WE_ARE_ON_DD ) |
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| 229 | // printf("DD "); |
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| 230 | // else |
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| 231 | // printf("FD "); |
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| 232 | // printf("%02Xh at PC=%04Xh.\n", Z80ReadMem(r_PC-1), r_PC-2 ); |
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| 233 | // } |
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| 234 | break; |
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| 235 | } |
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| 236 | |||
| 237 | #undef REG |
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| 238 | #undef REGL |
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| 239 | #undef REGH |