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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1814 | yogev_ezra | 1 | /*====================================================================/* |
| 2 | opcodes_cb.c -> This file executes the CB PREFIX opcodes. |
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| 3 | |||
| 4 | When you find the CB opcode, it means that you must fetch another |
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| 5 | byte from memory and treat it as a new opcode with different |
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| 6 | meaning than the single-byte opcodes. This is a common way to extend |
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| 7 | the number of opcodes (8 bits of instruction word = just 256 opcodes) |
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| 8 | and it's called an OPCODE PREFIX (now we have another 256 new opcodes |
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| 9 | by using this trick). |
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| 10 | |||
| 11 | This program is free software; you can redistribute it and/or modify |
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| 12 | it under the terms of the GNU General Public License as published by |
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| 13 | the Free Software Foundation; either version 2 of the License, or |
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| 14 | (at your option) any later version. |
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| 15 | |||
| 16 | This program is distributed in the hope that it will be useful, |
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| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 19 | GNU General Public License for more details. |
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| 20 | |||
| 21 | You should have received a copy of the GNU General Public License |
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| 22 | along with this program; if not, write to the Free Software |
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| 23 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 24 | |||
| 25 | Copyright (c) 2000 Santiago Romero Iglesias. |
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| 26 | Email: sromero@escomposlinux.org |
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| 27 | =====================================================================*/ |
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| 28 | |||
| 29 | /* 8 clock cycles minimum = CB opcode = 4+4 */ |
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| 30 | |||
| 31 | opcode = Z80ReadMem( r_PC ); |
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| 32 | r_PC++; |
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| 33 | |||
| 34 | switch(opcode) |
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| 35 | { |
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| 36 | |||
| 37 | case RLC_B : RLC(r_B); AddCycles( 4+4 ); break; |
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| 38 | case RLC_C : RLC(r_C); AddCycles( 4+4 ); break; |
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| 39 | case RLC_D : RLC(r_D); AddCycles( 4+4 ); break; |
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| 40 | case RLC_E : RLC(r_E); AddCycles( 4+4 ); break; |
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| 41 | case RLC_H : RLC(r_H); AddCycles( 4+4 ); break; |
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| 42 | case RLC_L : RLC(r_L); AddCycles( 4+4 ); break; |
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| 43 | case RLC_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 44 | RLC(r_meml); |
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| 45 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 46 | AddCycles( 4+4+3+3+1 ); break; |
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| 47 | case RLC_A : RLC(r_A); AddCycles( 4+4 ); break; |
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| 48 | |||
| 49 | case RRC_B : RRC(r_B); AddCycles( 4+4 ); break; |
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| 50 | case RRC_C : RRC(r_C); AddCycles( 4+4 ); break; |
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| 51 | case RRC_D : RRC(r_D); AddCycles( 4+4 ); break; |
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| 52 | case RRC_E : RRC(r_E); AddCycles( 4+4 ); break; |
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| 53 | case RRC_H : RRC(r_H); AddCycles( 4+4 ); break; |
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| 54 | case RRC_L : RRC(r_L); AddCycles( 4+4 ); break; |
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| 55 | case RRC_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 56 | RRC(r_meml); |
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| 57 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 58 | AddCycles( 4+4+3+3+1 ); break; |
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| 59 | case RRC_A : RRC(r_A); AddCycles( 4+4 ); break; |
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| 60 | |||
| 61 | case RL_B : RL(r_B); AddCycles( 4+4 ); break; |
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| 62 | case RL_C : RL(r_C); AddCycles( 4+4 ); break; |
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| 63 | case RL_D : RL(r_D); AddCycles( 4+4 ); break; |
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| 64 | case RL_E : RL(r_E); AddCycles( 4+4 ); break; |
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| 65 | case RL_H : RL(r_H); AddCycles( 4+4 ); break; |
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| 66 | case RL_L : RL(r_L); AddCycles( 4+4 ); break; |
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| 67 | case RL_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 68 | RL(r_meml); |
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| 69 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 70 | AddCycles( 4+4+3+3+1 ); break; |
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| 71 | case RL_A : RL(r_A); AddCycles( 4+4 ); break; |
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| 72 | |||
| 73 | case RR_B : RR(r_B); AddCycles( 4+4 ); break; |
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| 74 | case RR_C : RR(r_C); AddCycles( 4+4 ); break; |
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| 75 | case RR_D : RR(r_D); AddCycles( 4+4 ); break; |
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| 76 | case RR_E : RR(r_E); AddCycles( 4+4 ); break; |
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| 77 | case RR_H : RR(r_H); AddCycles( 4+4 ); break; |
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| 78 | case RR_L : RR(r_L); AddCycles( 4+4 ); break; |
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| 79 | case RR_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 80 | RR(r_meml); |
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| 81 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 82 | AddCycles( 4+4+3+3+1 ); break; |
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| 83 | case RR_A : RR(r_A); AddCycles( 4+4 ); break; |
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| 84 | |||
| 85 | case SLA_B : SLA(r_B); AddCycles( 4+4 ); break; |
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| 86 | case SLA_C : SLA(r_C); AddCycles( 4+4 ); break; |
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| 87 | case SLA_D : SLA(r_D); AddCycles( 4+4 ); break; |
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| 88 | case SLA_E : SLA(r_E); AddCycles( 4+4 ); break; |
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| 89 | case SLA_H : SLA(r_H); AddCycles( 4+4 ); break; |
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| 90 | case SLA_L : SLA(r_L); AddCycles( 4+4 ); break; |
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| 91 | case SLA_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 92 | SLA(r_meml); |
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| 93 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 94 | AddCycles( 4+4+3+3+1 ); break; |
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| 95 | case SLA_A : SLA(r_A); AddCycles( 4+4 ); break; |
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| 96 | |||
| 97 | case SRA_B : SRA(r_B); AddCycles( 4+4 ); break; |
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| 98 | case SRA_C : SRA(r_C); AddCycles( 4+4 ); break; |
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| 99 | case SRA_D : SRA(r_D); AddCycles( 4+4 ); break; |
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| 100 | case SRA_E : SRA(r_E); AddCycles( 4+4 ); break; |
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| 101 | case SRA_H : SRA(r_H); AddCycles( 4+4 ); break; |
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| 102 | case SRA_L : SRA(r_L); AddCycles( 4+4 ); break; |
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| 103 | case SRA_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 104 | SRA(r_meml); |
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| 105 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 106 | AddCycles( 4+4+3+3+1 ); break; |
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| 107 | case SRA_A : SRA(r_A); AddCycles( 4+4 ); break; |
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| 108 | |||
| 109 | case SLL_B : SLL(r_B); AddCycles( 4+4 ); break; |
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| 110 | case SLL_C : SLL(r_C); AddCycles( 4+4 ); break; |
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| 111 | case SLL_D : SLL(r_D); AddCycles( 4+4 ); break; |
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| 112 | case SLL_E : SLL(r_E); AddCycles( 4+4 ); break; |
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| 113 | case SLL_H : SLL(r_H); AddCycles( 4+4 ); break; |
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| 114 | case SLL_L : SLL(r_L); AddCycles( 4+4 ); break; |
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| 115 | case SLL_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 116 | SLL(r_meml); |
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| 117 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 118 | AddCycles( 4+4+3+3+1 ); break; |
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| 119 | case SLL_A : SLL(r_A); AddCycles( 4+4 ); break; |
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| 120 | |||
| 121 | case SRL_B : SRL(r_B); AddCycles( 4+4 ); break; |
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| 122 | case SRL_C : SRL(r_C); AddCycles( 4+4 ); break; |
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| 123 | case SRL_D : SRL(r_D); AddCycles( 4+4 ); break; |
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| 124 | case SRL_E : SRL(r_E); AddCycles( 4+4 ); break; |
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| 125 | case SRL_H : SRL(r_H); AddCycles( 4+4 ); break; |
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| 126 | case SRL_L : SRL(r_L); AddCycles( 4+4 ); break; |
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| 127 | case SRL_xHL : r_meml = Z80ReadMem( r_HL ); |
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| 128 | SRL(r_meml); |
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| 129 | Z80WriteMem( r_HL, r_meml, regs ); |
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| 130 | AddCycles( 4+4+3+3+1 ); break; |
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| 131 | case SRL_A : SRL(r_A); AddCycles( 4+4 ); break; |
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| 132 | |||
| 133 | case BIT_0_B : BIT_BIT(0, r_B); AddCycles( 4+4 ); break; |
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| 134 | case BIT_0_C : BIT_BIT(0, r_C); AddCycles( 4+4 ); break; |
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| 135 | case BIT_0_D : BIT_BIT(0, r_D); AddCycles( 4+4 ); break; |
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| 136 | case BIT_0_E : BIT_BIT(0, r_E); AddCycles( 4+4 ); break; |
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| 137 | case BIT_0_H : BIT_BIT(0, r_H); AddCycles( 4+4 ); break; |
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| 138 | case BIT_0_L : BIT_BIT(0, r_L); AddCycles( 4+4 ); break; |
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| 139 | case BIT_0_xHL : BIT_mem_BIT(0, r_HL); AddCycles( 12 ); break; |
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| 140 | case BIT_0_A : BIT_BIT(0, r_A); AddCycles( 4+4 ); break; |
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| 141 | |||
| 142 | case BIT_1_B : BIT_BIT(1, r_B); AddCycles( 4+4 ); break; |
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| 143 | case BIT_1_C : BIT_BIT(1, r_C); AddCycles( 4+4 ); break; |
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| 144 | case BIT_1_D : BIT_BIT(1, r_D); AddCycles( 4+4 ); break; |
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| 145 | case BIT_1_E : BIT_BIT(1, r_E); AddCycles( 4+4 ); break; |
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| 146 | case BIT_1_H : BIT_BIT(1, r_H); AddCycles( 4+4 ); break; |
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| 147 | case BIT_1_L : BIT_BIT(1, r_L); AddCycles( 4+4 ); break; |
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| 148 | case BIT_1_xHL : BIT_mem_BIT(1, r_HL); AddCycles( 12 ); break; |
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| 149 | case BIT_1_A : BIT_BIT(1, r_A); AddCycles( 4+4 ); break; |
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| 150 | |||
| 151 | case BIT_2_B : BIT_BIT(2, r_B); AddCycles( 4+4 ); break; |
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| 152 | case BIT_2_C : BIT_BIT(2, r_C); AddCycles( 4+4 ); break; |
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| 153 | case BIT_2_D : BIT_BIT(2, r_D); AddCycles( 4+4 ); break; |
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| 154 | case BIT_2_E : BIT_BIT(2, r_E); AddCycles( 4+4 ); break; |
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| 155 | case BIT_2_H : BIT_BIT(2, r_H); AddCycles( 4+4 ); break; |
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| 156 | case BIT_2_L : BIT_BIT(2, r_L); AddCycles( 4+4 ); break; |
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| 157 | case BIT_2_xHL : BIT_mem_BIT(2, r_HL); AddCycles( 12 ); break; |
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| 158 | case BIT_2_A : BIT_BIT(2, r_A); AddCycles( 4+4 ); break; |
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| 159 | |||
| 160 | case BIT_3_B : BIT_BIT(3, r_B); AddCycles( 4+4 ); break; |
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| 161 | case BIT_3_C : BIT_BIT(3, r_C); AddCycles( 4+4 ); break; |
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| 162 | case BIT_3_D : BIT_BIT(3, r_D); AddCycles( 4+4 ); break; |
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| 163 | case BIT_3_E : BIT_BIT(3, r_E); AddCycles( 4+4 ); break; |
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| 164 | case BIT_3_H : BIT_BIT(3, r_H); AddCycles( 4+4 ); break; |
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| 165 | case BIT_3_L : BIT_BIT(3, r_L); AddCycles( 4+4 ); break; |
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| 166 | case BIT_3_xHL : BIT_mem_BIT(3, r_HL); AddCycles( 12 ); break; |
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| 167 | case BIT_3_A : BIT_BIT(3, r_A); AddCycles( 4+4 ); break; |
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| 168 | |||
| 169 | case BIT_4_B : BIT_BIT(4, r_B); AddCycles( 4+4 ); break; |
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| 170 | case BIT_4_C : BIT_BIT(4, r_C); AddCycles( 4+4 ); break; |
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| 171 | case BIT_4_D : BIT_BIT(4, r_D); AddCycles( 4+4 ); break; |
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| 172 | case BIT_4_E : BIT_BIT(4, r_E); AddCycles( 4+4 ); break; |
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| 173 | case BIT_4_H : BIT_BIT(4, r_H); AddCycles( 4+4 ); break; |
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| 174 | case BIT_4_L : BIT_BIT(4, r_L); AddCycles( 4+4 ); break; |
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| 175 | case BIT_4_xHL : BIT_mem_BIT(4, r_HL); AddCycles( 12 ); break; |
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| 176 | case BIT_4_A : BIT_BIT(4, r_A); AddCycles( 4+4 ); break; |
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| 177 | |||
| 178 | case BIT_5_B : BIT_BIT(5, r_B); AddCycles( 4+4 ); break; |
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| 179 | case BIT_5_C : BIT_BIT(5, r_C); AddCycles( 4+4 ); break; |
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| 180 | case BIT_5_D : BIT_BIT(5, r_D); AddCycles( 4+4 ); break; |
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| 181 | case BIT_5_E : BIT_BIT(5, r_E); AddCycles( 4+4 ); break; |
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| 182 | case BIT_5_H : BIT_BIT(5, r_H); AddCycles( 4+4 ); break; |
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| 183 | case BIT_5_L : BIT_BIT(5, r_L); AddCycles( 4+4 ); break; |
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| 184 | case BIT_5_xHL : BIT_mem_BIT(5, r_HL); AddCycles( 12 ); break; |
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| 185 | case BIT_5_A : BIT_BIT(5, r_A); AddCycles( 4+4 ); break; |
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| 186 | |||
| 187 | case BIT_6_B : BIT_BIT(6, r_B); AddCycles( 4+4 ); break; |
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| 188 | case BIT_6_C : BIT_BIT(6, r_C); AddCycles( 4+4 ); break; |
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| 189 | case BIT_6_D : BIT_BIT(6, r_D); AddCycles( 4+4 ); break; |
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| 190 | case BIT_6_E : BIT_BIT(6, r_E); AddCycles( 4+4 ); break; |
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| 191 | case BIT_6_H : BIT_BIT(6, r_H); AddCycles( 4+4 ); break; |
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| 192 | case BIT_6_L : BIT_BIT(6, r_L); AddCycles( 4+4 ); break; |
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| 193 | case BIT_6_xHL : BIT_mem_BIT(6, r_HL); AddCycles( 12 ); break; |
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| 194 | case BIT_6_A : BIT_BIT(6, r_A); AddCycles( 4+4 ); break; |
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| 195 | |||
| 196 | case BIT_7_B : BIT_BIT7(r_B); AddCycles( 4+4 ); break; |
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| 197 | case BIT_7_C : BIT_BIT7(r_C); AddCycles( 4+4 ); break; |
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| 198 | case BIT_7_D : BIT_BIT7(r_D); AddCycles( 4+4 ); break; |
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| 199 | case BIT_7_E : BIT_BIT7(r_E); AddCycles( 4+4 ); break; |
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| 200 | case BIT_7_H : BIT_BIT7(r_H); AddCycles( 4+4 ); break; |
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| 201 | case BIT_7_L : BIT_BIT7(r_L); AddCycles( 4+4 ); break; |
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| 202 | case BIT_7_xHL : BIT_mem_BIT7(r_HL); AddCycles( 12 ); break; |
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| 203 | case BIT_7_A : BIT_BIT7(r_A); AddCycles( 4+4 ); break; |
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| 204 | |||
| 205 | case RES_0_B : BIT_RES(0, r_B); AddCycles( 4+4 ); break; |
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| 206 | case RES_0_C : BIT_RES(0, r_C); AddCycles( 4+4 ); break; |
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| 207 | case RES_0_D : BIT_RES(0, r_D); AddCycles( 4+4 ); break; |
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| 208 | case RES_0_E : BIT_RES(0, r_E); AddCycles( 4+4 ); break; |
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| 209 | case RES_0_H : BIT_RES(0, r_H); AddCycles( 4+4 ); break; |
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| 210 | case RES_0_L : BIT_RES(0, r_L); AddCycles( 4+4 ); break; |
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| 211 | case RES_0_xHL : BIT_mem_RES(0, r_HL); AddCycles( 4+4+7 ); break; |
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| 212 | case RES_0_A : BIT_RES(0, r_A); AddCycles( 4+4 ); break; |
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| 213 | |||
| 214 | case RES_1_B : BIT_RES(1, r_B); AddCycles( 4+4 ); break; |
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| 215 | case RES_1_C : BIT_RES(1, r_C); AddCycles( 4+4 ); break; |
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| 216 | case RES_1_D : BIT_RES(1, r_D); AddCycles( 4+4 ); break; |
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| 217 | case RES_1_E : BIT_RES(1, r_E); AddCycles( 4+4 ); break; |
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| 218 | case RES_1_H : BIT_RES(1, r_H); AddCycles( 4+4 ); break; |
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| 219 | case RES_1_L : BIT_RES(1, r_L); AddCycles( 4+4 ); break; |
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| 220 | case RES_1_xHL : BIT_mem_RES(1, r_HL); AddCycles( 4+4+7 ); break; |
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| 221 | case RES_1_A : BIT_RES(1, r_A); AddCycles( 4+4 ); break; |
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| 222 | |||
| 223 | case RES_2_B : BIT_RES(2, r_B); AddCycles( 4+4 ); break; |
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| 224 | case RES_2_C : BIT_RES(2, r_C); AddCycles( 4+4 ); break; |
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| 225 | case RES_2_D : BIT_RES(2, r_D); AddCycles( 4+4 ); break; |
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| 226 | case RES_2_E : BIT_RES(2, r_E); AddCycles( 4+4 ); break; |
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| 227 | case RES_2_H : BIT_RES(2, r_H); AddCycles( 4+4 ); break; |
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| 228 | case RES_2_L : BIT_RES(2, r_L); AddCycles( 4+4 ); break; |
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| 229 | case RES_2_xHL : BIT_mem_RES(2, r_HL); AddCycles( 4+4+7 ); break; |
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| 230 | case RES_2_A : BIT_RES(2, r_A); AddCycles( 4+4 ); break; |
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| 231 | |||
| 232 | case RES_3_B : BIT_RES(3, r_B); AddCycles( 4+4 ); break; |
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| 233 | case RES_3_C : BIT_RES(3, r_C); AddCycles( 4+4 ); break; |
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| 234 | case RES_3_D : BIT_RES(3, r_D); AddCycles( 4+4 ); break; |
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| 235 | case RES_3_E : BIT_RES(3, r_E); AddCycles( 4+4 ); break; |
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| 236 | case RES_3_H : BIT_RES(3, r_H); AddCycles( 4+4 ); break; |
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| 237 | case RES_3_L : BIT_RES(3, r_L); AddCycles( 4+4 ); break; |
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| 238 | case RES_3_xHL : BIT_mem_RES(3, r_HL); AddCycles( 4+4+7 ); break; |
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| 239 | case RES_3_A : BIT_RES(3, r_A); AddCycles( 4+4 ); break; |
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| 240 | |||
| 241 | case RES_4_B : BIT_RES(4, r_B); AddCycles( 4+4 ); break; |
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| 242 | case RES_4_C : BIT_RES(4, r_C); AddCycles( 4+4 ); break; |
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| 243 | case RES_4_D : BIT_RES(4, r_D); AddCycles( 4+4 ); break; |
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| 244 | case RES_4_E : BIT_RES(4, r_E); AddCycles( 4+4 ); break; |
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| 245 | case RES_4_H : BIT_RES(4, r_H); AddCycles( 4+4 ); break; |
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| 246 | case RES_4_L : BIT_RES(4, r_L); AddCycles( 4+4 ); break; |
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| 247 | case RES_4_xHL : BIT_mem_RES(4, r_HL); AddCycles( 4+4+7 ); break; |
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| 248 | case RES_4_A : BIT_RES(4, r_A); AddCycles( 4+4 ); break; |
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| 249 | |||
| 250 | case RES_5_B : BIT_RES(5, r_B); AddCycles( 4+4 ); break; |
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| 251 | case RES_5_C : BIT_RES(5, r_C); AddCycles( 4+4 ); break; |
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| 252 | case RES_5_D : BIT_RES(5, r_D); AddCycles( 4+4 ); break; |
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| 253 | case RES_5_E : BIT_RES(5, r_E); AddCycles( 4+4 ); break; |
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| 254 | case RES_5_H : BIT_RES(5, r_H); AddCycles( 4+4 ); break; |
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| 255 | case RES_5_L : BIT_RES(5, r_L); AddCycles( 4+4 ); break; |
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| 256 | case RES_5_xHL : BIT_mem_RES(5, r_HL); AddCycles( 4+4+7 ); break; |
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| 257 | case RES_5_A : BIT_RES(5, r_A); AddCycles( 4+4 ); break; |
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| 258 | |||
| 259 | case RES_6_B : BIT_RES(6, r_B); AddCycles( 4+4 ); break; |
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| 260 | case RES_6_C : BIT_RES(6, r_C); AddCycles( 4+4 ); break; |
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| 261 | case RES_6_D : BIT_RES(6, r_D); AddCycles( 4+4 ); break; |
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| 262 | case RES_6_E : BIT_RES(6, r_E); AddCycles( 4+4 ); break; |
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| 263 | case RES_6_H : BIT_RES(6, r_H); AddCycles( 4+4 ); break; |
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| 264 | case RES_6_L : BIT_RES(6, r_L); AddCycles( 4+4 ); break; |
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| 265 | case RES_6_xHL : BIT_mem_RES(6, r_HL); AddCycles( 4+4+7 ); break; |
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| 266 | case RES_6_A : BIT_RES(6, r_A); AddCycles( 4+4 ); break; |
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| 267 | |||
| 268 | case RES_7_B : BIT_RES(7, r_B); AddCycles( 4+4 ); break; |
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| 269 | case RES_7_C : BIT_RES(7, r_C); AddCycles( 4+4 ); break; |
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| 270 | case RES_7_D : BIT_RES(7, r_D); AddCycles( 4+4 ); break; |
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| 271 | case RES_7_E : BIT_RES(7, r_E); AddCycles( 4+4 ); break; |
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| 272 | case RES_7_H : BIT_RES(7, r_H); AddCycles( 4+4 ); break; |
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| 273 | case RES_7_L : BIT_RES(7, r_L); AddCycles( 4+4 ); break; |
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| 274 | case RES_7_xHL : BIT_mem_RES(7, r_HL); AddCycles( 4+4+7 ); break; |
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| 275 | case RES_7_A : BIT_RES(7, r_A); AddCycles( 4+4 ); break; |
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| 276 | |||
| 277 | case SET_0_B : BIT_SET(0, r_B); AddCycles( 4+4 ); break; |
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| 278 | case SET_0_C : BIT_SET(0, r_C); AddCycles( 4+4 ); break; |
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| 279 | case SET_0_D : BIT_SET(0, r_D); AddCycles( 4+4 ); break; |
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| 280 | case SET_0_E : BIT_SET(0, r_E); AddCycles( 4+4 ); break; |
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| 281 | case SET_0_H : BIT_SET(0, r_H); AddCycles( 4+4 ); break; |
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| 282 | case SET_0_L : BIT_SET(0, r_L); AddCycles( 4+4 ); break; |
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| 283 | case SET_0_xHL : BIT_mem_SET(0, r_HL); AddCycles( 4+4+7 ); break; |
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| 284 | case SET_0_A : BIT_SET(0, r_A); AddCycles( 4+4 ); break; |
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| 285 | |||
| 286 | case SET_1_B : BIT_SET(1, r_B); AddCycles( 4+4 ); break; |
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| 287 | case SET_1_C : BIT_SET(1, r_C); AddCycles( 4+4 ); break; |
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| 288 | case SET_1_D : BIT_SET(1, r_D); AddCycles( 4+4 ); break; |
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| 289 | case SET_1_E : BIT_SET(1, r_E); AddCycles( 4+4 ); break; |
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| 290 | case SET_1_H : BIT_SET(1, r_H); AddCycles( 4+4 ); break; |
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| 291 | case SET_1_L : BIT_SET(1, r_L); AddCycles( 4+4 ); break; |
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| 292 | case SET_1_xHL : BIT_mem_SET(1, r_HL); AddCycles( 4+4+7 ); break; |
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| 293 | case SET_1_A : BIT_SET(1, r_A); AddCycles( 4+4 ); break; |
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| 294 | |||
| 295 | case SET_2_B : BIT_SET(2, r_B); AddCycles( 4+4 ); break; |
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| 296 | case SET_2_C : BIT_SET(2, r_C); AddCycles( 4+4 ); break; |
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| 297 | case SET_2_D : BIT_SET(2, r_D); AddCycles( 4+4 ); break; |
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| 298 | case SET_2_E : BIT_SET(2, r_E); AddCycles( 4+4 ); break; |
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| 299 | case SET_2_H : BIT_SET(2, r_H); AddCycles( 4+4 ); break; |
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| 300 | case SET_2_L : BIT_SET(2, r_L); AddCycles( 4+4 ); break; |
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| 301 | case SET_2_xHL : BIT_mem_SET(2, r_HL); AddCycles( 4+4+7 ); break; |
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| 302 | case SET_2_A : BIT_SET(2, r_A); AddCycles( 4+4 ); break; |
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| 303 | |||
| 304 | case SET_3_B : BIT_SET(3, r_B); AddCycles( 4+4 ); break; |
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| 305 | case SET_3_C : BIT_SET(3, r_C); AddCycles( 4+4 ); break; |
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| 306 | case SET_3_D : BIT_SET(3, r_D); AddCycles( 4+4 ); break; |
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| 307 | case SET_3_E : BIT_SET(3, r_E); AddCycles( 4+4 ); break; |
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| 308 | case SET_3_H : BIT_SET(3, r_H); AddCycles( 4+4 ); break; |
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| 309 | case SET_3_L : BIT_SET(3, r_L); AddCycles( 4+4 ); break; |
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| 310 | case SET_3_xHL : BIT_mem_SET(3, r_HL); AddCycles( 4+4+7 ); break; |
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| 311 | case SET_3_A : BIT_SET(3, r_A); AddCycles( 4+4 ); break; |
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| 312 | |||
| 313 | case SET_4_B : BIT_SET(4, r_B); AddCycles( 4+4 ); break; |
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| 314 | case SET_4_C : BIT_SET(4, r_C); AddCycles( 4+4 ); break; |
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| 315 | case SET_4_D : BIT_SET(4, r_D); AddCycles( 4+4 ); break; |
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| 316 | case SET_4_E : BIT_SET(4, r_E); AddCycles( 4+4 ); break; |
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| 317 | case SET_4_H : BIT_SET(4, r_H); AddCycles( 4+4 ); break; |
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| 318 | case SET_4_L : BIT_SET(4, r_L); AddCycles( 4+4 ); break; |
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| 319 | case SET_4_xHL : BIT_mem_SET(4, r_HL); AddCycles( 4+4+7 ); break; |
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| 320 | case SET_4_A : BIT_SET(4, r_A); AddCycles( 4+4 ); break; |
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| 321 | |||
| 322 | case SET_5_B : BIT_SET(5, r_B); AddCycles( 4+4 ); break; |
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| 323 | case SET_5_C : BIT_SET(5, r_C); AddCycles( 4+4 ); break; |
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| 324 | case SET_5_D : BIT_SET(5, r_D); AddCycles( 4+4 ); break; |
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| 325 | case SET_5_E : BIT_SET(5, r_E); AddCycles( 4+4 ); break; |
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| 326 | case SET_5_H : BIT_SET(5, r_H); AddCycles( 4+4 ); break; |
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| 327 | case SET_5_L : BIT_SET(5, r_L); AddCycles( 4+4 ); break; |
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| 328 | case SET_5_xHL : BIT_mem_SET(5, r_HL); AddCycles( 4+4+7 ); break; |
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| 329 | case SET_5_A : BIT_SET(5, r_A); AddCycles( 4+4 ); break; |
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| 330 | |||
| 331 | case SET_6_B : BIT_SET(6, r_B); AddCycles( 4+4 ); break; |
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| 332 | case SET_6_C : BIT_SET(6, r_C); AddCycles( 4+4 ); break; |
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| 333 | case SET_6_D : BIT_SET(6, r_D); AddCycles( 4+4 ); break; |
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| 334 | case SET_6_E : BIT_SET(6, r_E); AddCycles( 4+4 ); break; |
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| 335 | case SET_6_H : BIT_SET(6, r_H); AddCycles( 4+4 ); break; |
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| 336 | case SET_6_L : BIT_SET(6, r_L); AddCycles( 4+4 ); break; |
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| 337 | case SET_6_xHL : BIT_mem_SET(6, r_HL); AddCycles( 4+4+7 ); break; |
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| 338 | case SET_6_A : BIT_SET(6, r_A); AddCycles( 4+4 ); break; |
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| 339 | |||
| 340 | case SET_7_B : BIT_SET(7, r_B); AddCycles( 4+4 ); break; |
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| 341 | case SET_7_C : BIT_SET(7, r_C); AddCycles( 4+4 ); break; |
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| 342 | case SET_7_D : BIT_SET(7, r_D); AddCycles( 4+4 ); break; |
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| 343 | case SET_7_E : BIT_SET(7, r_E); AddCycles( 4+4 ); break; |
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| 344 | case SET_7_H : BIT_SET(7, r_H); AddCycles( 4+4 ); break; |
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| 345 | case SET_7_L : BIT_SET(7, r_L); AddCycles( 4+4 ); break; |
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| 346 | case SET_7_xHL : BIT_mem_SET(7, r_HL); AddCycles( 4+4+7 ); break; |
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| 347 | case SET_7_A : BIT_SET(7, r_A); AddCycles( 4+4 ); break; |
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| 348 | |||
| 349 | default: |
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| 350 | // exit(1); |
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| 351 | ///!!! if( regs->DecodingErrors ) |
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| 352 | ///!!! printf("z80 core: Unknown instruction: CB %02Xh at PC=%04Xh.\n", |
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| 353 | ///!!! Z80ReadMem(r_PC-1), r_PC-2 ); |
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| 354 | break; |
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| 355 | } |
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| 356 |