WebSVN – Kolibri OS – Blame – /kernel/trunk/drivers/r500hw.inc

Rev	Author	Line No.	Line
729	serge	1	if 0
		2
		3	Copyright 2008 Serge
		4
		5	The below code is a rework from code in
		6	xf86-video-radeonhd/src/r5xx_accel.c, xf86-video-radeonhd/src/r5xx_xaa.c
		7
		8	Copyright 2008 Luc Verhaegen
		9	Copyright 2008 Matthias Hopf
		10	Copyright 2008 Egbert Eich
		11	Copyright 2008 Advanced Micro Devices, Inc.
		12
		13	Permission is hereby granted, free of charge, to any person obtaining a
		14	copy of this software and associated documentation files (the "Software"),
		15	to deal in the Software without restriction, including without limitation
		16	the rights to use, copy, modify, merge, publish, distribute, sublicense,
		17	and/or sell copies of the Software, and to permit persons to whom the
		18	Software is furnished to do so, subject to the following conditions:
		19
		20	The above copyright notice and this permission notice shall be included in
		21	all copies or substantial portions of the Software.
		22
		23	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		24	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		25	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		26	THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		27	OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		28	ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		29	OTHER DEALINGS IN THE SOFTWARE.
		30
		31	The below code is a rework from code in xf86-video-ati/src/radeon_accel.c
		32	The original license is included below, it has the messed up disclaimer and
		33	an all rights reserved statement.
		34
		35
		36	Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
		37	VA Linux Systems Inc., Fremont, California.
		38
		39	All Rights Reserved.
		40
		41	Permission is hereby granted, free of charge, to any person obtaining
		42	a copy of this software and associated documentation files (the
		43	"Software"), to deal in the Software without restriction, including
		44	without limitation on the rights to use, copy, modify, merge,
		45	publish, distribute, sublicense, and/or sell copies of the Software,
		46	and to permit persons to whom the Software is furnished to do so,
		47	subject to the following conditions:
		48
		49	The above copyright notice and this permission notice (including the
		50	next paragraph) shall be included in all copies or substantial
		51	portions of the Software.
		52
		53	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		54	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		55	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		56	NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
		57	THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
		58	WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		59	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		60	DEALINGS IN THE SOFTWARE.
		61
		62	Authors:
		63	Kevin E. Martin
		64	Rickard E. Faith
		65	Alan Hourihane
		66
		67	end if
		68
732	serge	69	D1GRPH_PITCH equ 0x6120
729	serge	70
		71	R5XX_DATATYPE_ARGB8888 equ 6
		72
		73	R5XX_RB3D_CNTL equ 0x1c3c
		74
		75	R5XX_RBBM_STATUS equ 0x0e40
		76	R5XX_RBBM_FIFOCNT_MASK equ 0x007f
		77	R5XX_RBBM_ACTIVE equ (1 shl 31)
		78
		79	R5XX_RBBM_SOFT_RESET equ 0x00f0
		80	R5XX_SOFT_RESET_CP equ (1 shl 0)
		81	R5XX_SOFT_RESET_HI equ (1 shl 1)
		82	R5XX_SOFT_RESET_SE equ (1 shl 2)
		83	R5XX_SOFT_RESET_RE equ (1 shl 3)
		84	R5XX_SOFT_RESET_PP equ (1 shl 4)
		85	R5XX_SOFT_RESET_E2 equ (1 shl 5)
		86	R5XX_SOFT_RESET_RB equ (1 shl 6)
		87	R5XX_SOFT_RESET_HDP equ (1 shl 7)
		88
		89	R5XX_SRC_PITCH_OFFSET equ 0x1428
		90	R5XX_DST_PITCH_OFFSET equ 0x142c
		91
		92	R5XX_DP_DATATYPE equ 0x16c4
		93	R5XX_HOST_BIG_ENDIAN_EN equ (1 shl 29)
		94
		95	R5XX_DP_CNTL equ 0x16c0
		96	R5XX_DST_X_LEFT_TO_RIGHT equ (1 shl 0)
		97	R5XX_DST_Y_TOP_TO_BOTTOM equ (1 shl 1)
		98	R5XX_DP_DST_TILE_LINEAR equ (0 shl 3)
		99	R5XX_DP_DST_TILE_MACRO equ (1 shl 3)
		100	R5XX_DP_DST_TILE_MICRO equ (2 shl 3)
		101	R5XX_DP_DST_TILE_BOTH equ (3 shl 3)
		102
		103
		104	R5XX_RB3D_DSTCACHE_CTLSTAT equ 0x325C
		105	R5XX_RB3D_DC_FLUSH equ (3 shl 0)
		106	R5XX_RB3D_DC_FREE equ (3 shl 2)
		107	R5XX_RB3D_DC_FLUSH_ALL equ 0xf
		108	R5XX_RB3D_DC_BUSY equ (1 shl 31)
		109
		110	R5XX_SURFACE_CNTL equ 0x0b00
		111	R5XX_SURF_TRANSLATION_DIS equ (1 shl 8)
		112	R5XX_NONSURF_AP0_SWP_16BPP equ (1 shl 20)
		113	R5XX_NONSURF_AP0_SWP_32BPP equ (1 shl 21)
		114	R5XX_NONSURF_AP1_SWP_16BPP equ (1 shl 22)
		115	R5XX_NONSURF_AP1_SWP_32BPP equ (1 shl 23)
		116
		117	R5XX_DEFAULT_SC_BOTTOM_RIGHT equ 0x16e8
		118	R5XX_DEFAULT_SC_RIGHT_MAX equ (0x1fff shl 0)
		119	R5XX_DEFAULT_SC_BOTTOM_MAX equ (0x1fff shl 16)
		120
		121	R5XX_SC_TOP_LEFT equ 0x16ec
		122	R5XX_SC_BOTTOM_RIGHT equ 0x16f0
		123	R5XX_SC_SIGN_MASK_LO equ 0x8000
		124	R5XX_SC_SIGN_MASK_HI equ 0x80000000
		125
		126	R5XX_DP_GUI_MASTER_CNTL equ 0x146c
		127	R5XX_GMC_SRC_PITCH_OFFSET_CNTL equ (1 shl 0)
		128	R5XX_GMC_DST_PITCH_OFFSET_CNTL equ (1 shl 1)
		129	R5XX_GMC_SRC_CLIPPING equ (1 shl 2)
		130	R5XX_GMC_DST_CLIPPING equ (1 shl 3)
		131	R5XX_GMC_BRUSH_DATATYPE_MASK equ (0x0f shl 4)
		132	R5XX_GMC_BRUSH_8X8_MONO_FG_BG equ (0 shl 4)
		133	R5XX_GMC_BRUSH_8X8_MONO_FG_LA equ (1 shl 4)
		134	R5XX_GMC_BRUSH_1X8_MONO_FG_BG equ (4 shl 4)
		135	R5XX_GMC_BRUSH_1X8_MONO_FG_LA equ (5 shl 4)
		136	R5XX_GMC_BRUSH_32x1_MONO_FG_BG equ (6 shl 4)
		137	R5XX_GMC_BRUSH_32x1_MONO_FG_LA equ (7 shl 4)
		138	R5XX_GMC_BRUSH_32x32_MONO_FG_BG equ (8 shl 4)
		139	R5XX_GMC_BRUSH_32x32_MONO_FG_LA equ (9 shl 4)
		140	R5XX_GMC_BRUSH_8x8_COLOR equ (10 shl 4)
		141	R5XX_GMC_BRUSH_1X8_COLOR equ (12 shl 4)
		142	R5XX_GMC_BRUSH_SOLID_COLOR equ (13 shl 4)
		143	R5XX_GMC_BRUSH_NONE equ (15 shl 4)
		144	R5XX_GMC_DST_8BPP_CI equ (2 shl 8)
		145	R5XX_GMC_DST_15BPP equ (3 shl 8)
		146	R5XX_GMC_DST_16BPP equ (4 shl 8)
		147	R5XX_GMC_DST_24BPP equ (5 shl 8)
		148	R5XX_GMC_DST_32BPP equ (6 shl 8)
		149	R5XX_GMC_DST_8BPP_RGB equ (7 shl 8)
		150	R5XX_GMC_DST_Y8 equ (8 shl 8)
		151	R5XX_GMC_DST_RGB8 equ (9 shl 8)
		152	R5XX_GMC_DST_VYUY equ (11 shl 8)
		153	R5XX_GMC_DST_YVYU equ (12 shl 8)
		154	R5XX_GMC_DST_AYUV444 equ (14 shl 8)
		155	R5XX_GMC_DST_ARGB4444 equ (15 shl 8)
		156	R5XX_GMC_DST_DATATYPE_MASK equ (0x0f shl 8)
		157	R5XX_GMC_DST_DATATYPE_SHIFT equ 8
		158	R5XX_GMC_SRC_DATATYPE_MASK equ (3 shl 12)
		159	R5XX_GMC_SRC_DATATYPE_MONO_FG_BG equ (0 shl 12)
		160	R5XX_GMC_SRC_DATATYPE_MONO_FG_LA equ (1 shl 12)
		161	R5XX_GMC_SRC_DATATYPE_COLOR equ (3 shl 12)
		162	R5XX_GMC_BYTE_PIX_ORDER equ (1 shl 14)
		163	R5XX_GMC_BYTE_MSB_TO_LSB equ (0 shl 14)
		164	R5XX_GMC_BYTE_LSB_TO_MSB equ (1 shl 14)
		165	R5XX_GMC_CONVERSION_TEMP equ (1 shl 15)
		166	R5XX_GMC_CONVERSION_TEMP_6500 equ (0 shl 15)
		167	R5XX_GMC_CONVERSION_TEMP_9300 equ (1 shl 15)
		168	R5XX_GMC_ROP3_MASK equ (0xff shl 16)
		169	R5XX_DP_SRC_SOURCE_MASK equ (7 shl 24)
		170	R5XX_DP_SRC_SOURCE_MEMORY equ (2 shl 24)
		171	R5XX_DP_SRC_SOURCE_HOST_DATA equ (3 shl 24)
		172	R5XX_GMC_3D_FCN_EN equ (1 shl 27)
		173	R5XX_GMC_CLR_CMP_CNTL_DIS equ (1 shl 28)
		174	R5XX_GMC_AUX_CLIP_DIS equ (1 shl 29)
		175	R5XX_GMC_WR_MSK_DIS equ (1 shl 30)
		176	R5XX_GMC_LD_BRUSH_Y_X equ (1 shl 31)
		177	R5XX_ROP3_ZERO equ 0x00000000
		178	R5XX_ROP3_DSa equ 0x00880000
		179	R5XX_ROP3_SDna equ 0x00440000
		180	R5XX_ROP3_S equ 0x00cc0000
		181	R5XX_ROP3_DSna equ 0x00220000
		182	R5XX_ROP3_D equ 0x00aa0000
		183	R5XX_ROP3_DSx equ 0x00660000
		184	R5XX_ROP3_DSo equ 0x00ee0000
		185	R5XX_ROP3_DSon equ 0x00110000
		186	R5XX_ROP3_DSxn equ 0x00990000
		187	R5XX_ROP3_Dn equ 0x00550000
		188	R5XX_ROP3_SDno equ 0x00dd0000
		189	R5XX_ROP3_Sn equ 0x00330000
		190	R5XX_ROP3_DSno equ 0x00bb0000
		191	R5XX_ROP3_DSan equ 0x00770000
		192	R5XX_ROP3_ONE equ 0x00ff0000
		193	R5XX_ROP3_DPa equ 0x00a00000
		194	R5XX_ROP3_PDna equ 0x00500000
		195	R5XX_ROP3_P equ 0x00f00000
		196	R5XX_ROP3_DPna equ 0x000a0000
		197	R5XX_ROP3_D equ 0x00aa0000
		198	R5XX_ROP3_DPx equ 0x005a0000
		199	R5XX_ROP3_DPo equ 0x00fa0000
		200	R5XX_ROP3_DPon equ 0x00050000
		201	R5XX_ROP3_PDxn equ 0x00a50000
		202	R5XX_ROP3_PDno equ 0x00f50000
		203	R5XX_ROP3_Pn equ 0x000f0000
		204	R5XX_ROP3_DPno equ 0x00af0000
		205	R5XX_ROP3_DPan equ 0x005f0000
		206
		207	R5XX_HOST_PATH_CNTL equ 0x0130
		208	R5XX_HDP_SOFT_RESET equ (1 shl 26)
		209	R5XX_HDP_APER_CNTL equ (1 shl 23)
		210
		211	R5XX_RB3D_DSTCACHE_MODE equ 0x3258
		212	R5XX_RB3D_DC_CACHE_ENABLE equ (0)
		213	R5XX_RB3D_DC_2D_CACHE_DISABLE equ (1)
		214	R5XX_RB3D_DC_3D_CACHE_DISABLE equ (2)
		215	R5XX_RB3D_DC_CACHE_DISABLE equ (3)
		216	R5XX_RB3D_DC_2D_CACHE_LINESIZE_128 equ (1 shl 2)
		217	R5XX_RB3D_DC_3D_CACHE_LINESIZE_128 equ (2 shl 2)
		218	R5XX_RB3D_DC_2D_CACHE_AUTOFLUSH equ (1 shl 8)
		219	R5XX_RB3D_DC_3D_CACHE_AUTOFLUSH equ (2 shl 8)
		220	R200_RB3D_DC_2D_CACHE_AUTOFREE equ (1 shl 10)
		221	R200_RB3D_DC_3D_CACHE_AUTOFREE equ (2 shl 10)
		222	R5XX_RB3D_DC_FORCE_RMW equ (1 shl 16)
		223	R5XX_RB3D_DC_DISABLE_RI_FILL equ (1 shl 24)
		224	R5XX_RB3D_DC_DISABLE_RI_READ equ (1 shl 25)
		225
		226	R5XX_BRUSH_Y_X equ 0x1474
		227	R5XX_DP_BRUSH_BKGD_CLR equ 0x1478
		228	R5XX_DP_BRUSH_FRGD_CLR equ 0x147c
		229	R5XX_BRUSH_DATA0 equ 0x1480
		230	R5XX_BRUSH_DATA1 equ 0x1484
		231
732	serge	232	R5XX_SRC_Y_X equ 0x1434
		233
		234	R5XX_DST_Y_X equ 0x1438
		235	R5XX_DST_HEIGHT_WIDTH equ 0x143c
729	serge	236	R5XX_DST_WIDTH_HEIGHT equ 0x1598
		237
732	serge	238	R5XX_DST_LINE_START equ 0x1600
		239	R5XX_DST_LINE_END equ 0x1604
		240	R5XX_DST_LINE_PATCOUNT equ 0x1608
		241	R5XX_BRES_CNTL_SHIFT equ 8
		242
		243
729	serge	244	R5XX_DP_SRC_BKGD_CLR equ 0x15dc
		245	R5XX_DP_SRC_FRGD_CLR equ 0x15d8
		246
		247	R5XX_DP_WRITE_MASK equ 0x16cc
		248
		249	struc RHD
		250	{
		251	.control rd 1
		252	.control_saved rd 1
		253	.datatype rd 1
		254	.surface_cntl rd 1
		255	.dst_pitch_offset rd 1
		256	};
		257
		258	R5XX_LOOP_COUNT equ 2000000
		259
		260	align 4
		261	R5xxFIFOWaitLocal:
		262
		263	mov ecx, R5XX_LOOP_COUNT
		264	@@:
		265	rdr ebx, R5XX_RBBM_STATUS
		266	and ebx, R5XX_RBBM_FIFOCNT_MASK
		267
		268	cmp eax, ebx
		269	jbe .done
		270	loop @B
		271
		272	mov esi, msgR5xxFIFOWaitLocaltimeout
		273	call SysMsgBoardStr
		274	xor eax, eax
		275	ret
		276	.done:
		277	mov eax, 1
		278	ret
		279
		280	align 4
		281	R5xxFIFOWait:
		282	call R5xxFIFOWaitLocal
		283	test eax, eax
		284	jz .reset
		285
		286	ret
		287	.reset:
		288	call R5xx2DReset
		289	call R5xx2DSetup
		290
		291	ret
		292
		293
		294	; Wait for the graphics engine to be completely idle: the FIFO has
		295	; drained, the Pixel Cache is flushed, and the engine is idle. This is
		296	; a standard "sync" function that will make the hardware "quiescent".
		297
		298	align 4
		299	R5xx2DIdleLocal:
		300
		301	mov ecx, R5XX_LOOP_COUNT
		302	@@:
		303	rdr eax, R5XX_RBBM_STATUS
		304	and eax, R5XX_RBBM_FIFOCNT_MASK
		305	cmp eax, 0x40
		306	je @F
		307	loop @B
		308
		309	mov esi, msgR5xx2DIdleLocaltimeout
		310	call SysMsgBoardStr
		311	xor eax, eax
		312	ret
		313	@@:
		314	mov ecx, R5XX_LOOP_COUNT
		315	@@:
		316	rdr eax, R5XX_RBBM_STATUS
		317	test eax, R5XX_RBBM_ACTIVE
		318	jz .done
		319	loop @B
		320
		321	mov esi, msgR5xx2DIdleLocaltimeout
		322	call SysMsgBoardStr
		323	xor eax, eax
		324	ret
		325	.done:
		326	call R5xx2DFlush
		327	ret
		328
		329	align 4
		330	R5xx2DFlush:
		331	rmask R5XX_RB3D_DSTCACHE_CTLSTAT, R5XX_RB3D_DC_FLUSH_ALL, R5XX_RB3D_DC_FLUSH_ALL
		332
		333	mov ecx, R5XX_LOOP_COUNT
		334	@@:
		335	rdr eax, R5XX_RB3D_DSTCACHE_CTLSTAT
		336	test eax, R5XX_RB3D_DC_BUSY
		337	jz .done
		338	loop @B
		339	.fail:
		340	mov esi, msgR5xx2DFlushtimeout
		341	call SysMsgBoardStr
		342	xor eax, eax
		343	ret
		344	.done:
		345	mov eax, 1
		346	ret
		347
		348	align 4
		349	proc R5xx2DReset
		350	locals
		351	save rd 1
		352	tmp rd 1
		353	endl
		354
		355	; The following RBBM_SOFT_RESET sequence can help un-wedge
		356	; an R300 after the command processor got stuck.
		357
		358	rdr eax, R5XX_RBBM_SOFT_RESET
		359	mov [save], eax
		360
		361	or eax, R5XX_SOFT_RESET_CP or \
		362	R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_SE or \
		363	R5XX_SOFT_RESET_RE or R5XX_SOFT_RESET_PP or \
		364	R5XX_SOFT_RESET_E2 or R5XX_SOFT_RESET_RB
		365	mov [tmp], eax
		366
		367	; RHDRegWrite(rhdPtr, R5XX_RBBM_SOFT_RESET, tmp);
		368	wrr R5XX_RBBM_SOFT_RESET, eax
		369
		370	; RHDRegRead(rhdPtr, R5XX_RBBM_SOFT_RESET);
		371	rdr ebx, R5XX_RBBM_SOFT_RESET
		372	and eax, not (R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or \
		373	R5XX_SOFT_RESET_SE or R5XX_SOFT_RESET_RE or \
		374	R5XX_SOFT_RESET_PP or R5XX_SOFT_RESET_E2 or \
		375	R5XX_SOFT_RESET_RB)
		376	; RHDRegWrite(rhdPtr, R5XX_RBBM_SOFT_RESET, tmp);
		377	wrr R5XX_RBBM_SOFT_RESET, eax
		378	; RHDRegRead(rhdPtr, R5XX_RBBM_SOFT_RESET);
		379	rdr ebx, R5XX_RBBM_SOFT_RESET
		380	; RHDRegWrite(rhdPtr, R5XX_RBBM_SOFT_RESET, save);
		381	mov eax, [save]
		382	wrr R5XX_RBBM_SOFT_RESET, eax
		383	; RHDRegRead(rhdPtr, R5XX_RBBM_SOFT_RESET);
		384	rdr ebx, R5XX_RBBM_SOFT_RESET
		385	; R5xx2DFlush(rhdPtr->scrnIndex);
		386	call R5xx2DFlush
		387
		388	; Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
		389	; unexpected behaviour on some machines. Here we use
		390	; R5XX_HOST_PATH_CNTL to reset it.
		391
		392	; save = RHDRegRead(rhdPtr, R5XX_HOST_PATH_CNTL);
		393	rdr edx, R5XX_HOST_PATH_CNTL
		394
		395	; tmp = RHDRegRead(rhdPtr, R5XX_RBBM_SOFT_RESET);
		396	rdr ebx, R5XX_RBBM_SOFT_RESET
		397
		398	; tmp \|= R5XX_SOFT_RESET_CP \| R5XX_SOFT_RESET_HI \| R5XX_SOFT_RESET_E2;
		399	or ebx, R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_E2
		400
		401	; RHDRegWrite(rhdPtr, R5XX_RBBM_SOFT_RESET, tmp);
		402	wrr R5XX_RBBM_SOFT_RESET, ebx
		403
		404	; RHDRegRead(rhdPtr, R5XX_RBBM_SOFT_RESET);
		405	rdr eax, R5XX_RBBM_SOFT_RESET
		406
		407	; RHDRegWrite(rhdPtr, R5XX_RBBM_SOFT_RESET, 0);
		408	wrr R5XX_RBBM_SOFT_RESET, 0
		409
		410	; tmp = RHDRegRead(rhdPtr, R5XX_RB3D_DSTCACHE_MODE);
		411	rdr ebx, R5XX_RB3D_DSTCACHE_MODE
		412
		413	; RHDRegWrite(rhdPtr, R5XX_RB3D_DSTCACHE_MODE, tmp \| (1 << 17)); /* FIXME */
		414	or ebx, (1 shl 17)
		415	wrr R5XX_RB3D_DSTCACHE_MODE, ebx
		416
		417	; RHDRegWrite(rhdPtr, R5XX_HOST_PATH_CNTL, save \| R5XX_HDP_SOFT_RESET);
		418	lea eax, [edx+R5XX_HDP_SOFT_RESET]
		419	wrr R5XX_HOST_PATH_CNTL, eax
		420
		421	; RHDRegRead(rhdPtr, R5XX_HOST_PATH_CNTL);
		422	rdr ebx, R5XX_HOST_PATH_CNTL
		423
		424	; RHDRegWrite(rhdPtr, R5XX_HOST_PATH_CNTL, save);
		425	wrr R5XX_HOST_PATH_CNTL, edx
		426
		427	ret
		428	endp
		429
		430	align 4
		431	R5xx2DSetup:
		432
		433	; Setup engine location. This shouldn't be necessary since we
		434	; set them appropriately before any accel ops, but let's avoid
		435	; random bogus DMA in case we inadvertently trigger the engine
		436	; in the wrong place (happened).
		437
		438	; R5xxFIFOWaitLocal(rhdPtr->scrnIndex, 2);
		439	mov eax, 2
		440	call R5xxFIFOWaitLocal
		441
		442	; RHDRegWrite(rhdPtr, R5XX_DST_PITCH_OFFSET, TwoDInfo->dst_pitch_offset);
		443	mov eax, [rhd.dst_pitch_offset]
		444	wrr R5XX_DST_PITCH_OFFSET, eax
		445
		446	; RHDRegWrite(rhdPtr, R5XX_SRC_PITCH_OFFSET, TwoDInfo->dst_pitch_offset);
		447	wrr R5XX_SRC_PITCH_OFFSET, eax
		448
		449	; R5xxFIFOWaitLocal(rhdPtr->scrnIndex, 1);
		450	mov eax, 1
		451	call R5xxFIFOWaitLocal
		452
		453	; RHDRegMask(rhdPtr, R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
		454	rmask R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN
		455
		456	; RHDRegWrite(rhdPtr, R5XX_SURFACE_CNTL, TwoDInfo->surface_cntl);
		457	mov eax, [rhd.surface_cntl]
		458	wrr R5XX_SURFACE_CNTL, eax
		459
		460	; R5xxFIFOWaitLocal(rhdPtr->scrnIndex, 1);
		461	mov eax, 1
		462	call R5xxFIFOWaitLocal
		463
		464	; RHDRegWrite(rhdPtr, R5XX_DEFAULT_SC_BOTTOM_RIGHT,
		465	; R5XX_DEFAULT_SC_RIGHT_MAX \| R5XX_DEFAULT_SC_BOTTOM_MAX);
		466	wrr R5XX_DEFAULT_SC_BOTTOM_RIGHT,\
		467	(R5XX_DEFAULT_SC_RIGHT_MAX or R5XX_DEFAULT_SC_BOTTOM_MAX)
		468
		469	; R5xxFIFOWaitLocal(rhdPtr->scrnIndex, 1);
		470	mov eax, 1
		471	call R5xxFIFOWaitLocal
		472
		473	; RHDRegWrite(rhdPtr, R5XX_DP_GUI_MASTER_CNTL, TwoDInfo->control \|
		474	; R5XX_GMC_BRUSH_SOLID_COLOR \| R5XX_GMC_SRC_DATATYPE_COLOR);
		475	mov eax, [rhd.control]
		476	or eax, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		477	wrr R5XX_DP_GUI_MASTER_CNTL, eax
		478
		479	; R5xxFIFOWaitLocal(rhdPtr->scrnIndex, 5);
		480	mov eax, 5
		481	call R5xxFIFOWaitLocal
		482
		483	; RHDRegWrite(rhdPtr, R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
		484	wrr R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF
		485
		486	; RHDRegWrite(rhdPtr, R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
		487	wrr R5XX_DP_BRUSH_BKGD_CLR, 0x00000000
		488
		489	; RHDRegWrite(rhdPtr, R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
		490	wrr R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF
		491	; RHDRegWrite(rhdPtr, R5XX_DP_SRC_BKGD_CLR, 0x00000000);
		492	wrr R5XX_DP_SRC_BKGD_CLR, 0x00000000
		493	; RHDRegWrite(rhdPtr, R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
		494	wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		495
		496	; R5xx2DIdleLocal(rhdPtr->scrnIndex);
		497	call R5xx2DIdleLocal
		498	ret
		499
		500	align 4
		501	R5xx2DPreInit:
		502
		503	mov [rhd.control], (R5XX_DATATYPE_ARGB8888 shl R5XX_GMC_DST_DATATYPE_SHIFT) or\
		504	R5XX_GMC_CLR_CMP_CNTL_DIS or R5XX_GMC_DST_PITCH_OFFSET_CNTL
		505
		506	mov [rhd.datatype], R5XX_DATATYPE_ARGB8888
		507	mov [rhd.surface_cntl],0
		508
732	serge	509	rdr eax, D1GRPH_PITCH
		510	shl eax, 18
		511
		512	mov ebx, [r500_LFB]
		513	shr ebx, 10
		514	or eax, ebx
		515
		516	; or eax, ((1024*4)/64) shl 22
729	serge	517	mov [rhd.dst_pitch_offset], eax
		518
		519	ret
		520
		521	align 4
		522	R5xx2DInit:
		523
		524	call R5xx2DPreInit
		525	wrr R5XX_RB3D_CNTL, 0
		526	call R5xx2DReset
		527	call R5xx2DSetup
		528	ret
		529
		530	proc R5xxSetupForSolidFill stdcall,color:dword, rop:dword, planemask:dword
		531
		532	mov edx, [rop]
		533	mov edx, [R5xxRops+4+edx*8]
		534	or edx, [rhd.control]
		535	or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		536
		537	; Save for later clipping */
		538	mov [rhd.control_saved], edx
		539
		540	mov eax, 4
		541	call R5xxFIFOWait
		542
		543	; RHDRegWrite(pScrn, R5XX_DP_GUI_MASTER_CNTL, control);
		544	wrr R5XX_DP_GUI_MASTER_CNTL, edx
		545
		546	; RHDRegWrite(pScrn, R5XX_DP_BRUSH_FRGD_CLR, color);
		547	mov eax, [color]
		548	wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		549
		550	; RHDRegWrite(pScrn, R5XX_DP_WRITE_MASK, planemask);
		551	mov ebx, [planemask]
		552	wrr R5XX_DP_WRITE_MASK, ebx
		553
		554	; RHDRegWrite(pScrn, R5XX_DP_CNTL,
		555	; R5XX_DST_X_LEFT_TO_RIGHT \| R5XX_DST_Y_TOP_TO_BOTTOM);
		556	wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
		557
		558	ret
		559	endp
		560
		561	align 4
		562	proc R5xxSolidFillRect stdcall, x:dword, y:dword, w:dword, h:dword
		563
		564	mov eax, 3
		565	call R5xxFIFOWait
		566
		567	mov eax, [rhd.dst_pitch_offset]
		568	wrr R5XX_DST_PITCH_OFFSET, eax
		569
		570	mov ebx, [y]
		571	shl ebx, 16
		572	mov bx, word [x]
		573	wrr R5XX_DST_Y_X, ebx
		574
		575	mov ecx, [w]
		576	shl ecx, 16
		577	mov cx, word [h]
		578	wrr R5XX_DST_WIDTH_HEIGHT, ecx
		579
		580	ret
		581	endp
		582
732	serge	583	handle equ IOCTL.handle
		584	io_code equ IOCTL.io_code
		585	input equ IOCTL.input
		586	inp_size equ IOCTL.inp_size
		587	output equ IOCTL.output
		588	out_size equ IOCTL.out_size
729	serge	589
732	serge	590	SRV_GETVERSION equ 0
		591	SOLID_FILL equ 1
		592	LINE_2P equ 2
		593
		594	align 4
		595	proc r500_entry stdcall, state:dword
		596
		597	.close:
		598	; call r500_close
		599
		600	xor eax, eax
		601	ret
		602	endp
		603
		604	align 4
		605	proc r500_HDraw stdcall, ioctl:dword
		606
		607	mov ebx, [ioctl]
		608	mov eax, [ebx+io_code]
		609	cmp eax, LINE_2P
		610	ja .fail
		611
		612	cmp eax, SRV_GETVERSION
		613	jne @F
		614
		615	mov eax, [ebx+output]
		616	cmp [ebx+out_size], 4
		617	jne .fail
		618	mov [eax], dword API_VERSION
		619	xor eax, eax
		620	ret
		621	@@:
		622	cmp eax, SOLID_FILL
		623	jne @F
		624
		625	cmp [ebx+inp_size], 5
		626	jne .fail
		627
		628	mov esi, [ebx+input]
		629	call solid_fill
		630	xor eax, eax
		631	ret
		632	@@:
		633	cmp eax, LINE_2P
		634	jne @F
		635
		636	cmp [ebx+inp_size], 5
		637	jne .fail
		638
		639	mov esi, [ebx+input]
		640	call solid_line
		641	xor eax, eax
		642	ret
		643	@@:
		644
		645	.fail:
		646	or eax, -1
		647	ret
		648	endp
		649
		650	restore handle
		651	restore io_code
		652	restore input
		653	restore inp_size
		654	restore output
		655	restore out_size
		656
		657	struc FILL
		658	{
		659	.color rd 1
		660	.x rd 1
		661	.y rd 1
		662	.w rd 1
		663	.h rd 1
		664	}
		665
		666	virtual at 0
		667	FILL FILL
		668	end virtual
		669
		670	struc LINE2P
		671	{
		672	.color rd 1
		673	.x1 rd 1
		674	.y1 rd 1
		675	.x2 rd 1
		676	.y2 rd 1
		677	}
		678
		679	virtual at 0
		680	LINE2P LINE2P
		681	end virtual
		682
		683	GXcopy equ 3
		684
		685	; esi= input params
		686	align 4
		687	solid_fill:
		688
		689	mov edx, [R5xxRops+4+GXcopy*8]
		690	or edx, [rhd.control]
		691	or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		692
		693	mov eax, 7
		694	call R5xxFIFOWait
		695
		696	wrr R5XX_DP_GUI_MASTER_CNTL, edx
		697
		698	mov eax, [esi+FILL.color]
		699	wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		700
		701	wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		702
		703	wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
		704
		705	mov eax, [rhd.dst_pitch_offset]
		706	wrr R5XX_DST_PITCH_OFFSET, eax
		707
		708	mov ebx, [esi+FILL.y]
		709	shl ebx, 16
		710	mov bx, word [esi+FILL.x]
		711	wrr R5XX_DST_Y_X, ebx
		712
		713	mov ecx, [esi+FILL.w]
		714	shl ecx, 16
		715	mov cx, word [esi+FILL.h]
		716	wrr R5XX_DST_WIDTH_HEIGHT, ecx
		717
		718	ret
		719
		720	align 4
		721	solid_line:
		722
		723	mov eax, 7
		724	call R5xxFIFOWait
		725
		726	mov edx, [R5xxRops+4+GXcopy*8]
		727	or edx, [rhd.control]
		728	or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		729
		730	wrr R5XX_DST_LINE_PATCOUNT, (0x55 shl R5XX_BRES_CNTL_SHIFT)
		731	wrr R5XX_DP_GUI_MASTER_CNTL, edx
		732
		733	mov eax, [esi+FILL.color]
		734	wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		735
		736	wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		737
		738	mov eax, [rhd.dst_pitch_offset]
		739	wrr R5XX_DST_PITCH_OFFSET, eax
		740
		741	mov ebx, [esi+LINE2P.y1]
		742	shl ebx, 16
		743	mov bx, word [esi+LINE2P.x1]
		744	wrr R5XX_DST_LINE_START, ebx
		745
		746	mov ecx, [esi+LINE2P.y2]
		747	shl ecx, 16
		748	mov cx, word [esi+LINE2P.x2]
		749	wrr R5XX_DST_LINE_END, ecx
		750
		751	ret

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(root)/kernel/trunk/drivers/r500hw.inc – Rev 732