Rev 1554 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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1472 | hidnplayr | 1 | ; PCI Bus defines |
2 | PCI_HEADER_TYPE equ 0x0e ;8 bit |
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3 | PCI_BASE_ADDRESS_0 equ 0x10 ;32 bit |
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4 | PCI_BASE_ADDRESS_5 equ 0x24 ;32 bits |
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5 | PCI_BASE_ADDRESS_SPACE_IO equ 0x01 |
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6 | PCI_VENDOR_ID equ 0x00 ;16 bit |
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7 | PCI_BASE_ADDRESS_IO_MASK equ 0xFFFFFFFC |
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8 | |||
9 | |||
10 | ; PCI programming |
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11 | PCI_REG_COMMAND equ 0x4 ; command register |
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12 | PCI_REG_STATUS equ 0x6 ; status register |
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13 | PCI_REG_LATENCY equ 0xd ; latency timer register |
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14 | PCI_REG_CAP_PTR equ 0x34 ; capabilities pointer |
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15 | PCI_REG_CAPABILITY_ID equ 0x0 ; capapility ID in pm register block |
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16 | PCI_REG_PM_STATUS equ 0x4 ; power management status register |
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17 | PCI_REG_PM_CTRL equ 0x4 ; power management control register |
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1502 | hidnplayr | 18 | PCI_BIT_PIO equ 1 ; bit0: io space control |
19 | PCI_BIT_MMIO equ 2 ; bit1: memory space control |
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20 | PCI_BIT_MASTER equ 4 ; bit2: device acts as a PCI master |
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1472 | hidnplayr | 21 | |
22 | |||
1556 | hidnplayr | 23 | ; Kernel variables |
1472 | hidnplayr | 24 | |
1556 | hidnplayr | 25 | PAGESIZE equ 4096 |
26 | PG_SW equ 0x003 |
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1472 | hidnplayr | 27 | |
1556 | hidnplayr | 28 | |
1514 | hidnplayr | 29 | ; network driver types |
1472 | hidnplayr | 30 | |
1514 | hidnplayr | 31 | NET_TYPE_ETH equ 1 |
32 | NET_TYPE_SLIP equ 2 |
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33 | |||
34 | |||
35 | |||
1472 | hidnplayr | 36 | LAST_IO = 0 |
37 | |||
38 | macro set_io addr { |
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39 | |||
40 | if addr = 0 |
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41 | mov edx, [device.io_addr] |
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42 | else if addr = LAST_IO |
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43 | else |
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44 | add edx, addr - LAST_IO |
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45 | end if |
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46 | |||
47 | LAST_IO = addr |
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48 | } |
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49 | |||
50 | macro allocate_and_clear dest, size, err { |
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51 | |||
52 | ; We need to allocate at least 8 pages, if we want a continuous memory in ram |
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1521 | hidnplayr | 53 | push edx |
1472 | hidnplayr | 54 | if (size < 8*4096) & (size > 4096) |
55 | stdcall KernelAlloc, 8*4096 |
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56 | else |
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57 | stdcall KernelAlloc, size |
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58 | end if |
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1521 | hidnplayr | 59 | pop edx |
60 | |||
1472 | hidnplayr | 61 | test eax, eax |
62 | jz err |
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63 | mov dest, eax ; Save the address to it into the device struct |
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64 | mov edi, eax ; look at last part of code! |
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65 | |||
66 | ; Release the unused pages (if any) |
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67 | if (size < 8*4096) & (size > 4096) |
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68 | add eax, (size/4096+1)*4096 |
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69 | mov ecx, 8-(size/4096+1) |
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1521 | hidnplayr | 70 | push edx |
1472 | hidnplayr | 71 | call ReleasePages |
1521 | hidnplayr | 72 | pop edx |
1472 | hidnplayr | 73 | end if |
74 | |||
75 | ; Clear the allocated buffer |
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76 | mov ecx, size/4 ; divide by 4 because of DWORD |
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77 | xor eax, eax |
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78 | rep stosd |
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79 | |||
80 | } |
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81 | |||
82 | macro find_io bus, dev, io { |
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83 | |||
84 | local .check, .inc, .got |
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85 | |||
86 | xor eax, eax |
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87 | mov esi, PCI_BASE_ADDRESS_0 |
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88 | movzx ecx, bus |
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89 | movzx edx, dev |
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90 | .check: |
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1502 | hidnplayr | 91 | stdcall PciRead32, ecx ,edx ,esi |
1472 | hidnplayr | 92 | |
1502 | hidnplayr | 93 | test eax, PCI_BASE_ADDRESS_IO_MASK |
1472 | hidnplayr | 94 | jz .inc |
95 | |||
1502 | hidnplayr | 96 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
1472 | hidnplayr | 97 | jz .inc |
98 | |||
99 | and eax, PCI_BASE_ADDRESS_IO_MASK |
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100 | mov io , eax |
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101 | jmp .got |
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102 | |||
103 | .inc: |
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104 | add esi, 4 |
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105 | cmp esi, PCI_BASE_ADDRESS_5 |
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1502 | hidnplayr | 106 | jle .check |
1472 | hidnplayr | 107 | |
108 | .got: |
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109 | |||
110 | } |
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111 | |||
1492 | hidnplayr | 112 | macro find_irq bus, dev, irq { |
1472 | hidnplayr | 113 | |
1492 | hidnplayr | 114 | push eax edx ecx |
115 | movzx ecx, bus |
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116 | movzx edx, dev |
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117 | stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found |
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118 | mov irq, al |
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119 | pop ecx edx eax |
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1472 | hidnplayr | 120 | |
1492 | hidnplayr | 121 | } |
122 | |||
1502 | hidnplayr | 123 | macro find_rev bus, dev, rev { |
1492 | hidnplayr | 124 | |
1502 | hidnplayr | 125 | push eax edx ecx |
126 | movzx ecx, bus |
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127 | movzx edx, dev |
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128 | stdcall PciRead8, ecx ,edx ,0x8 |
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129 | mov rev, al |
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130 | pop ecx edx eax |
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131 | |||
132 | } |
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133 | |||
1472 | hidnplayr | 134 | macro make_bus_master bus, dev { |
135 | |||
136 | movzx ecx, bus |
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137 | movzx edx, dev |
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1554 | hidnplayr | 138 | stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND |
1472 | hidnplayr | 139 | |
1554 | hidnplayr | 140 | or al, PCI_BIT_MASTER ;or PCI_BIT_PIO |
141 | ; and al, not PCI_BIT_MMIO |
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142 | stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax |
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1472 | hidnplayr | 143 | |
1554 | hidnplayr | 144 | ;; TODO: try to switch to PIO, and check if PIO works or not.. |
1514 | hidnplayr | 145 | |
1472 | hidnplayr | 146 | } |
147 | |||
148 | struc IOCTL { |
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149 | .handle dd ? |
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150 | .io_code dd ? |
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151 | .input dd ? |
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152 | .inp_size dd ? |
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153 | .output dd ? |
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154 | .out_size dd ? |
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155 | } |
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156 | |||
157 | virtual at edx |
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158 | IOCTL IOCTL |
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159 | end virtual |
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160 | |||
161 | |||
162 | if used null_op |
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163 | align 4 |
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164 | null_op: |
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165 | or eax, -1 |
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166 | ret |
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167 | |||
168 | end if |
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169 | |||
170 | |||
1556 | hidnplayr | 171 | macro GetRealAddr { ; input and output is eax |
1472 | hidnplayr | 172 | |
173 | push ax |
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1529 | hidnplayr | 174 | call GetPgAddr |
1472 | hidnplayr | 175 | and word[esp], PAGESIZE - 1 |
176 | or ax, word[esp] |
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177 | inc esp |
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178 | inc esp |
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179 | |||
1492 | hidnplayr | 180 | } |
181 | |||
1514 | hidnplayr | 182 | macro NET_DEVICE { |
1519 | hidnplayr | 183 | |
184 | .type dd ? ; Type field |
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185 | .mtu dd ? ; Maximal Transmission Unit |
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186 | .name dd ? ; Ptr to 0 terminated string |
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187 | |||
188 | .unload dd ? ; Ptrs to driver functions |
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189 | .reset dd ? ; |
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190 | .transmit dd ? ; |
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191 | |||
192 | .bytes_tx dq ? ; Statistics, updated by the driver |
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193 | .bytes_rx dq ? ; |
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194 | .packets_tx dd ? ; |
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195 | .packets_rx dd ? ; |
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196 | |||
197 | .end: |
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1514 | hidnplayr | 198 | } |
1492 | hidnplayr | 199 | |
1529 | hidnplayr | 200 | |
1492 | hidnplayr | 201 | macro ETH_DEVICE { |
1514 | hidnplayr | 202 | NET_DEVICE |
1519 | hidnplayr | 203 | |
204 | .set_mode dd ? |
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205 | .get_mode dd ? |
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206 | |||
207 | .set_MAC dd ? |
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208 | .get_MAC dd ? |
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209 | |||
210 | .mode dd ? |
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211 | .mac dp ? |
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212 | dp ? ; qword alignment |
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213 | |||
1492 | hidnplayr | 214 | } |
215 | |||
1502 | hidnplayr | 216 | |
217 | |||
218 | macro SLIP_DEVICE { |
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1514 | hidnplayr | 219 | NET_DEVICE |
1519 | hidnplayr | 220 | |
1502 | hidnplayr | 221 | .set_mode dd ? |
222 | .get_mode dd ? |
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1519 | hidnplayr | 223 | |
1502 | hidnplayr | 224 | .mode dd ? |
1519 | hidnplayr | 225 | |
1529 | hidnplayr | 226 | }>> |