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Rev | Author | Line No. | Line |
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1472 | hidnplayr | 1 | ; PCI Bus defines |
2 | PCI_HEADER_TYPE equ 0x0e ;8 bit |
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3 | PCI_BASE_ADDRESS_0 equ 0x10 ;32 bit |
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4 | PCI_BASE_ADDRESS_5 equ 0x24 ;32 bits |
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5 | PCI_BASE_ADDRESS_SPACE_IO equ 0x01 |
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6 | PCI_VENDOR_ID equ 0x00 ;16 bit |
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7 | PCI_BASE_ADDRESS_IO_MASK equ 0xFFFFFFFC |
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8 | |||
9 | |||
10 | ; PCI programming |
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11 | PCI_REG_COMMAND equ 0x4 ; command register |
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12 | PCI_REG_STATUS equ 0x6 ; status register |
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13 | PCI_REG_LATENCY equ 0xd ; latency timer register |
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14 | PCI_REG_CAP_PTR equ 0x34 ; capabilities pointer |
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15 | PCI_REG_CAPABILITY_ID equ 0x0 ; capapility ID in pm register block |
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16 | PCI_REG_PM_STATUS equ 0x4 ; power management status register |
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17 | PCI_REG_PM_CTRL equ 0x4 ; power management control register |
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1502 | hidnplayr | 18 | PCI_BIT_PIO equ 1 ; bit0: io space control |
19 | PCI_BIT_MMIO equ 2 ; bit1: memory space control |
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20 | PCI_BIT_MASTER equ 4 ; bit2: device acts as a PCI master |
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1472 | hidnplayr | 21 | |
22 | |||
23 | PAGESIZE equ 4096 |
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24 | |||
25 | |||
26 | |||
27 | LAST_IO = 0 |
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28 | |||
29 | macro set_io addr { |
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30 | |||
31 | if addr = 0 |
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32 | |||
33 | mov edx, [device.io_addr] |
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34 | |||
35 | else if addr = LAST_IO |
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36 | |||
37 | else |
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38 | |||
39 | add edx, addr - LAST_IO |
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40 | |||
41 | end if |
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42 | |||
43 | LAST_IO = addr |
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44 | } |
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45 | |||
46 | |||
47 | |||
48 | macro allocate_and_clear dest, size, err { |
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49 | |||
50 | ; We need to allocate at least 8 pages, if we want a continuous memory in ram |
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51 | if (size < 8*4096) & (size > 4096) |
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52 | stdcall KernelAlloc, 8*4096 |
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53 | else |
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54 | stdcall KernelAlloc, size |
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55 | end if |
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56 | test eax, eax |
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57 | jz err |
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58 | mov dest, eax ; Save the address to it into the device struct |
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59 | mov edi, eax ; look at last part of code! |
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60 | |||
61 | ; Release the unused pages (if any) |
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62 | if (size < 8*4096) & (size > 4096) |
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63 | add eax, (size/4096+1)*4096 |
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64 | mov ecx, 8-(size/4096+1) |
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65 | call ReleasePages |
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66 | end if |
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67 | |||
68 | ; Clear the allocated buffer |
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69 | mov ecx, size/4 ; divide by 4 because of DWORD |
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70 | xor eax, eax |
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71 | rep stosd |
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72 | |||
73 | } |
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74 | |||
75 | |||
76 | |||
77 | macro find_io bus, dev, io { |
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78 | |||
79 | local .check, .inc, .got |
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80 | |||
81 | xor eax, eax |
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82 | mov esi, PCI_BASE_ADDRESS_0 |
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83 | movzx ecx, bus |
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84 | movzx edx, dev |
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85 | .check: |
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1502 | hidnplayr | 86 | stdcall PciRead32, ecx ,edx ,esi |
1472 | hidnplayr | 87 | |
1502 | hidnplayr | 88 | test eax, PCI_BASE_ADDRESS_IO_MASK |
1472 | hidnplayr | 89 | jz .inc |
90 | |||
1502 | hidnplayr | 91 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
1472 | hidnplayr | 92 | jz .inc |
93 | |||
94 | and eax, PCI_BASE_ADDRESS_IO_MASK |
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95 | mov io , eax |
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96 | jmp .got |
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97 | |||
98 | .inc: |
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99 | add esi, 4 |
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100 | cmp esi, PCI_BASE_ADDRESS_5 |
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1502 | hidnplayr | 101 | jle .check |
1472 | hidnplayr | 102 | |
103 | .got: |
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104 | |||
105 | } |
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106 | |||
1492 | hidnplayr | 107 | macro find_irq bus, dev, irq { |
1472 | hidnplayr | 108 | |
1492 | hidnplayr | 109 | push eax edx ecx |
110 | movzx ecx, bus |
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111 | movzx edx, dev |
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112 | stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found |
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113 | mov irq, al |
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114 | pop ecx edx eax |
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1472 | hidnplayr | 115 | |
1492 | hidnplayr | 116 | } |
117 | |||
118 | |||
1502 | hidnplayr | 119 | macro find_rev bus, dev, rev { |
1492 | hidnplayr | 120 | |
1502 | hidnplayr | 121 | push eax edx ecx |
122 | movzx ecx, bus |
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123 | movzx edx, dev |
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124 | stdcall PciRead8, ecx ,edx ,0x8 |
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125 | mov rev, al |
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126 | pop ecx edx eax |
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127 | |||
128 | } |
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129 | |||
130 | |||
131 | |||
1472 | hidnplayr | 132 | macro make_bus_master bus, dev { |
133 | |||
134 | movzx ecx, bus |
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135 | movzx edx, dev |
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1492 | hidnplayr | 136 | stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND |
1472 | hidnplayr | 137 | |
1502 | hidnplayr | 138 | or al, PCI_BIT_MASTER or PCI_BIT_PIO |
139 | and al, not PCI_BIT_MMIO |
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1472 | hidnplayr | 140 | stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax |
141 | |||
142 | } |
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143 | |||
144 | struc IOCTL { |
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145 | .handle dd ? |
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146 | .io_code dd ? |
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147 | .input dd ? |
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148 | .inp_size dd ? |
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149 | .output dd ? |
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150 | .out_size dd ? |
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151 | } |
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152 | |||
153 | virtual at edx |
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154 | IOCTL IOCTL |
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155 | end virtual |
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156 | |||
157 | |||
158 | |||
159 | |||
160 | if used null_op |
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161 | |||
162 | align 4 |
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163 | null_op: |
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164 | or eax, -1 |
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165 | ret |
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166 | |||
167 | end if |
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168 | |||
169 | |||
170 | macro virt_to_dma { ; input is eax |
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171 | |||
172 | push ax |
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173 | and word[esp], PAGESIZE - 1 |
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174 | call GetPgAddr |
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175 | or ax, word[esp] |
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176 | inc esp |
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177 | inc esp |
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178 | |||
1492 | hidnplayr | 179 | } |
180 | |||
181 | |||
182 | ;struc ETH_DEVICE { |
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183 | macro ETH_DEVICE { |
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184 | ; pointers to procedures |
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185 | .unload dd ? |
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186 | .reset dd ? |
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187 | .transmit dd ? |
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188 | .set_MAC dd ? |
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189 | .get_MAC dd ? |
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190 | .set_mode dd ? |
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191 | .get_mode dd ? |
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192 | ; status |
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193 | .bytes_tx dq ? |
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194 | .bytes_rx dq ? |
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195 | .packets_tx dd ? |
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196 | .packets_rx dd ? |
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197 | .mode dd ? |
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198 | .name dd ? |
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199 | .mac dp ? |
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200 | } |
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201 | |||
1502 | hidnplayr | 202 | |
203 | |||
204 | macro SLIP_DEVICE { |
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205 | ; pointers to procedures |
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206 | .unload dd ? |
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207 | .reset dd ? |
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208 | .transmit dd ? |
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209 | .set_mode dd ? |
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210 | .get_mode dd ? |
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211 | ; status |
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212 | .bytes_tx dq ? |
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213 | .bytes_rx dq ? |
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214 | .packets_tx dd ? |
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215 | .packets_rx dd ? |
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216 | .mode dd ? |
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217 | .name dd ? |
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218 | } |
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219 | |||
220 | macro GetRealAddr { |
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221 | |||
222 | push eax |
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223 | call GetPgAddr |
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224 | and dword [esp], (PAGESIZE - 1) |
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225 | add eax, dword [esp] |
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226 | add esp, 4 |
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227 | |||
228 | }>> |
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229 |