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1472 hidnplayr 1 
; PCI Bus defines
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	PCI_HEADER_TYPE 		equ	0x0e  ;8 bit
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	PCI_BASE_ADDRESS_0		equ	0x10  ;32 bit
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	PCI_BASE_ADDRESS_5		equ	0x24  ;32 bits
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	PCI_BASE_ADDRESS_SPACE_IO	equ	0x01
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	PCI_VENDOR_ID			equ	0x00  ;16 bit
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	PCI_BASE_ADDRESS_IO_MASK	equ	0xFFFFFFFC
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; PCI programming
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	PCI_REG_COMMAND 	equ 0x4 ; command register
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	PCI_REG_STATUS		equ 0x6 ; status register
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	PCI_REG_LATENCY 	equ 0xd ; latency timer register
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	PCI_REG_CAP_PTR 	equ 0x34 ; capabilities pointer
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	PCI_REG_CAPABILITY_ID	equ 0x0 ; capapility ID in pm register block
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	PCI_REG_PM_STATUS	equ 0x4 ; power management status register
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	PCI_REG_PM_CTRL 	equ 0x4 ; power management control register
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	PCI_BIT_PIO		equ 0 ; bit0: io space control
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	PCI_BIT_MMIO		equ 1 ; bit1: memory space control
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	PCI_BIT_MASTER		equ 2 ; bit2: device acts as a PCI master
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	PAGESIZE		equ	4096
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	LAST_IO = 0
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macro set_io addr {
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	if	addr = 0
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	mov	edx, [device.io_addr]
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	else if addr = LAST_IO
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	else
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	add	edx, addr - LAST_IO
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	end if
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	LAST_IO = addr
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}
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macro diff16 title,l1,l2
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{
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  local s,d
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  s = l2-l1
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  display title,': 0x'
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  repeat 16
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    d = 48 + s shr ((16-%) shl 2) and $0F
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    if d > 57
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      d = d + 65-57-1
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    end if
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    display d
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  end repeat
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  display 13,10
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}
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macro allocate_and_clear dest, size, err {
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; We need to allocate at least 8 pages, if we want a continuous memory in ram
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    if (size < 8*4096) & (size > 4096)
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	stdcall KernelAlloc, 8*4096
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    else
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	stdcall KernelAlloc, size
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    end if
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	test	eax, eax
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	jz	err
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	mov	dest, eax		; Save the address to it into the device struct
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	mov	edi, eax		; look at last part of code!
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; Release the unused pages (if any)
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    if (size < 8*4096) & (size > 4096)
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	add	eax, (size/4096+1)*4096
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	mov	ecx, 8-(size/4096+1)
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	call	ReleasePages
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    end if
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; Clear the allocated buffer
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	;mov     edi, eax
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	mov	ecx, size/4		; divide by 4 because of DWORD
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	xor	eax, eax
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	rep	stosd
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}
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macro find_io bus, dev, io {
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	local	.check, .inc, .got
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	xor	eax, eax
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	mov	esi, PCI_BASE_ADDRESS_0
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	movzx	ecx, bus
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	movzx	edx, dev
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  .check:
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	stdcall PciRead16, ecx ,edx ,esi
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	mov	io , eax
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	and	eax, PCI_BASE_ADDRESS_IO_MASK
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	test	eax, eax
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	jz	.inc
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	mov	eax, io
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	and	eax, PCI_BASE_ADDRESS_SPACE_IO
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	test	eax, eax
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	jz	.inc
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	mov	eax, io
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	and	eax, PCI_BASE_ADDRESS_IO_MASK
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	mov	io , eax
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	jmp	.got
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  .inc:
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	add	esi, 4
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	cmp	esi, PCI_BASE_ADDRESS_5
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	jbe	.check
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  .got:
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}
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macro make_bus_master bus, dev {
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	movzx	ecx, bus
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	movzx	edx, dev
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	stdcall PciRead32, ecx ,edx ,PCI_REG_COMMAND
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	or	al, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)
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	and	al, not (1 shl PCI_BIT_MMIO)
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	stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
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}
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struc IOCTL {
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      .handle		dd ?
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      .io_code		dd ?
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      .input		dd ?
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      .inp_size 	dd ?
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      .output		dd ?
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      .out_size 	dd ?
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}
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virtual at edx
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  IOCTL IOCTL
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end virtual
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if used null_op
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align 4
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null_op:
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	or	eax, -1
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	ret
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end if
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macro virt_to_dma { ; input is eax
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	push	ax
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	and	word[esp], PAGESIZE - 1
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	call	GetPgAddr
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	or	ax, word[esp]
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	inc	esp
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	inc	esp
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}