Subversion Repositories Kolibri OS

;;                                                              ;;

;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;

;; Distributed under terms of the GNU General Public License    ;;

;;                                                              ;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

include "../proc32.inc"

include "../const.inc"

sel_os_stack    equ  0x18

sel_app_data    equ  0x2B

sel_srv_stack   equ  0x39

public _pg_balloc

public cpu_sign

public cpu_info

public cpu_caps

extrn _16bit_end

extrn _enter_bootscreen

extrn init_idt

extrn _init_mm

extrn _slab_cache_init

extrn @init_heap@8

extrn init_malloc

extrn _init_core_dll

extrn _init_threads

extrn init_mtrr

extrn system_init

extrn syscall_entry

extrn _current_thread

extrn _k_reenter:dword

extrn LFBAddress:dword

extrn LFBSize:dword

           mov dx, sel_app_data

           mov ss, ax

           mov esp, __os_stack

           mov es, dx

           mov fs, dx

           mov gs, dx

         ;  jnc @F

         ;  or ebx, CR4_PGE

         ;  mov cr4, ebx

@@:

         ;  mov eax, cr3

         ;  mov cr3, eax           ; flush TLB

           mov eax, 3

           out dx, al

           call _parse_mbi

        ;   mov [_copy_pg_balloc], eax

           mov ecx, _16bit_end

           shr ecx, 2

           mov edi, _16BIT_BASE

           cld

           rep movsd

core_init:

           cld

           mov dx, sel_app_data

           mov ss, ax

           mov esp, __os_stack

           mov es, dx

           mov fs, dx

           mov gs, dx

           mov [tss._esp0], __os_stack

           mov [tss._esp], __os_stack

           mov [tss._cs], sel_os_code

           mov [tss._ss], sel_os_stack

           mov [tss._ds], sel_app_data

           mov [tss._es], sel_app_data

           mov [tss._fs], sel_app_data

           mov [tss._gs], sel_app_data

           mov [tss._io], 128

;Add IO access table - bit array of permitted ports

           mov edi, tss._io_map_0

           xor eax, eax

       ;    not eax

           mov ecx, 8192/4

           rep stosd             ; access to 4096*8=65536 ports

           ltr ax

; Intel SYSENTER/SYSEXIT (AMD CPU support it too)

	   bt [cpu_caps], CAPS_SEP

	   jnc .SEnP   ; SysEnter not Present

	   mov ecx, MSR_SYSENTER_CS

       mov eax, sel_os_code

	   wrmsr

	   mov ecx, MSR_SYSENTER_ESP

;           mov eax, sysenter_stack ; Check it

	   xor	   eax, eax

	   wrmsr

	   mov ecx, MSR_SYSENTER_EIP

	   mov eax, sysenter_entry

	   wrmsr

; AMD SYSCALL/SYSRET

	   cmp byte[cpu_vendor], 'A'

	   jne .noSYSCALL

	   mov eax, 0x80000001

	   cpuid

	   test edx, 0x800  ; bit_11 - SYSCALL/SYSRET support

	   jz .noSYSCALL

	   mov ecx, MSR_AMD_EFER

	   rdmsr

	   or eax, 1   ; bit_0 - System Call Extension (SCE)

	   wrmsr

; Bit 31–16 During the SYSRET instruction, this field is copied into the CS register

;  and the contents of this field, plus 8, are copied into the SS register.

; Bit 15–0 During the SYSCALL instruction, this field is copied into the CS register

;  and the contents of this field, plus 8, are copied into the SS register.

	   mov ecx, MSR_AMD_STAR

	   wrmsr

.noSYSCALL:

           call _slab_cache_init

           mov edx, 0x40000000

           call @init_heap@8

           call _init_threads

           mov dword [_sys_pdbr+4], eax

           mov   [scr_mode],eax

           call map_LFB

           mov cr3, eax

           mov ecx, system_init

           call @create_systhread@4

           mov ecx, cr3

           cmp ebx, ecx

           je .skip

           mov cr3, ebx

.skip:

           mov esp, [_current_thread]

        ;   lea eax, [esp+THR.pl0_stack]

        ;   mov [tss._esp0], eax

restart1:

           dec [_k_reenter]

           popad

           add esp, 4                 ; skip return adr

           iretd                      ; continue process

end if

map_LFB:

           cmp eax, -1

           jne @f

@@:

           test [scr_mode], 0100000000000000b

           jnz @f

           mov [BOOT_VAR+0x901c],byte 2

           ret

@@:

           mov [LFBAddress], eax

           mov [LFBSize], 0x800000

           call init_mtrr

           or eax, PG_LARGE+PG_UW

           mov [_sys_pdbr+(LFB_BASE shr 20)], eax

           add eax, 0x00400000

           mov [_sys_pdbr+4+(LFB_BASE shr 20)], eax

if SHADOWFB

           mov ecx, 11

           call @core_alloc@4

           or eax, PG_LARGE+PG_UW

           mov [_sys_pdbr+(SHADOWFB shr 20)], eax

           add eax, 0x00400000

           mov [_sys_pdbr+4+(SHADOWFB shr 20)], eax

end if

           jnc @F

           or dword [_sys_pdbr+(LFB_BASE shr 20)], PG_GLOBAL

@@:

           mov dword [LFBAddress], LFB_BASE

           ret

proc test_cpu

           locals

              cpu_type   dd ?

              cpu_id     dd ?

              cpu_Intel  dd ?

              cpu_AMD    dd ?

           endl

           xor eax, eax

           mov [cpu_caps], eax

           mov [cpu_caps+4], eax

           cpuid

           mov [cpu_vendor+4], edx

           mov [cpu_vendor+8], ecx

           cmp ebx, dword [intel_str]

           jne .check_AMD

           cmp edx, dword [intel_str+4]

           jne .check_AMD

           cmp ecx, dword [intel_str+8]

           jne .check_AMD

           mov [cpu_Intel], 1

           cmp eax, 1

           jl .end_cpuid

           mov eax, 1

           cpuid

           mov [cpu_sign], eax

           mov [cpu_info],  ebx

           mov [cpu_caps],  edx

           mov [cpu_caps+4],ecx

           and eax, 0x0f

           ret

.end_cpuid:

           mov eax, [cpu_type]

           ret

           cmp ebx, dword [AMD_str]

           jne .unknown

           cmp edx, dword [AMD_str+4]

           jne .unknown

           cmp ecx, dword [AMD_str+8]

           jne .unknown

           mov [cpu_AMD], 1

           cmp eax, 1

           jl .unknown

           mov eax, 1

           cpuid

           mov [cpu_sign], eax

           mov [cpu_info],  ebx

           mov [cpu_caps],  edx

           mov [cpu_caps+4],ecx

           shr eax, 8

           and eax, 0x0f

           ret

.unknown:

           mov eax, 1

           cpuid

           mov [cpu_sign], eax

           mov [cpu_info],  ebx

           mov [cpu_caps],  edx

           mov [cpu_caps+4],ecx

           shr eax, 8

           and eax, 0x0f

           ret

endp

AMD_str    db "AuthenticAMD",0

align 4

           mov edi, 0xE0000

.pcibios_nxt:

           cmp dword[edi], '_32_' ; "magic" word

           je .BIOS32_found

.pcibios_nxt2:

           add edi, 0x10

           cmp edi, 0xFFFF0

           je .BIOS32_not_found

           jmp .pcibios_nxt

.BIOS32_found:			; magic word found, check control summ

           shl ecx, 4

           mov esi, edi

           xor eax, eax

           cld   ; paranoia

@@:	lodsb

           add ah, al

           loop @b

           jnz .pcibios_nxt2 ; control summ must be zero

    ; BIOS32 service found !

           mov ebp, [edi + 4]

           mov [bios32_entry], ebp

    ; check PCI BIOS present

           mov eax, '$PCI'

           xor ebx, ebx

           push cs  ; special for 'ret far' from  BIOS

           call ebp

           test al, al

           jnz .PCI_BIOS32_not_found

           dec ecx

           mov [(pci_code_32-OS_BASE)], cx    ;limit 0-15

           mov [(pci_data_32-OS_BASE)], cx    ;limit 0-15

           mov [(pci_data_32-OS_BASE)+2], bx  ;base  0-15

           mov [(pci_code_32-OS_BASE)+4], bl  ;base  16-23

           mov [(pci_data_32-OS_BASE)+4], bl  ;base  16-23

           and cl, 0x0F

           mov ch, bh

           add cx, D32

           mov [(pci_code_32-OS_BASE)+6], cx  ;lim   16-19 &

           mov [(pci_data_32-OS_BASE)+6], cx  ;base  24-31

         ; jmp .end

.PCI_BIOS32_not_found:

	; çäåñü äîëæíà çàïîëíÿòñÿ pci_emu_dat

.BIOS32_not_found:

.end:

           ret

cpu_sign          rd 1

cpu_info          rd 1

cpu_caps          rd 4