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1463 | art_zh | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; ;; |
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7 | ;; PCIe.INC ;; |
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8 | ;; ;; |
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9 | ;; Extended PCI express services ;; |
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10 | ;; ;; |
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1560 | art_zh | 11 | ;; art_zh |
1463 | art_zh | 12 | ;; ;; |
13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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14 | |||
1560 | art_zh | 15 | $Revision: 1554 $ |
1463 | art_zh | 16 | |
17 | ;*************************************************************************** |
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18 | ; Function |
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19 | ; pci_ext_config: |
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20 | ; |
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21 | ; Description |
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22 | ; PCIe extended (memory-mapped) config space detection |
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23 | ; |
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1560 | art_zh | 24 | ; WARNINGs: |
25 | ; 1) Very Experimental! |
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26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
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27 | ; 3) Only AMD/HT processors currently supported |
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1463 | art_zh | 28 | ; |
29 | ;*************************************************************************** |
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30 | |||
1551 | art_zh | 31 | align 4 |
1560 | art_zh | 32 | mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
33 | mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
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34 | mmio_pcie_cfg_pdes dw 1 ; number of PDEs to map the space |
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35 | PCIe_bus_range dw 2 ; the Bus range: power-of-2 Megabytes |
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1463 | art_zh | 36 | |
37 | |||
38 | align 4 |
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39 | pci_ext_config: |
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1560 | art_zh | 40 | mov eax, [mmio_pcie_cfg_addr] |
41 | mov ebx, eax |
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42 | or ebx, ebx |
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1487 | art_zh | 43 | jz @f |
1560 | art_zh | 44 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
1487 | art_zh | 45 | jnz .pcie_failed |
46 | add ebx, 0x0FFFFC |
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47 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
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48 | ja .pcie_failed |
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1560 | art_zh | 49 | ret ; return the address forced |
1487 | art_zh | 50 | @@: |
51 | mov ebx, [cpu_vendor] |
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52 | cmp ebx, dword [AMD_str] |
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53 | jne .pcie_failed |
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1463 | art_zh | 54 | mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
55 | |||
56 | .check_HT_mmio: |
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57 | mov cx, bx |
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58 | mov ax, 0x0002 ; bus = 0, 1dword to read |
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1560 | art_zh | 59 | call pci_read_reg |
1463 | art_zh | 60 | mov bx, cx |
61 | sub bl, 4 |
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1560 | art_zh | 62 | and al, 0x80 ; check the NP bit |
1487 | art_zh | 63 | jz .no_pcie_cfg |
1560 | art_zh | 64 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
65 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
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66 | ; mov [mmio_pcie_cfg_lim], eax |
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1463 | art_zh | 67 | mov cl, bl |
68 | mov ax, 0x0002 ; bus = 0, 1dword to read |
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1560 | art_zh | 69 | call pci_read_reg |
1463 | art_zh | 70 | mov bx, cx |
71 | test al, 0x03 ; MMIO Base RW enabled? |
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1487 | art_zh | 72 | jz .no_pcie_cfg |
1463 | art_zh | 73 | test al, 0x0C ; MMIO Base locked? |
1487 | art_zh | 74 | jnz .no_pcie_cfg |
1463 | art_zh | 75 | xor al, al |
76 | shl eax, 8 |
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1560 | art_zh | 77 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
1487 | art_zh | 78 | jnz .no_pcie_cfg |
1463 | art_zh | 79 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
1560 | art_zh | 80 | |
1487 | art_zh | 81 | .no_pcie_cfg: |
1463 | art_zh | 82 | xor eax, eax |
83 | mov [mmio_pcie_cfg_addr], eax |
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84 | mov [mmio_pcie_cfg_lim], eax |
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85 | add bl, 12 |
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86 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
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87 | jb .check_HT_mmio |
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1560 | art_zh | 88 | |
1487 | art_zh | 89 | .pcie_failed: |
1683 | art_zh | 90 | jmp $ |
91 | ; xor eax, eax |
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92 | ; ret ; <<<<<<<<< FAILURE >>>>>>>>> |
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1463 | art_zh | 93 | |
1599 | art_zh | 94 | |
95 | ;-------------------------------------------------------------------------- |
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96 | ; this routine is platform-specific and used to change some BIOS settengs |
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97 | ; pcie_init_gfx |
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98 | ; sets the GPP mode of GFX bus |
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99 | |||
100 | |||
101 | ; this option disables external graphics |
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102 | pcie_init_gfx: |
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103 | |||
104 | ret><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<><<<<<<<<<><<<<<<<<<<> |