Subversion Repositories Kolibri OS

Rev

Rev 1560 | Rev 1641 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
1463 art_zh 1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2
;;                                                              ;;
3
;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
4
;; Distributed under terms of the GNU General Public License    ;;
5
;;                                                              ;;
6
;;                                                              ;;
7
;;  PCIe.INC                                                    ;;
8
;;                                                              ;;
9
;;  Extended PCI express services                               ;;
10
;;                                                              ;;
1560 art_zh 11
;;                  art_zh                  ;;
1463 art_zh 12
;;                                                              ;;
13
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
 
1560 art_zh 15
$Revision: 1554 $
1463 art_zh 16
 
17
;***************************************************************************
18
;   Function
19
;      pci_ext_config:
20
;
21
;   Description
22
;       PCIe extended (memory-mapped) config space detection
23
;
1560 art_zh 24
;   WARNINGs:
25
;       1) Very Experimental!
26
;       2) direct HT-detection (no ACPI or BIOS service used)
27
;       3) Only AMD/HT processors currently supported
1463 art_zh 28
;
29
;***************************************************************************
30
 
1551 art_zh 31
align 4
1560 art_zh 32
mmio_pcie_cfg_addr	dd	0x00000000	; pcie space may be defined here
33
mmio_pcie_cfg_lim	dd	0x000FFFFF	; upper pcie space address
34
mmio_pcie_cfg_pdes	dw	1		; number of PDEs to map the space
35
PCIe_bus_range		dw	2		; the Bus range: power-of-2 Megabytes
1463 art_zh 36
 
37
 
38
align 4
39
pci_ext_config:
1560 art_zh 40
	mov	eax, [mmio_pcie_cfg_addr]
41
	mov	ebx, eax
42
	or	ebx, ebx
1487 art_zh 43
	jz	@f
1560 art_zh 44
	or	ebx, 0x7FFFFFFF 	; required by PCI-SIG standards
1487 art_zh 45
	jnz	.pcie_failed
46
	add	ebx, 0x0FFFFC
47
	cmp	ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
48
	ja	.pcie_failed
1560 art_zh 49
	ret				; return the address forced
1487 art_zh 50
@@:
51
	mov	ebx, [cpu_vendor]
52
	cmp	ebx, dword [AMD_str]
53
	jne	.pcie_failed
1463 art_zh 54
	mov	bx, 0xC184		; dev = 24, fn = 01, reg = 84h
55
 
56
.check_HT_mmio:
57
	mov	cx, bx
58
	mov	ax, 0x0002		; bus = 0, 1dword to read
1560 art_zh 59
	call	pci_read_reg
1463 art_zh 60
	mov	bx, cx
61
	sub	bl, 4
1560 art_zh 62
	and	al, 0x80		; check the NP bit
1487 art_zh 63
	jz	.no_pcie_cfg
1560 art_zh 64
	shl	eax, 8			; bus:[27..20], dev:[19:15]
65
	or	eax, 0x00007FFC 	; fun:[14..12], reg:[11:2]
66
;       mov     [mmio_pcie_cfg_lim], eax
1463 art_zh 67
	mov	cl, bl
68
	mov	ax, 0x0002		; bus = 0, 1dword to read
1560 art_zh 69
	call	pci_read_reg
1463 art_zh 70
	mov	bx, cx
71
	test	al, 0x03		; MMIO Base RW enabled?
1487 art_zh 72
	jz	.no_pcie_cfg
1463 art_zh 73
	test	al, 0x0C		; MMIO Base locked?
1487 art_zh 74
	jnz	.no_pcie_cfg
1463 art_zh 75
	xor	al, al
76
	shl	eax, 8
1560 art_zh 77
	test	eax, 0x000F0000 	; MMIO Base must be bus0-aligned
1487 art_zh 78
	jnz	.no_pcie_cfg
1463 art_zh 79
 
1560 art_zh 80
;       -- it looks like a true PCIe config space;
1463 art_zh 81
 
82
	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
1560 art_zh 83
 
1487 art_zh 84
.no_pcie_cfg:
1463 art_zh 85
	xor	eax, eax
86
	mov	[mmio_pcie_cfg_addr], eax
87
	mov	[mmio_pcie_cfg_lim],  eax
88
	add	bl, 12
89
	cmp	bl, 0xC0		; MMIO regs lay below this offset
90
	jb	.check_HT_mmio
1560 art_zh 91
 
1487 art_zh 92
.pcie_failed:
1508 art_zh 93
	mov	esi, boot_pcie_fail
94
	call	boot_log
1463 art_zh 95
	ret	; <<<<<<<<< FAILURE >>>>>>>>>
96
 
1599 art_zh 97
 
98
;--------------------------------------------------------------------------
99
; this routine is platform-specific and used to change some BIOS settengs
100
; pcie_init_gfx
101
;       sets the GPP mode of GFX bus
102
 
103
 
104
;       this option disables external graphics
105
pcie_init_gfx:
106
 
107
	 ret