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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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;; ;; |
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;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;; |
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;; Distributed under terms of the GNU General Public License ;; |
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;; ;; |
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;; ;; |
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;; PCIe.INC ;; |
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;; ;; |
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;; Extended PCI express services ;; |
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;; ;; |
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;; Author: ;; |
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;; art_zh ;; |
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;; ;; |
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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$Revision: 1463 $ |
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;*************************************************************************** |
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; Function |
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; pci_ext_config: |
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; |
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; Description |
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; PCIe extended (memory-mapped) config space detection |
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; |
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; WARNINGs: |
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; 1) Very Experimental! |
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; 2) direct HT-detection (no ACPI or BIOS service used) |
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; 3) Only AMD/HT processors currently supported |
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; |
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;*************************************************************************** |
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PCIe_CONFIG_SPACE equ 0xF0000000 ; to be moved to const.inc |
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mmio_pcie_cfg_addr dd 0x0 ; not defined by default |
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mmio_pcie_cfg_lim dd 0x0 ; each bus needs 1Mb |
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align 4 |
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pci_ext_config: |
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push ebx |
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mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
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.check_HT_mmio: |
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mov cx, bx |
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mov ax, 0x0002 ; bus = 0, 1dword to read |
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call pci_read_reg |
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mov bx, cx |
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sub bl, 4 |
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and al, 0x80 ; check the NP bit |
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jz .not_pcie_cfg |
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shl eax, 8 ; bus:[27..20], dev:[19:15] |
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or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
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mov [mmio_pcie_cfg_lim], eax |
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mov cl, bl |
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mov ax, 0x0002 ; bus = 0, 1dword to read |
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call pci_read_reg |
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mov bx, cx |
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test al, 0x03 ; MMIO Base RW enabled? |
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jz .not_pcie_cfg |
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test al, 0x0C ; MMIO Base locked? |
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jnz .not_pcie_cfg |
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xor al, al |
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shl eax, 8 |
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; test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
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; jnz .not_pcie_cfg |
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mov [mmio_pcie_cfg_addr], eax |
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add eax, 0x000FFFFC |
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sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
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ja .not_pcie_cfg |
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; -- it looks like a true PCIe config space; |
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mov eax,[mmio_pcie_cfg_addr] ; physical address |
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or eax, (PG_SHARED + PG_LARGE + PG_USER) |
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mov ebx, PCIe_CONFIG_SPACE ; linear address |
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mov ecx, ebx |
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shr ebx, 20 |
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add ebx, sys_pgdir ; PgDir entry @ |
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@@: |
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mov dword[ebx], eax ; map 4 buses |
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invlpg [ecx] |
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cmp bl, 4 |
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jz .pcie_cfg_mapped ; fix it later |
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add bl, 4 ; next PgDir entry |
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add eax, 0x400000 ; eax += 4M |
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add ecx, 0x400000 |
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jmp @b |
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.pcie_cfg_mapped: |
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; -- glad to have the extended PCIe config field found |
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mov esi, boot_pcie_ok |
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pop ebx |
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call boot_log |
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ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
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.not_pcie_cfg: |
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xor eax, eax |
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mov [mmio_pcie_cfg_addr], eax |
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mov [mmio_pcie_cfg_lim], eax |
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add bl, 12 |
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cmp bl, 0xC0 ; MMIO regs lay below this offset |
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jb .check_HT_mmio |
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mov esi, boot_pcie_fail |
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pop ebx |
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call boot_log |
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ret ; <<<<<<<<< FAILURE >>>>>>>>> |
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